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3, MAY 2006
AbstractInterleaving technique is used in some applications decrease the voltage stress in the transistors and to eliminate
due to its advantages regarding filter reduction, dynamic response, the inductor. Finally, a procedure to design this type of power
and power management. In dual battery system vehicles, the bidi- converter based on models implemented in Matlab is shown in
rectional dcdc converter takes advantage of this technique using
three-to-five paralleled buck stages. [7]. References [2] and [3] are deeply analyzed and compared
In this paper, we propose the use of a much higher number of in Table II.
phases in parallel together with digital control. It will be shown Using interleaving, the power stage of a converter is divided
that this approach opens new possibilities since changes in the tech- into several and smaller power stages. Therefore, the size of
nology are possible. Thus, two 1000-W prototypes have been de- each component is reduced. With a very high number of inter-
signed using surface mount technology devices (SO-8 transistors).
An additional important feature is that due to the accuracy of the leaved phases, the current stress is greatly reduced and using a
digital device [field-programmable gate array (FPGA)], current different technology becomes a possibility. This change of tech-
loops have been eliminated, greatly simplifying the implementa- nology may bring several advantages:
tion of the control stage. power converter is made of surface mount technology
Index TermsDigital control, field-programmable gate array (SMT) components;
(FPGA), surface mount technology (SMT). automatic assembly;
absence of heatsinks (usually heatsinks require manual as-
sembly);
I. INTRODUCTION magnetic components can be planar or SMT. Repetitivity
is greatly increased;
A UTOMOTIVE electronics are one field of power elec-
tronics that has been growing rapidly in recent years.
Some good examples of this are the electronics involved in the
very small input and output filters.
However, there are some challenges to face a many-phases
dual battery system vehicles that use 14-V and 42-V batteries. converter.
One of the specific converters for these vehicles is the bidi- General purpose integrated circuits (ICs) cannot be used
rectional module placed in between those batteries that is in because there are many phases. Specific digital control is
charge of the power flow. Typically, the power of this converter required.
ranges from 500 to 1000 W. Due to the relative high current Introducing a current loop per phase will not be cost-effec-
of this application, some approaches use the interleaving tech- tive. Passive current equalization should be considered.
nique [1]. The main advantages of using this technique in this In this paper, two multiphase dc/dc converters made of many
application are the filters reduction and efficiency. State of the interleaved phases (16 and 36) for automotive application are
art engineering for this application proposes the use of three proposed. Apart from the aforementioned advantages, the mea-
to five paralleled buck stages (phases) to build the converter sures in the prototypes show a very good efficiency (94%95%)
[2][5]. A comparison between this multiphase converter with a at full load (1000 W).
single buck converter is carried out in [2], where the advantage
of this technique for this application can be seen. Reference II. POWER STAGE DESIGN
[3] proposes a CAD tool to calculate the number of phases to The converter will be implemented using the synchronous
optimize cost, size, and weight. A similar analysis, but more buck configuration because it is suitable for this specification
oriented to calculate power losses, can be found in [4]. A and it is used for most of the authors [2][5]. It has bidirec-
magnetic component to couple all the phases is introduced in tional capability and efficiency is quite good. No isolation is
[5], obtaining a size reduction compared with inductors for needed between both batteries and therefore, topologies with
the same power losses. A quite different solution is presented transformers are unnecessary. Fig. 1 shows a multiphase syn-
in [6], where the authors propose a multilevel converter to chronous buck dc/dc converter.
The design has been guided by the compromise of using SMT
Manuscript received March 9, 2005; revised October 26, 2005. This work components. The number of phases has been selected to reduce
was presented in part at PESC04 and APEC05. Recommended by Associate
Editor J. Shen.
the dc current enough to use small transistors. Thus, two de-
O. Garca, A. de Castro, and J. A. Cobos are with the Divisin de Inge- signs have been considered as shown in Table I. In the first
niera Electrnica, Universidad Politcnica de Madrid, Madrid 28006, Madrid. one, with 16 phases, each metal-oxide-semiconductor field-ef-
(e-mail: o.garcia@upm.es). fect transistor (MOSFET) needs a SO-8 case while the second,
P. Zumel is with the Departamento de Tecnologa Electrnica, Universidad
Carlos III de Madrid, Madrid, Spain. with 36 phases, has its two MOSFETs of each phase in the same
Digital Object Identifier 10.1109/TPEL.2006.872379 SO-8 case.
0885-8993/$20.00 2006 IEEE
GARCA et al.: AUTOMOTIVE DCDC BIDIRECTIONAL CONVERTER 579
TABLE II
COMPARISON OF SEVERAL DC/DC CONVERTERS FOR THE SAME APPLICATION BUT WITH DIFFERENT NUMBER OF INTERLEAVED PHASES
Another advantage of interleaving is ripple cancellation [9]. The same can be said about the inductors, obtaining a small
With a very high number of phases, the current ripple at the size for Design II. Even with 36 phases, the total inductor
output is nearly negligible at every input voltage. Therefore, the volume is smaller compared with the others designs.
output capacitor is really small. Output capacitance: with 16 interleaved phases, there is a
Table II shows a comparison among several designs for the very high ripple cancellation for every duty cycle. How-
automotive 42/14-V bidirectional converter. All of them have ever, the tolerances in the inductance forces one to use a
been designed for 1000 W. Single phase design is theoretical; relatively large output capacitor (the authors do not know
state of the art columns are taken from [2] and [3] (data between if previous works have considered this phenomenon). This
brackets are estimations); finally, the last two columns with the effect is much smaller in the 36-phase converter where a
proposed designs have been included. Other examples [4], [5] small filter is obtained.
designed for smaller amounts of power (400500 W) also use a Two differential features are common to these two designs:
small number of phases such as 3 or 4. first, they do not use commercial ICs to control, but specific
Regarding this table, some comments can be made. circuits using digital devices; second, no heatsinks are used
The higher the number of phases, the smaller the MOSFET in them. This is one of the most important differences be-
size. A high number of phases allows the use of SMT tran- cause it simplifies the constructive process and reduces the
sistors. Moreover, with a proper design heatsinks can be cost.
avoided. Efficiency in the proposed designs is very high.
GARCA et al.: AUTOMOTIVE DCDC BIDIRECTIONAL CONVERTER 581
Fig. 5. (a) Shift-register hardware structure and (b) its workings. Fig. 6. Equivalent dc circuit of the multiphase buck converter working in CCM.
delays are equivalent to the desired phase-shifting operation [see sistance is the input voltage multiplied by the actual duty
Fig. 5(b)]. cycle of this phase .
In case of passive load , the output voltage of the con-
C. Phase-Shifters Comparison verter can be calculated from the aforementioned param-
eters ( , , and ) with the following expression:
Three comparison criteria can be used to distinguish between
these two solutions.
Duty cycle resolution. The shift-register method leads to
shorter critical paths. Therefore, higher clock frequency
(2)
can be achieved and, as a consequence, duty cycle reso-
lution can be increased.
Closed-loop dynamics. Using addition and compar-
ison phase-shifters, duty cycle changes start affecting Note that if the load is a battery, the output voltage is just
all driving signals immediately, while for shift-register the battery voltage and (2) is not used. Once is known, the
phase-shifters these changes only affect the first phase current through each phase is easily calculated
immediately. The rest of the phases are affected only after
a time equal to their delay. Therefore, somewhat higher
(3)
closed-loop dynamics is achieved with the addition and
comparison method.
Area. The addition and comparison phase-shifter is very The worst-case for a single phase takes place when this phase
sensitive to the number of phases, as each phase needs its has the maximum duty cycle and the minimum resistance while
own adder and comparator. The shift-register phase-shifter the rest have minimum duty cycle and maximum resistance.
is not sensitive to the number of phases, as including more In such a case, the phase current is maximum while the other
phases needs is just extracting more driving signals from phases will handle a current below the average value . In
the already available shift-register. However, it is sensitive order to determine which of both factors (differences in duty
to the duty cycle resolution, as the length of the shift-reg- cycle or in resistance) is the most important, we can analyze
ister is proportional to it. each one independently. This analysis can be found in detail in
[13], but the main results are the following ones. The differences
caused by resistance unbalance when only one resistance is dif-
IV. CURRENT SHARING
ferent from the others can be calculated as shown in
One of the concerns of the interleaved converters is current
sharing. Commercial integrated circuits solve this problem by
including an additional current loop [11], [12]. As a conse- (4)
quence, the cost of the IC is quite high. Also, the additional
circuitry grows, increasing size and decreasing reliability. being the common resistance for the rest of the phases and
Therefore, although the aforementioned IC controllers have the difference in the unbalanced resistance. On the other
been designed with the capability of paralleling some of them, hand, the differences caused by duty cycle unbalance when only
in practice, a high number of phases is not feasible. one duty cycle is different from the others can be calculated as
The purpose of this paper is to use a high number of phases shown in
but without any current loop. The dc current depends strongly
on the conduction mode of the converter.
(5)
A. Continuous Conduction Mode (CCM)
Fig. 6 shows the equivalent dc circuit of a multiphase buck being the common duty cycle for the rest of the phases,
converter when it operates in CCM. Each phase is characterized the difference in the unbalanced duty cycle, and the power
by a dc parasitic resistance ; the voltage applied to this re- efficiency due to losses on the resistance exclusively.
GARCA et al.: AUTOMOTIVE DCDC BIDIRECTIONAL CONVERTER 583
TABLE III
DC CURRENT VALUES IN DCM AND CCM
FOR 1% AND 5% DUTY CYCLE INEQUALITIES
Fig. 10. Prototype made with 16 phases: (a) single phase power stage and (b)
whole power stage.
B. Design II
The main characteristics of this prototype are as follows.
Number of phases: 36.
Power per phase: 27.7 W.
Phase switching frequency: 100 kHz.
Inductor per phase: 47 H (WE PD-47).
MOSFETs: IRF7341 (two transistors in a SO-8 package).
Driver: IR2181S (two drivers in a SO-8 package).
Compared with the previously presented prototype, the main
difference is that this design runs in CCM but with positive cur-
rent (current ripple is small compared to the dc current value).
In these conditions, the dc current through each phase is only
defined by the parasitic resistances and duty cycle inequalities
Fig. 9. Measured efficiency of Design I as a function of the output current. [see (3)]. Measured current waveforms in steady-state condi-
tions are shown in Fig. 11(a) and (c). Although no current loops
have been used, dc currents through each phase are quite sim-
Digital control, implemented in an FPGA. ilar even during transients as shown in Fig. 12 (only four phase
Two designs have been carried out. Design I with 16 phases currents are shown). All of them are in the range 10% at full
and Design II with 36. load. Fig. 11(b) and (d) shows the dc phase current values.
Design II has a maximum efficiency of 94% with 50 A and
A. Design I 93.5% at full load as shown in Fig. 13. A converter with 36
Main characteristics of this prototype are as follows. phases is shown in Fig. 14. The converter is composed of two
Number of phases: 16. stacked PCBs with a pair of connectors between. The first PCB
Power per phase: 62.5 W. contains the power transistors (on the top side) and the drivers
Phase switching frequency: 150 kHz. (bottom side); the second PCB includes the inductors and the
Inductor per phase: 5.4 H (RM7). output capacitors.
MOSFETs: SI4450DY (SO-8 package).
Driver: IR2181S (2 drivers in a SO-8 package). VI. CONCLUSION
The current per phase at full load is shown in Fig. 8. It can The interleaving technique has several advantages such as fil-
be seen that the current ripple is high enough to achieve zero- ters reduction, better dynamic response, and better thermal man-
voltage switcing (ZVS) in both transitions. In these conditions, agement. Besides the classical approach, using a high number
the efficiency is maximum (it has been experimentally checked of phases brings other advantages. In particular, power compo-
[14]) and a good current balance is achieved. This prototype has nents can be SMD and/or inductors can be integrated in the PCB.
been tested in CCM and DCM to see the performance about Thus, the converter is repetitivity increased, the assembly can be
current unbalance [15]. The main conclusion is that DCM is automatic, and even heatsinks can be removed.
much better than CCM but, thanks to the accuracy of the digital In this paper, two multiphase 1000-W dcdc converters made
control, the equilibrium in CCM is quite good. of many interleaved buck phases (16 and 36) are proposed.
GARCA et al.: AUTOMOTIVE DCDC BIDIRECTIONAL CONVERTER 585
Fig. 11. (a) Measured current waveforms and (b) dc value in the 36-phases prototype at half-load; same in (c) and (d) but at full load.
Fig. 13. Efficiency of the converter with 36 phases as a function of the output
current.
Fig. 12. Evolution of four phase currents of the converter during a transient.