Volume 2, Issue 11, November 2017 International Journal of Innovative Science and Research Technology

ISSN No:-2456 2165

High Area Efficient Spanning Tree Based Modified

Booth Multiplier Design for Fir Filter Using Cadence
T.Revathi S. Jayasudha Dr.N.J.R.Muniraj
Associate Professor, Department of PG Scholar, Department of ECE, Principal, Tejaa Shakthi Institute of
ECE, Tejaa Shakthi Institute of Tejaa Shakthi Institute of Technology Technology for Women, Coimbatore,
Technology for Women, Coimbatore, for Women, Coimbatore, Tamilnadu-641659.
Tamilnadu-641659. Tamilnadu-641659. ENjrmuniraj@Yahoo.Co.In
Srksuresh@Gmail.Com Revathireva112@Gmail.Com.

Abstract: Now a day the finite impulse response (FIR)
filters are extensively used in various digital signal
processing applications. Such as digital audio, data
transmission etc... there are several techniques are used to
the FIR filter circuit must be capable to operate at high
sample rate and must be a low power circuit are operating
at moderate sample rates.To design and implement the
modified booth multiplier for fast computation with less
energy and area consumption.Now we proposed an high
area efficient spanning tree based booth multiplier design
for FIR filter.These techniques were employed to
optimized the excessive area and power consumption for
large multiplication using spanning tree based modified
booth multiplier in FIR filter design.The design was
implemented in cadence technology and its optimized the
total area efficient .The spanning tree based modified
booth multiplier used to consuming highly area efficient
and low power for FIR filter.
Keywords:- FIR Filter; Modified Booth Multiplier, Spanning
Tree.
I. INTRODUCTION
The digital filters are very important port of digital signal
processing. To the advanced technology with digital filters are
most used function in multiplication. The proposed technique
to design multipliers are high speed and low power
consumption and lesser area to implementation of VLSI
technique. To using design of fixed width multipliers with
linear compensation function topologies are exhibit better
accuracy.The high accuracy fixed width modified booth
multipliers for application using to save area,power and
increment in speed the modified booth multiplier is used to
instead of baughwolley multiplier and also used to speedup the
multiplication carry lookahead adder is used as a carry
propagate adder.To increase the speed mostly used in larger
areas.Therefore,compromise the improve the speed of the
circuit for a larger improvement in reduction of space and
power . The multiplier based on modified booth algorithm and
Wallace addition is one of the fast and low power multiplier.
The FIR filter design are based on spanning tree based
modified booth multiplier.Area of modified booth Wallace
multiplier can further be improved by using a modified booth
multiplier. In FIR filter the modified booth multiplier is the
major constraint which defines the performance of the desired
filter usually booth multiplier and modified booth multipliers
are used for good performance.
II. LITERATURE SURVEY
Speculative functional units are arithmetic functional units that
operate using a predictor for the carry signal. The carry
prediction helps to shorten the critical path of the functional
unit; the average case performance of these units is determined
by the hit rate of the prediction. The Dism is used to optimize
the FUS and register binding boost execution time. The data
path utilizing both linear structure and logarithmic structure
for speculative arithmetic functional units So, its possible to
reduce the execution time for logarithmic structure and linear
structure [2]. The design of fixed width multipliers with linear
compensation functions by investigating in detail with linear
compensation function. There are two topologies are used to
the fixed width multipliers in Uniform quantization and
non-uniform quantization To improving the power and speed
and reduce the circuit complexity [3].The high accuracy fixed
width modified booth multipliers for lossy application
described on adaptive conditional probability estimator fixed
width modified booth multiplier, which can be easily applied
to large length booth multiplier for achieving higher accuracy
performance. To save the area and power and increment in
speed the modified booth multiplier is used to instead of
baugh wolley multiplier and also speedup the multiplication.
The multipliers are applicable to lossy applications to reduce
the area and power consumptions [4].

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Volume 2, Issue 11, November 2017 International Journal of Innovative Science and Research Technology
ISSN No:-2456 2165

The fixed width modified booth multiplier using generalized signals and respective filter co efficient, followed by the
probalistic estimation bias(GPEB) booth multiplier are accumulation of all the products .accumulation is also done by
implemented in the circuit of using 2D-DCT to reduce the area using a modified spanning tree adder is used for previous
cost. The GPEB booth multiplier can achieve the higher technique in final addition .A modified spanning tree
accuracy and most power efficiency. The 2D DCT multiplier is developed here such that it enhances the
implementation with the GPEB booth multiplier is achieved performance further. To design a low area cost FIR filter with
by the PSNR and area cost. The GPEB fixed width booth the advantages of reduced power consumption and moderate
multipliers have low hardware cost and low power speed performance. To design and implement the modified
consumption while achieving high accuracy [5]. The ACPE is booth algorithm and Wallace addition is one of the fast and
applied to the fixed width booth multiplier is proposed .The low power .Multiplier for high speed applications, to furthere
ACPE can be easily applied to large length booth multipliers improved the booth Wallace multiplier by using a spanning
for achieving a higher accuracy performance. tree based modified booth multiplier. The booth multiplier
algorithm or the method of multiplying binary numbers in
To described a single compensation formula of ACPE
twos complement notation.Modified booth multiplier is an
adaptive conditional probabilistic estimate applied to fixed
extension of booth multiplier .Multiplier architecture consists
width booth multiplier is proposed.To achieving a higher
of booth encoder,partial product generator ,Wallace tree and a
accuracy performance based on the conditional probability
modified spanning tree parallel prefix adder. The modified
theory[6].The VLSBM (variable latency speculating booth
booth algorithm which encodes the multiplier bits and the
multiplier) is a high speed and energy efficient to perform a
partial product generator produces the partial products by
speculating and correcting phase. To reduce the critical path
operating on multiplicand.This will reduce the number of
and least significant part (LSP) and most significant part
partial products.
(MSP) and an estimation function stochastically predicts the
carry to the MSP, thereby allowing Independent calculation
of the partial product accumulation of parts.[7].The low cost
FIR filter designs by jointly considering the optimization of
co-efficient bit width and hardware resources in
implementation. To increase the speed and to reduce the
complexity of FIR filter, they implemented by using vedic
multiplier [8]. The parallel prefix adder are known to have the
best performance in VLSI design.This performance advantage
does not translate directly into FPGA implementations due to
constraints on logic block configuration and routing overhead.
The parallel prefix adders are using to increase the speed and
to reduce the power[11]. Parallel prefix adder is the most
flexible and widely used for binary addition. Parallel prefix
tree is an approach to redesign the basic operator used in
parallel prefix architecture. The area requirement can be
considered from the utilization of LUTS and slices and overall
gate count [12]. The high speed arithmetic in binary
computers obtaining high speed in addition, multiplication and
division in parallel binary computers are described and then
compared with each other as to efficiency of operation and
cost [9].The modified booth multiplier algorithm is an
algorithm which multipliers two signed binary numbers in
twos complement notation. For designing a lower error and
area efficient 2s complement fixed width booth multiplier
that receives two n-bit numbers and produces an n-bit product.
The unified signed and unsigned multiplier was optimized in
terms of speed, power consumption [13].

III. PROPOSED SYSTEM

The spanning tree based modified booth multiplier module Figure 1 RTL View of Booth Multiplier
performs the concurrent multiplications of individual delayed

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Volume 2, Issue 11, November 2017 International Journal of Innovative Science and Research Technology
ISSN No:-2456 2165

A. Spanning Tree Based Modified Booth Multiplier:
speed comparison is done using the timing report obtained in
the synthesis report. While comparing filters using spanning
tree based modified booth multiplier is consuming lesser area
.The Xilinx ISE 14.2 software was used to synthesize the
design onto the Spartan 3E device.The spanning tree based
modified booth multiplier and booth multiplier design has
been performed by using the CADENCE tool.The simulation
results obtained for the two FIR filters ,namely FIR filter using
spanning tree based modified booth multiplier and booth
multiplier.

Figure 3 Output Waveform of Fir Filter Based on Booth

Multiplier
Figure 2 RTL View of Modified Booth Multiplier

The comparison for the conventional FIR filter using Booth

The booth multiplier makes use of booth encoding algorithm multiplier and modified booth multiplier are shown in a
in order to reduce the number of partial products by table1.
processing three at a time during recoding. Tress are an
FIR filter topology Booth multiplier Modified booth
extremely fast structure for summing products.spanning tree
multiplier
based FIR filter consumes less power than that of existing FIR
filter.The reduction in number of gates accounted for the No of slices 28 96
reduction in power in spanning tree based FIR filter. The No of slice of flip- 28 28
multipliers have the four types of main characteristics in area, flops
accuracy, speed, and speed. The spanning tree to use
minimum number of multi input gates and hybrid adder. No of I/P LUTS 45 175
Therefore proposed FIR filter using modified spanning tree No of IOBs 35 33
based modified booth multiplier is high area efficient when
compared with other two FIR filters.

Table 1: Comparison Area of Booth and Modified Booth

IV. SIMULATION AND RESULT Multiplier

The symmetric form structure of proposed FIR filter is
implemented.In this chapter the simulation result of all the
circuit has been placed. The FIR filter using spanning tree
based modified booth multiplier has been implemented.The
booth multiplier and modified booth multiplier coding
simulated result in compare the power and area,gates and
The comparisons for the results are shown in the form of
graphical view. When the power reduction will be more in
multiplier, while comparing with simple spanning tree based
modified booth multiplier power estimation.

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Volume 2, Issue 11, November 2017 International Journal of Innovative Science and Research Technology
ISSN No:-2456 2165

Analysis Booth multiplier Modified Booth

multiplier
BOOTH MULTIPLIER MODIFIED BOOTH
200000
Gate 95 401
180000
Power 34300.811 196179.955 160000
140000
Area 984 3685 120000
100000
80000

Table 2: Performance Comparison 60000

40000
20000
0
Gate Power Area

Figure 6 Performance Comparison

V. CONCLUSION

In the design of FIR filter using spanning tree based modified

booth multiplier and booth multiplier implementation. A
highly area efficient FIR filter using spanning tree based
modified booth multiplier is designed based on the symmetric
form realization.By employing spanning tree booth multiplier
and spanning tree based modified booth multiplier in FIR
Figure 4 Output Waveform of Fir Filter on Modified Booth filter ,area is optimized by 984 and 3685 respectively and
Multiplier power is reduced . The target devices for booth and spanning
tree based modified booth multiplier are same in XILINX.
Everything has been done in the cadence. This tool it is easy to
analysis output of the circuit. For further improvement of high
area efficient and power characteristics of multipliers.

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Volume 2, Issue 11, November 2017 International Journal of Innovative Science and Research Technology
ISSN No:-2456 2165

[4]. Yuan-Ho Chen, T-Y, chang and C-Y.Li, Area-effective

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