LUT-DA PROGRAM

LIBRARY ieee; -- Using predefined packages

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY too IS ------> Interface

PORT (clk : IN STD_LOGIC;

x0_in, x1_in, x2_in,x3_in :

IN STD_LOGIC_VECTOR(3 DOWNTO 0);

lut : OUT INTEGER RANGE 0 TO 500;

y : OUT INTEGER RANGE 0 TO 1000);

END too;

ARCHITECTURE fpga OF too IS

COMPONENT tt -- User-defined component

PORT ( table_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

table_out : OUT INTEGER RANGE 0 TO 1000);

END COMPONENT;

TYPE STATE_TYPE IS (s0, s1);

SIGNAL state : STATE_TYPE;

SIGNAL x0, x1, x2,x3, table_in

: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL table_out : INTEGER RANGE 0 TO 1000;

BEGIN

table_in(0) <= x0(0);

table_in(1) <= x1(0);

table_in(2) <= x2(0);

table_in(3) <= x3(0);

PROCESS ------> DA in behavioral style

VARIABLE p : INTEGER RANGE 0 TO 1000;-- temp. register

VARIABLE count : INTEGER RANGE 0 TO 4; -- counts shifts

BEGIN

wait on clk;

CASE state IS

WHEN s0 =>

state <= s1;

count := 0;

p := 0;

x0 <= x0_in;

x1 <= x1_in;

x2 <= x2_in;

x3 <= x3_in;

WHEN s1 =>

IF count = 4 THEN

y <= p;

state <= s0;

else

p := p / 2 + table_out * 8;

x0(0) <= x0(1);

x0(1) <= x0(2);

x0(2) <= x0(3);

x1(0) <= x1(1);

x1(1) <= x1(2);

x1(2) <= x1(3);

x2(0) <= x2(1);

x2(1) <= x2(2);

x2(2) <= x2(3);

x3(0) <= x3(1);

x3(1) <= x3(2);

x3(2) <= x3(3);

count := count + 1;

state <= s1;

end if;

END CASE;

END PROCESS;

LC_Table0: tt

PORT MAP(table_in => table_in, table_out => table_out);

lut <= table_out; -- Extra test signal

END fpga;

COMPONENT CODE

LIBRARY ieee;USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY tt IS

PORT ( table_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

table_out : OUT INTEGER RANGE 0 TO 1000);

END tt;

ARCHITECTURE LEs OF tt IS

BEGIN

-- This is the DA CASE table for

-- the 3 coefficients: 1,1, 20, 27

-- automatically generated with dagen.exe -- DO NOT EDIT!

PROCESS (table_in)

BEGIN

CASE table_in IS

WHEN "0000" => table_out <= 0;

WHEN "0001" => table_out <= 27;

WHEN "0010" => table_out <= 20;

WHEN "0011" => table_out <= 47;

WHEN "0100" => table_out <= 1;

WHEN "0101" => table_out <= 28;

WHEN "0110" => table_out <= 21;

WHEN "0111" => table_out <= 48;

WHEN "1000" => table_out <= 1;

WHEN "1001" => table_out <= 28;

WHEN "1010" => table_out <= 21;

WHEN "1011" => table_out <= 48;

WHEN "1100" => table_out <= 2;

WHEN "1101" => table_out <= 29;

WHEN "1110" => table_out <= 22;

WHEN "1111" => table_out <= 49;

WHEN OTHERS => table_out <= 0;

END CASE;

END PROCESS;

END LEs;
 SIMULATION RESULT

h(K) ={27,20,1,1} , x(k)= {2,4,15,14}

H(k)={27,20,1,1} x(k)={3,8,7,9}
LUT-LESS DA

LIBRARY ieee; -- Using predefined packages

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY lless IS ------> Interface

PORT (clk,reset : IN STD_LOGIC;

x0_in, x1_in, x2_in,x3_in :

IN STD_LOGIC_VECTOR(3 DOWNTO 0);

lut : OUT INTEGER RANGE 0 TO 500;

y : OUT INTEGER RANGE 0 TO 1000);

END lless;

ARCHITECTURE fpga OF lless IS

COMPONENT lmux -- User-defined component

PORT ( clk:in std_logic;table_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

table_out : OUT INTEGER RANGE 0 TO 1000);

END COMPONENT;

TYPE STATE_TYPE IS (s0, s1);

SIGNAL state : STATE_TYPE;

SIGNAL x0, x1, x2,x3, table_in

: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL table_out : INTEGER RANGE 0 TO 1000;

BEGIN

table_in(0) <= x0(0);

table_in(1) <= x1(0);

table_in(2) <= x2(0);

table_in(3) <= x3(0);

PROCESS (reset,clk)------> DA in behavioral style

VARIABLE p : INTEGER RANGE 0 TO 1000;-- temp. register

VARIABLE count : INTEGER RANGE 0 TO 5; -- counts shifts

BEGIN

IF reset = '1' THEN -- asynchronous reset

state <= s0;

ELSIF rising_edge(clk) THEN

CASE state IS

WHEN s0 =>

state <= s1;

count := 0;

p := 0;

x0 <= x0_in;

x1 <= x1_in;

x2 <= x2_in;

x3 <= x3_in;

WHEN s1 =>

IF count = 5 THEN

y <= p;

state <= s0;

else

p := p / 2 + table_out * 8;

x0(0) <= x0(1);

x0(1) <= x0(2);

x0(2) <= x0(3);

x1(0) <= x1(1);

x1(1) <= x1(2);

x1(2) <= x1(3);

x2(0) <= x2(1);

x2(1) <= x2(2);

x2(2) <= x2(3);

x3(0) <= x3(1);

x3(1) <= x3(2);

x3(2) <= x3(3);

count := count + 1;

state <= s1;

end if;

END CASE;

end if;

END PROCESS;

LC_Table0:lmux

PORT MAP(clk=>clk,table_in => table_in, table_out => table_out);

lut <= table_out; -- Extra test signal

END fpga;

LUT-LESS COMPONENT PROGRAM

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

use ieee.std_logic_1164.std_logic;

ENTITY lmux IS

PORT (clk:in std_logic;table_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

table_out : OUT INTEGER RANGE 0 TO 1000);

END lmux;

ARCHITECTURE LEs OF lmux IS

SIGNAL lsbs : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL msbs0 : STD_LOGIC_vector(1 downto 0);

SIGNAL table0out00, table0out01 : INTEGER RANGE 0 TO 1000;

BEGIN

-- These are the distributed arithmetic CASE tables for

-- the 5 coefficients: 1 1 20 27

-- automatically generated with dagen.exe -- DO NOT EDIT!

PROCESS

BEGIN

wait on clk;

lsbs(0) <= table_in(0);

lsbs(1) <= table_in(1);

lsbs(2) <= table_in(2);

msbs0(0) <= table_in(3);

msbs0(1) <= msbs0(0);

END PROCESS;

PROCESS

-- This is the final DA MPX stage.

BEGIN

-- Automatically generated with dagen.exe

wait on clk;

CASE msbs0(1) IS

WHEN '0' => table_out <= table0out00;

WHEN '1' => table_out <= table0out01;

WHEN OTHERS => table_out <= 0;

END CASE;

END PROCESS;

PROCESS

-- This is the DA CASE table 00 out of 1.

BEGIN
-- Automatically generated with dagen.exe

wait on clk;

CASE lsbs IS

WHEN "000" => table0out00 <= 0;

WHEN "001" => table0out00 <= 27;

WHEN "010" => table0out00 <= 20;

WHEN "011" => table0out00 <= 47;

WHEN "100" => table0out00 <= 1;

WHEN "101" => table0out00 <= 28;

WHEN "110" => table0out00 <= 21;

WHEN "111" => table0out00 <= 48;

WHEN OTHERS => table0out00 <= 0;

END CASE;

END PROCESS;

PROCESS

-- This is the DA CASE table 01 out of 1.

BEGIN

-- Automatically generated with dagen.exe

wait on clk;

CASE lsbs IS

WHEN "000" => table0out01 <= 1;

WHEN "001" => table0out01 <= 28;

WHEN "010" => table0out01 <= 21;

WHEN "011" => table0out01 <= 48;

WHEN "100" => table0out01 <= 2;

WHEN "101" => table0out01 <= 29;

WHEN "110" => table0out01 <= 22;

WHEN "111" => table0out01 <= 49;

WHEN OTHERS => table0out01 <= 0;

END CASE;

END PROCESS;

end les;

SIMULATION RESULT

H(k)={27,20,1,1} x(k)={5,10,15,5}

H(k)={27,20,1,1} x(k)={3,8,7,9}
SIGNED LUT-DA SERIAL

LIBRARY ieee;

-- Using predefined packages

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY daserial IS ------> Interface

PORT (clk, reset : IN STD_LOGIC;

x_in0, x_in1, x_in2

: IN STD_LOGIC_VECTOR(3 DOWNTO 0);

lut : out INTEGER RANGE -2 TO 4;

y : OUT INTEGER RANGE -64 TO 63);

END serial;

ARCHITECTURE fpga OF daserial IS

COMPONENT dase -- User-defined components

PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

table_out : OUT INTEGER RANGE -2 TO 4);

END COMPONENT;

TYPE STATE_TYPE IS (s0, s1);

SIGNAL state : STATE_TYPE;

SIGNAL table_in : STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL x0, x1, x2 : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL table_out : INTEGER RANGE -2 TO 4;

BEGIN

table_in(0) <= x0(0);

table_in(1) <= x1(0);

table_in(2) <= x2(0);

PROCESS (reset, clk) ------> DA in behavioral style

VARIABLE p : INTEGER RANGE -64 TO 63:= 0; -- Temp. reg.

VARIABLE count : INTEGER RANGE 0 TO 4; -- Counts the

BEGIN -- shifts

IF reset = '1' THEN -- asynchronous reset

state <= s0;

ELSIF rising_edge(clk) THEN

CASE state IS

WHEN s0 => -- Initialization step

state <= s1;

count := 0;

p := 0;

x0 <= x_in0;

x1 <= x_in1;

x2 <= x_in2;

WHEN s1 =>

IF count = 4 THEN -- Is sum of product done?

y <= p; -- Output of result to y and

state <= s0; -- start next sum of product

ELSE

IF count = 3 THEN -- Subtract for last

p := p / 2 - table_out * 8; -- accumulator step

ELSE

p := p / 2 + table_out * 8; -- Accumulation for

END IF; -- all other steps

FOR k IN 0 TO 2 LOOP -- Shift bits

x0(k) <= x0(k+1);

x1(k) <= x1(k+1);

x2(k) <= x2(k+1);

END LOOP;
count := count + 1;

state <= s1;

END IF;

END CASE;

END IF;

END PROCESS;

LC_Table0: dase

PORT MAP(table_in => table_in, table_out => table_out);

lut <= table_out; -- Extra test signal

END fpga;

COMPONENT CODE

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY dase IS

PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

table_out : OUT INTEGER RANGE -2 TO 4);

END dase;

ARCHITECTURE LEs OF dase IS

BEGIN

-- This is the DA CASE table for

-- the 3 coefficients: -2, 3, 1

-- automatically generated with dagen.exe -- DO NOT EDIT!

PROCESS (table_in)

BEGIN

CASE table_in IS

WHEN "000" => table_out <= 0;

WHEN "001" => table_out <= -2;

WHEN "010" => table_out <= 3;

WHEN "011" => table_out <= 1;

WHEN "100" => table_out <= 1;

WHEN "101" => table_out <= -1;

WHEN "110" => table_out <= 4;

WHEN "111" => table_out <= 2;

WHEN OTHERS => table_out <= 0;

END CASE;

END PROCESS;

END LEs;

PARALLEL LUT-DA

LIBRARY ieee; -- Using predefined packages

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY parallel IS ------> Interface

PORT (clk : IN STD_LOGIC;

x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

y : OUT INTEGER RANGE -46 TO 44);

END parallel;

ARCHITECTURE fpga OF parallel IS

TYPE ARRAY4x3 IS ARRAY (0 TO 3)

OF STD_LOGIC_VECTOR(2 DOWNTO 0);

SIGNAL x : ARRAY4x3;

TYPE IARRAY IS ARRAY (0 TO 3) OF INTEGER RANGE -2 TO 4;

SIGNAL h : IARRAY;

SIGNAL s0 : INTEGER RANGE -6 TO 12;

SIGNAL s1 : INTEGER RANGE -10 TO 8;

SIGNAL t0, t1, t2, t3 : INTEGER RANGE -2 TO 4;

COMPONENT dapp

PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

table_out : OUT INTEGER RANGE -2 TO 4);

END COMPONENT;

BEGIN

PROCESS

------> DA in behavioral style

BEGIN

WAIT UNTIL clk = '1';

FOR l IN 0 TO 3 LOOP -- For all four vectors

FOR k IN 0 TO 1 LOOP -- shift all bits

x(l)(k) <= x(l)(k+1);

END LOOP;

END LOOP;

FOR k IN 0 TO 3 LOOP -- Load x_in in the

x(k)(2) <= x_in(k); -- MSBs of the registers

END LOOP;

y <= h(0) + 2 * h(1) + 4 * h(2) - 8 * h(3);

--Pipeline register and adder tree

t0 <= h(0); t1 <= h(1); t2 <= h(2); t3 <= h(3);

s0 <= t0 + 2 * t1; s1 <= t2 - 2 * t3;

y <= s0 + 4 * s1;

END PROCESS;

LC_Tables: FOR k IN 0 TO 3 GENERATE -- One table for each

LC_Table: dapp -- bit in x_in

PORT MAP(table_in => x(k), table_out => h(k));

END GENERATE;

END fpga;
COMPONET CODE FOR PARALLEL

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

ENTITY dapp IS

PORT ( table_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

table_out : OUT INTEGER RANGE -2 TO 4);

END dapp;

ARCHITECTURE LEs OF dapp IS

BEGIN

-- This is the DA CASE table for

-- the 3 coefficients: -2, 3, 1

-- automatically generated with dagen.exe -- DO NOT EDIT!

PROCESS (table_in)

BEGIN

CASE table_in IS

WHEN "000" => table_out <= 0;

WHEN "001" => table_out <= -2;

WHEN "010" => table_out <= 3;

WHEN "011" => table_out <= 1;

WHEN "100" => table_out <= 1;

WHEN "101" => table_out <= -1;

WHEN "110" => table_out <= 4;

WHEN "111" => table_out <= 2;

WHEN OTHERS => table_out <= 0;

END CASE;

END PROCESS;

END LEs;