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HCPL-3120 HCNW 3120 PDF
HCPL-3120 HCNW 3120 PDF
Data Sheet
Description Features
The HCPL-3120 contains a GaAsP LED while the HCPL-J312 and 2.5 A maximum peak output current
the HCNW3120 contain an AlGaAs LED. The LED is optically 2.0 A minimum peak output current
coupled to an integrated circuit with a power output stage. 25 kV/s minimum Common Mode Rejection (CMR) at VCM
These optocouplers are ideally suited for driving power IGBTs = 1500 V
and MOSFETs used in motor control inverter applications. The
0.5 V maximum low level output voltage (VOL) Eliminates
high operating voltage range of the output stage provides the
need for negative gate drive
drive voltages required by gate controlled devices. The voltage
and current supplied by these optocouplers make them ideally ICC = 5 mA maximum supply current
suited for directly driving IGBTs with ratings up to Under Voltage Lock-Out protection (UVLO) with hysteresis
1200 V/100 A. For IGBTs with higher ratings, the HCPL-3120 Wide operating VCC range: 15 to 30 Volts
series can be used to drive a discrete power stage which drives 500 ns maximum switching speeds
the IGBT gate. The HCNW3120 has the highest insulation Industrial temperature range: 40 C to 100 C
voltage of VIORM=1414Vpeak in the IEC/EN/DIN EN 60747-5-5.
Safety Approval:
The HCPL-J312 has an insulation voltage of VIORM = 1230Vpeak
and the VIORM = 630Vpeak is also available with the HCPL-3120 UL Recognized
(Option 060). 3750 Vrms for 1 min. for HCPL-3120/J312
5000 Vrms for 1 min. for HCNW3120
CAUTION It is advised that normal static precautions be
CSA Approval
taken in handling and assembly of this
component to prevent damage and/or IEC/EN/DIN EN 60747-5-5 Approved:
degradation which may be induced by ESD. VIORM= 630 Vpeak for HCPL-3120 (Option 060)
VIORM= 1230 Vpeak for HCPL-J312
VIORM= 1414 Vpeak for HCNW3120
Applications
IGBT/MOSFET gate drive
AC/Brushless DC motor drives
Industrial inverters
Switch mode power supplies
Avago Technologies
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HCPL-3120/J312, HCNW3120 Functional Diagram
Data Sheet
Functional Diagram
HCPL-3120/J312 HCNW3120
N/C 1 8 VCC N/C 1 8 VCC
ANODE 2 7 VO ANODE 2 7 VO
Truth Table
VCC - VEE VCC - VEE NEGATIVE
LED POSITIVE GOING GOING (i.e., V0
(i.e., TURN-ON) TURN-OFF)
OFF 030 V 030 V LOW
ON 011 V 09.5 V LOW
ON 11 13.5 V 9.512 V TRANSITION
ON 13.530 V 1230 V HIGH
Selection Guide
Avago Technologies
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HCPL-3120/J312, HCNW3120 Ordering Information
Data Sheet
Ordering Information
HCPL-3120 and HCPL-J312 are UL recognized with 3750 Vrms for 1 minute per UL1577. HCNW3120 is UL Recognized with 5000
Vrms for 1 minute per UL1577.
Option
Surface Tape and IEC/EN/DIN
Part RoHS Non RoHS Package Gull Wing Quantity
Mount Reel Number
Compliant Compliant
HCPL-3120 -000E No option 300-mil, 50 per tube
DIP-8
-300E #300 X X 50 per tube
-500E #500 X X X 1000 per reel
-060E #060 X 50 per tube
-360E #360 X X X 50 per tube
-560E/PE #560 X X X X 1000 per tube
HCPL-J312 -000E No option 300-mil, X 50 per tube
DIP-8
-300E #300 X X X 50 per tube
-500E #500 X X X X 1000 per reel
HCNW3120 -000E No option 400-mil, X 42 per tube
DIP-8
-300E #300 X X X 42 per tube
-500E #500 X X X X 750 per reel
NOTE The notation #XXX is used for older products, while products launched since 15th July 2001 and RoHS compliant
option will use -XXXE.
To order, choose a part number from the part number column and combine with the desired option from the option column to
form an order entry.
Example 1:
HCPL-3120-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-5 Safety Approval in RoHS compliant.
Example 2:
HCPL-3120 to order product of 300 mil DIP package in tube packaging and non RoHS compliant.
Option data sheets are available. Contact your Avago Technologies sales representative or authorized distributor for information.
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Outline Drawings
Data Sheet
+ 0.076
5 TYP. 0.254 - 0.051
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Outline Drawings
Data Sheet
8 7 6 5
6.350 0.25
(0.250 0.010) 10.9 (0.430)
1 2 3 4
2.0 (0.080)
1.27 (0.050)
1.080 0.320
(0.043 0.013) 0.635 0.25
(0.025 0.010)
0.635 0.130 12 NOM.
2.54
(0.100) (0.025 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Outline Drawings
Data Sheet
8 7 6 5 7.62 0.25
(0.300 0.010)
Avago A NNNN Z Test Rating Code
Lead Free
YYWW
EEE P
UL Logo
Special Program
6.35 0.25
(0.250 0.010)
Code
Pin 1 Dot 1 2 3 4
+ 0.076
5 TYP. 0.254 - 0.051
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Outline Drawings
Data Sheet
8 7 6 5
6.350 0.25
(0.250 0.010) 10.9 (0.430)
1 2 3 4
2.0 (0.080)
1.27 (0.050)
1.080 0.320
(0.043 0.013) 0.635 0.25
(0.025 0.010)
0.635 0.130 12 NOM.
2.54
(0.100) (0.025 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Outline Drawings
Data Sheet
3.10 (0.122)
3.90 (0.154) 0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 0.15 0.40 (0.016) DIMENSIONS IN MILLIMETERS (INCHES).
(0.070 0.006) 0.56 (0.022)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Outline Drawings
Data Sheet
11.15 0.15
(0.442 0.006)
8 7 6 5
13.56
(0.534)
9.00 0.15
(0.354 0.006)
1.3 2.29
1 2 3 4 (0.09)
(0.051)
12.30 0.30
1.55 (0.484 0.012)
(0.061) 11.00 MAX.
MAX. (0.433)
4.00 MAX.
(0.158)
1.78 0.15
(0.070 0.006) 1.00 0.15
0.75 0.25 (0.039 0.006) + 0.076
2.54 0.254 - 0.0051
(0.100) (0.030 0.010)
BSC + 0.003)
(0.010 - 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
7 NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Avago Technologies
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HCPL-3120/J312, HCNW3120 Solder Reflow Temperature Profile
Data Sheet
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.
25
t 25 C to PEAK
TIME
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 C, Tsmin = 150 C
30 TIME
160 C
150 C
SEC. 200 C
140 C
30
3 C + 1 C/0.5 C SEC.
100
PREHEATING TIME
150 C, 90 + 30 SEC. 50 SEC.
TIGHT
ROOM TYPICAL
TEMPERATURE LOOSE
0
0 50 100 150 200 250
TIME (SECONDS)
Avago Technologies
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HCPL-3120/J312, HCNW3120 Regulatory Information
Data Sheet
Regulatory Information
Agency/Standard HCPL-3120 HCPL-J312 HCNW3120
Underwriters Laboratory (UL) Compliant Compliant Compliant
Recognized under UL 1577, Component Recognition Program,
Category, File E55361
Canadian Standards Association (CSA) File CA88324, Compliant Compliant Compliant
per Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-5 Compliant Compliant Compliant
Option 060
Avago Technologies
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HCPL-3120/J312, HCNW3120 IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics
Data Sheet
All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements.
However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for
individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the
solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which
may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also
change depending on factors such as pollution degree and insulation level.
Input to Output Test Voltage, Method ba VPR 1181 1670 2652 Vpeak
VIORM 1.875 = VPR, 100% Production Test,
tm = 1 sec, Partial Discharge < 5pC
Input to Output Test Voltage, Method aa VPR 1008 1968 2262 Vpeak
VIORM 1.6 = VPR, Type and Sample Test,
tm = 10 sec, Partial Discharge < 5pC
a. Refer to the IEC/EN/DIN EN 60747-5-5 section (page 1-6/8) of the Isolation Control Component Designers Catalog for a detailed description of Method a/b
partial discharge test profiles.
NOTE These optocouplers are suitable for safe electrical isolation only within the safety limit data. Maintenance of the
safety data shall be ensured by means of protective circuits. Surface mount classification is Class A in accordance
with CECC 00802.
Avago Technologies
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HCPL-3120/J312, HCNW3120 Absolute Maximum Ratings
Data Sheet
Lead Solder Temperature HCPL-3120 260C for 10 sec., 1.6 mm below seating plane
HCPL-J312
HCNW3120 260 C for 10 sec., up to seating plane
Solder Reflow Temperature Profile See Package Outline Drawings section
a. Derate linearly above 70 C free-air temperature at a rate of 0.3 mA/C.
b. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum =
2.0 A. See Applications section for additional details on limiting IOH peak.
c. Derate linearly above 70 C free-air temperature at a rate of 4.8 mW/C.
d. Derate linearly above 70 C free-air temperature at a rate of 5.4 mW/C. The maximum LED junction temperature should not exceed 125 C.
Avago Technologies
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HCPL-3120/J312, HCNW3120 Electrical Specifications (DC)
Data Sheet
Parameter Symbol Device Min. Typ.a Max. Units Test Conditions Fig. Note
2.0 A VO = (VCC 15 V) 17 c
2.0 A VO = (VEE + 15 V) 18 c
Avago Technologies
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HCPL-3120/J312, HCNW3120 Switching Specifications (AC)
Data Sheet
Parameter Symbol Min. Typ.a Max. Units Test Conditions Fig. Note
Propagation Delay Time to High tPLH 0.10 0.30 0.50 s Rg = 10 , 10, 11, b
Output Level Cg = 10 nF, 12, 13,
f = 10 kHz, 14, 23
Propagation Delay Time to Low tPHL 0.10 0.30 0.50 s
Duty Cycle = 50%
Output Level
Pulse Width Distortion PWD 0.3 s c
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Characteristics
Data Sheet
Package Characteristics
Over recommended temperature (TA = 40 to 100 C) unless otherwise specified.
Parameter Symbol Device Min. Typ.a Max. Units Test Conditions Fig. Note
HCPL-J312
HCNW3120 1012 1013 TA = 25C
1011 TA = 100C
Capacitance (Input-Output) CI-O HCPL-3120 0.6 pF f = 1 MHz
HCPL-J312 0.8
HCNW3120 0.5 0.6
LED-to-Case Thermal Resistance LC 467 C/W Thermocouple 28
located at center
LED-to-Detector Thermal LD 442 C/W underside of
Resistance package
Detector-to-Case Thermal DC 126 C/W
Resistance
a. All typicals at TA = 25 C.
b. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating.
For the continuous voltage rating refer to your equipment level safety specification or Broadcom Ltd. Application Note 1074 entitled Optocoupler
Input-Output Endurance Voltage.
c. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit,
II-O 5 A).
d. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
e. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit,
II-O 5 A).
f. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 6000 Vrms for 1 second (leakage detection current limit,
II-O 5 A).
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Characteristics
Data Sheet
Figure 1 VOH vs. Temperature Figure 2 IOH vs. Temperature Figure 3 VOH vs. IOH
V
V
0 2.0 -1
I F = 7 to 16 mA I F = 7 to 16 mA
(V OH V CC ) HIGH OUTPUT VOLTAGE DROP
1.6 -3
-2
1.4 -4
-3 I F = 7 to 16 mA
1.2 -5 V CC = 15 to 30 V
V EE = 0 V
-4 1.0 -6
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5
T A TEMPERATURE C T A TEMPERATURE C I OH OUTPUT HIGH CURRENT A
Figure 4 VOL vs. Temperature Figure 5 IOL vs. Temperature Figure 6 VOL vs. IOL
0.25 4 4
V F(OFF) = -3.0 to 0.8 V
V
V
A
V EE = 0 V V EE = 0 V
0.15
2 2
0.10
1 1
0.05 100 C
25 C
-40 C
0 0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5
T A TEMPERATURE C T A TEMPERATURE C I OL OUTPUT LOW CURRENT A
3.5 3.5
I CCH I CCH
I CCL I CCL
3.0 3.0
I CC SUPPLY CURRENT mA
I CC SUPPLY CURRENT mA
2.5 2.5
V CC = 30 V I F = 10 mA for I CCH
2.0 V EE = 0 V 2.0 I F = 0 mA for I CCL
I F = 10 mA for I CCH T A = 25 C
I F = 0 mA for I CCL V EE = 0 V
1.5 1.5
-40 -20 0 20 40 60 80 100 15 20 25 30
T A TEMPERATURE C V CC SUPPLY VOLTAGE V
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Characteristics
Data Sheet
3 3 3
2 2 2
1 1 1
0 0 0
-40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100
T A TEMPERATURE C T A TEMPERATURE C T A TEMPERATURE C
Figure 10 Propagation Delay vs. VCC Figure 11 Propagation Delay vs. IF Figure 12 Propagation Delay vs.
Temperature
T p PROPAGATION DELAY ns
T p PROPAGATION DELAY ns
400
T p PROPAGATION DELAY ns
500 500
V CC = 30 V, V EE = 0 V V CC = 30 V, V EE = 0 V
T A = 25 C T A = 25 C
I F = 10 mA I F = 10 mA
T p PROPAGATION DELAY ns
T p PROPAGATION DELAY ns
400 Cg = 10 nF 400 Rg = 10
DUTY CYCLE = 50% DUTY CYCLE = 50%
f = 10 kHz f = 10 kHz
300 300
200 200
T PLH T PLH
T PH L T PH L
100 100
0 10 20 30 40 50 0 20 40 60 80 100
Rg SERIES LOAD RESISTANCE Cg LOAD CAPACITANCE nF
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Characteristics
Data Sheet
30 HCPL-J312
35
V
25
30
V
V O OUTPUT VOLTAGE
20 25
V O OUTPUT VOLTAGE
15 20
15
10
10
5
5
0
0 1 2 3 4 5 0
0 1 2 3 4 5
I F FORWARD LED CURRENT mA
I F FORWARD LED CURRENT mA
HCPL-3120 HCPL-J312/HCNW3120
1000 1000
T A = 25C
T A = 25C
100 100
IF IF
I F FORWARD CURRENT mA
I F FORWARD CURRENT mA
10 + 10 +
VF
VF
1.0 1.0
0.1 0.1
0.01 0.01
0.001 0.001
1.10 1.20 1.30 1.40 1.50 1.60 1.2 1.3 1.4 1.5 1.6 1.7
V F FORWARD VOLTAGE VOLTS
V F FORWARD VOLTAGE VOLTS
1 8
0.1 F
+ 4V
2 7
I F = 7 to + V CC = 15
16 mA to 30 V
3 6
I OH
4 5
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Characteristics
Data Sheet
1 8 1 8
0.1 F 0.1 F
I OL V OH
2 7 2 7
+ V CC = 15 I F = 7 to
to 30 V + V CC = 15
16 mA to 30 V
3 6 2.5 V + 3 6
100 mA
4 5 4 5
1 8 1 8
0.1 F 0.1 F
100 mA
2 7 2 7
+ V CC = 15 IF + V CC = 15
to 30 V VO > 5 V to 30 V
3 6 3 6
V OL
4 5 4 5
1 8
0.1 F
2 7
I F = 10 mA + V CC
VO > 5 V
3 6
4 5
Avago Technologies
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HCPL-3120/J312, HCNW3120 Package Characteristics
Data Sheet
1 8
0.1 F IF
I F = 7 to 16 mA V CC = 15
+ to 30 V
2 7
500 tr tf
+ VO
10 KH z 90%
50% DUT Y 3 6 10
CYCLE 50%
10 nF V OUT 10%
4 5
tPLH tPHL
V CM
V V CM
1 8 =
IF t t
A 0.1 F
0V
2 7
B
+ + t
5V VO
V CC = 30 V
3 6 V OH
VO
SWITCH AT A: I F = 10 mA
4 5
VO V OL
SWITCH AT B: I F = 0 mA
+
V CM = 1500 V
Avago Technologies
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HCPL-3120/J312, HCNW3120 Application Information
Data Sheet
Application Information
Eliminating Negative IGBT Gate Drive (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120)
To keep the IGBT firmly off, the HCPL-3120 has a very low maximum VOL specification of 0.5V. The HCPL-3120 realizes this very low
VOL by using a DMOS transistor with 1 (typical) on resistance in its pull down circuit. When the HCPL-3120 is in the low state, the
IGBT gate is shorted to the emitter by Rg + 1. Minimizing Rg and the lead inductance from the HCPL-3120 to the IGBT gate and
emitter (possibly by mounting the HCPL-3120 on a small PC board directly above the IGBT) can eliminate the need for negative
IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the
IGBT collector or emitter traces close to the HCPL-3120 input as this can result in unwanted coupling of transient signals into the
HCPL-3120 and degrade performance. (If the IGBT drain must be routed near the HCPL-3120 input, then the LED should be
reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3120.)
+5 V HCPL-3120
1 8
VCC = 18 V + HVDC
270 W 0.1 F +
2 7
Rg
CONTROL Q1 3-PHASE
INPUT 3 6 AC
74XXX
OPEN 4 5
COLLECTOR
Q2 - HVDC
Avago Technologies
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HCPL-3120/J312, HCNW3120 Application Information
Data Sheet
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching For the circuit in Figure 26 with IF (worst case) = 16mA, Rg =
Losses. (Discussion applies to HCPL-3120, HCPL-J312 and 8 , Max Duty Cycle = 80%, Qg = 500 nC, f=20 kHz and
HCNW3120) TA max = 85 C:
Step 1: Calculate Rg Minimum from the IOL Peak Specification. PE = 16 mA 1.8 V 0.8 = 23 mW
The IGBT and Rg in Figure 26 can be analyzed as a simple RC
PO = 4.25 mA 20 V + 5.2 J 20 kHz
circuit with a voltage supplied by the HCPL-3120.
= 85 mW + 104 mW
Rg (VCC VEE VOL) / IOLPEAK
= 189 mW > 178 mW (PO(MAX) @ 85 C
= (VCC VEE 2V) / IOLPEAK
= 250 mW-15C*4.8 mW/C)
= (15V + 5V 2V) / 2.5A
The value of 4.25 mA for ICC in the previous equation was
= 7.2 8
obtained by derating the ICC max of 5 mA (which occurs at
The VOL value of 2V in the previous equation is a conservative 40 C) to ICC max at 85C (see Figure 7).
value of VOL at the peak current of 2.5A (see Figure 6). At lower
Since PO for this case is greater than PO(MAX), Rg must be
Rg values the voltage supplied by the HCPL-3120 is not an ideal
increased to reduce the HCPL-3120 power dissipation.
voltage step. This results in lower peak currents (more margin)
than predicted by this analysis. When negative gate drive is not PO(SWITCHING MAX)
used VEE in the previous equation is equal to zero volts.
= PO(MAX) PO(BIAS)
Step 2: Check the HCPL-3120 Power Dissipation and Increase
= 178 mW 85 mW
Rg if Necessary. The HCPL-3120 total power dissipation (PT ) is
equal to the sum of the emitter power (PE) and the output = 93 mW
power (PO):
ESW(MAX) = (PO(SWITCHINGMAX)) / f
PT = PE + PO
= 93 mW / 20 kHz = 4.65 J
PE = IF VF Duty Cycle
For Qg = 500 nC, from Figure 27, a value of ESW = 4.65 J gives
PO = PO(BIAS) + PO (SWITCHING) an Rg = 10.3 .
= ICC (VCC VEE) + ESW(RG, QG) f
Figure 26 HCPL-3120 Typical Application Circuit with Negative IGBT Gate Drive
+5 V HCPL-3120
1 8
VCC = 15 V + HVDC
270 W 0.1 F +
2 7
Rg
CONTROL Q1 3-PHASE
3 6 AC
INPUT VEE = -5 V
+
74XXX
OPEN 4 5
COLLECTOR
Q2 - HVDC
Avago Technologies
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HCPL-3120/J312, HCNW3120 Application Information
Data Sheet
14
TJD = PE ((LC DC) /(LC + DC + LD)) + CA
Esw ENERGY PER SWITCHING CYCLE J
Qg = 100 nC
12 Qg = 500 nC
+ PD (DC||(LD + LC) + CA) + TA Qg = 1000 nC
10
VCC = 19 V
8 VEE = -9 V
Inserting the values for LC and DC shown in Figure 28 gives:
6
TJE = PE (256 C/W + CA)
4
+ PD (57 C/W + CA) + TA
2
0
TJD = PE (57 C/W + CA) 0 10 20 30 40 50
Rg GATE RESISTANCE W
+ PD (111 C/W +CA) + TA
Avago Technologies
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HCPL-3120/J312, HCNW3120 LED Drive Circuit Considerations for Ultra High CMR Performance
Data Sheet
1 8
C LEDP
2 7
3 6
C LEDN
4 5
1 C LEDO1 8
C LEDP
2 7
C LEDO2
3 6
C LEDN
4 5
SHIELD
Avago Technologies
- 25 -
HCPL-3120/J312, HCNW3120 CMR with the LED On (CMRH)
Data Sheet
CMR with the LED On (CMRH) Figure 32 Not Recommended Open Collector Drive Circuit
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving the 1 8
LED current beyond the input threshold so that it is not pulled +5 V
below the threshold during a transient. A minimum LED 2
C LEDP
7
current of 10 mA provides adequate margin over the maximum
IFLH of 5 mA to achieve 25 kV/s CMR.
3 6
Q1 C LEDN
I LEDN
CMR with the LED Off (CMRL) 4 5
SHIELD
A high CMR LED drive circuit must keep the LED off (VF
VF(OFF)) during common mode transients. For example, during
a dVcm/dt transient in Figure 31, the current flowing through
CLEDP also flows through the RSAT and VSAT of the logic gate. As Figure 33 Recommended LED Drive Circuit for Ultra-High CMR
long as the low state voltage developed across the logic gate is
less than VF(OFF), the LED will remain off and no common mode
failure will occur. 1 8
+5 V
The open collector drive circuit, shown in Figure 32, cannot C LEDP
2 7
keep the LED off during a +dVcm/dt transient, since all the
current flowing through CLEDN must be supplied by the LED,
and it is not recommended for applications requiring ultra high 3
C LEDN
6
CMRL performance. Figure 33 is an alternative drive circuit
which, like the recommended application circuit (Figure 25), 4 5
does achieve ultra high CMR performance by shunting the LED SHIELD
14
+5 V 12
V
1 8
0.1 (12.3, 10.8)
10
V O OUTPUT VOLTAGE
4 5 2
SHIELD
(10.7, 0.1) (12.3, 0.1)
0
0 5 10 15 20
* THE ARROWS INDICATE THE DIRECTIO N
(V CC - V EE ) SUPPLY VOLTAGE V
OF CURRENT FLOW DURING d V CM /dt.
+
V CM
Avago Technologies
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HCPL-3120/J312, HCNW3120 Under Voltage Lockout Feature
Data Sheet
high state (assumes LED is ON) with a typical delay, UVLO PDD* MAX
Turn On Delay of 0.8 s. MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
IPM Dead Time and Propagation Delay = (tPHL MAX - tPLH MIN) (tPHL MIN - tPLH MAX)
= PDD* MAX PDD* MIN
Specifications *PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
(Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
Avago Technologies
- 27 -
Figure 37 Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-5
HCNW3120
IS
IS
P S , INPUT CURRENT
900
P S , INPUT CURRENT
300 400
300
OUTPUT POWER
OUTPUT POWER
200
200
100
100
0 0
0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175
T S CASE TEMPERATURE C T S CASE TEMPERATURE C
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago Technologies and the A logo are trademarks of Avago Technologies in the United
States and other countries. All other brand and product names may be trademarks of their
respective companies.
Data subject to change. Copyright 2016 Avago Technologies. All Rights Reserved.
AV02-0161EN March 21, 2016
Mouser Electronics
Authorized Distributor
Avago Technologies:
HCPL-3120#300 HCPL-3120#360 HCPL-3120#500 HCPL-3120#560 HCPL-3120-300E HCPL-3120-360E HCPL-
3120-500E HCPL-3120-560E HCPL-J312#300 HCPL-J312#500 HCPL-J312-300E HCPL-J312-500E
Broadcom Limited:
HCPL-3120-000E