Professional Documents
Culture Documents
Notes2 PDF
Notes2 PDF
1
VLSI Test Principles and Architectures
EE141 Ch. 2 - Design for Testability - P. 1
Design For Testability - contents
Introduction
Testability Analysis
Design for Testability Basics
Scan Cells Designs
Scan Architectures
Scan Design Rules
Scan Design Flow
Special-Purpose Scan Designs
RTL Design for Testability
Concluding Remarks
2
VLSI Test Principles and Architectures
EE141 Ch. 2 - Design for Testability - P. 2
Introduction
History
During early years, design and test were separate
The final quality of the test was determined by keeping track of
the number of defective parts shipped to the customer
Defective parts per million (PPM) shipped was a final test
score.
This approach worked well for small-scale integrated circuit
During 1980s, fault simulation was used
Failed to improve the circuits fault coverage beyond 80%
Increased test cost and decreased test quality
lead to DFT engineering
3
VLSI Test Principles and Architectures
EE141 Ch. 2 - Design for Testability - P. 3
Introduction
History
Various testability measures & ad hoc testability
enhancement methods
To improve the testability of a design
To ease sequential ATPG (automatic test pattern generation)
Still quite difficult to reach more than 90% fault coverage
Structured DFT
To conquer the difficulties in controlling and observing the
internal states of sequential circuits
Scan design is the most popular structured DFT approach
Design for testability (DFT) has migration recently
From gate level to register-transfer level (RTL)
0-controllability 1-controllability
(Primary input, output, branch) (Primary input, output, branch)
Primary Input 1 1
AND min {input 0-controllabilities} + 1 (input 1-controllabilities) + 1
OR (input 0-controllabilities) + 1 min {input 1-controllabilities} + 1
NOT Input 1-controllability + 1 Input 0-controllability + 1
NAND (input 1-controllabilities) + 1 min {input 0-controllabilities} + 1
NOR min {input 1-controllabilities} + 1 (input 0-controllabilities) + 1
BUFFER Input 0-controllability + 1 Input 1-controllability + 1
XOR min {CC1(a)+CC1(b), min {CC1(a)+CC0(b),
CC0(a)+CC0(b)} + 1 CC0(a)+CC1(b)} + 1
XNOR min {CC1(a)+CC0(b), min {CC1(a)+CC1(b),
CC0(a)+CC1(b)} + 1 CC0(a)+CC0(b)} + 1
Branch Stem 0-controllability Stem 1-controllability
Observability
(Primary output, input, stem)
Primary Output 0
3/3/5
2/5/3
1/1/5 . 1/1/7 5/4/0
Cout
2/3/3
1/1/5
1/1/4
Cin
r
The combinational and
Reset
a d sequential controllability
b D Q q
measures of signal d:
Primary Input p0 p1 = 1 - p0
AND 1 (output 1-controllability) (input 1-controllabilities)
OR (input 0-controllabilities) 1 (output 0-controllability)
NOT Input 1-controllability Input 0-controllability
NAND (input 1-controllabilities) 1 (output 0-controllability)
NOR 1 (output 1-controllability) (input 0-controllabilities)
BUFFER Input 0-controllability Input 1-controllability
XOR 1 1-controllabilty (C1(a) C0(b), C0(a) C1(b))
XNOR 1 1-controllability (C0(a) C0(b), C1(a) C1(b))
Branch Stem 0-controllability Stem 1-controllability
Observability
(Primary output, input, stem)
Primary Output 1
a0 b0 ai bi an-1 bn-1
s0 si sn-1
.
Low-observability node A .
Low-observability node C
n
Test response upload
SE CK
The multiplexer uses an additional
Edge-triggered scan enable input SE to select
muxed-D scan
between the data input DI and the
cell
scan input SI.
DI
In the clocked-scan
Q/SO
SI cell, input selection is
conducted using two
DCK SCK independent clocks,
DCK and SCK.
Clocked-scan cell
PI V1: PI V2: PI
SE
S H C H S H C
CK
SFF1.Q 0 1 1 1 L L 1 0 1 1 L
SFF2.Q X 0 1 1 H H L 1 0 0 L
SFF3.Q X X 0 0 L L H L 1 1 H
Normal Normal 0 0
Shift Shift 1 1
Operation
Capture Capture 1 0
Operation
In a clocked full-
scan design, two
SFF1 SFF2 SFF3 operations are
DI DI DI
SI SI Q . SI Q . SI Q . SO
distinguished by
DCK SCK DCK SCK DCK SCK properly applying
DCK
SCK
. . . . the two independent
clocks SCK and
DCK during shift
mode and capture
Clocked full-scan circuit mode.
C1 FF3 C3 FF5 1 3 5
FF1
FF2 C2
2 4
FF4
CK
SC SC SC SI bit address shift
SCK register, where n is
SO the total number of
SC SC SC scan cells, is used to
specify which scan
Column (Y) decoder cell to access.
Address shift register AI
SC SC SC fixed order.
Combinational logic
SC SC SC
It is only necessary to
supply a column address
SC
SC SC
to specify which scan cell
TM Test Column line drivers PI
in an enabled row to
SI/SO control access.
CK logic Column address decoder
CA
PRAS Architecture
Tri-state buses Avoid during shift Fix bus contention during shift
Bi-directional I/O ports Avoid during shift Force to input or output mode
during shift
Gated clocks (muxed-D full-scan) Avoid during shift Enable clocks during shift
Non-scan storage elements Not recommended for full-scan Initialize to known states,
Design bypass, or make transparent
A DFF
D Q
LAT D Q
Clock EN CEN
gating D Q GCK
logic G
Although clock gating is a
D Q good approach for reducing
CK . . . power consumption, it prevents
the clock ports of some flip-
flops from being directly
controlled by primary inputs.
(a) Original circuit
gating G
logic
D Q
CK . . .
DFF1
A multiplexer selects CK,
D Q which is a clock directly
D Q . ICK 0 . controllable from a
primary input, to drive
CK . 1
DFF2
DFF1 and DFF2, during
TM D Q the entire test operation,
when TM = 1.
DI SFF1
SI Q RL Asynchronous set/reset
SE signals of scan cells that
R SFF2 are not directly controlled
DI from primary inputs can
SI Q
SE prevent scan chains from
shifting data properly.
CK .
(a) Original circuit
Testable
design
Scan synthesis
Scan configuration
. Scan replacement
Constraint
. Scan reordering Layout
information
&
control . Scan stitching
information
Scan
design
Scan verification
CK .
Circuit Structure
Circuit Structure
Z D1 D2 D3
Timing diagram
Enhanced-scan architecture
Advantages
High delay fault coverge achieved by applying any
arbitrary pair of test vectors
Disadvantages
Requiring an additional scan-hold D latch
Difficulty of maintaining the timing relationship
between UPDATE and CK
Over-test problem caused by false paths
Error-Resilient Scan O1 O2 Q
0 0 1
1 1 0
0 1 Previous value retained
SCB Scan portion 1 0 Previous value retained
LA LB
SI
SCA
1D
C1 Q
C1
1D
Q
O2. . SO
C-element Keeper
2D
CAPTURE C2 .
. . Q
PH1
1D
.
UPDATE PH2 C1
. . C1 Q 2D
Q
O1
Advantages
Provide online detection and correction of
soft errors
Embed with scan testing capability
Disadvantages
Require many test signals and clocks
Area overhead
RTL design
q <= q + 1;
end TM
assign clk_test = (TM)? clk : clk_15;
always @(posedge clk_test)
d < = start;
(c) Generated clock (RTL code) (d) Generated clock repair (Schematic)
Scan verification
Rely on generating a flush testbench to simulate flush tests
The flush testbench can be used for both RTL and gate-level
designs
Apply broadside-load test for verifying the scan capture
operation at RTL