STV9555

9.5 ns TRIPLE-CHANNEL HIGH VOLTAGE VIDEO AMPLIFIER

FEATURES above is required, ensuring a maximum quality of

the still pictures or moving video.
■ Triple-channel video amplifier
■ Supply voltage up to 115 V Perfecly matched with the STV921x ST
preamplifiers, it provides a highly performant and
■ 80V Output dynamic range very cost effective video system.
■ Perfect for PICTURE BOOST application
requiring high video amplitude
■ Pinning for easy PCB layout
■ Supports DC coupling (optimum cost saving)
and AC coupling applications.
■ Built-in Voltage Gain: 20 (Typ.)
■ Rise and Fall Times: 9.5 ns (Typ.)
■ Bandwidth: 37 MHz (Typ.)
■ Very low stand-by power consumption
■ Perfectly matched with the STV921x
preamplifiers
CLIPWATT 11
DESCRIPTION (Plastic Package)
The STV9555 is a triple-channel video amplifier
designed in a 120V-high voltage technology and ORDER CODE: STV9555
able to drive in DC-coupling mode the 3 cathodes
of a CRT monitor.
The STV9555 supports PICTURE BOOST
applications where video amplitude up to 50V or

PIN CONNECTIONS

11 OUT1
10 OUT2
9 OUT3
8 GNDP
7 VDD
6 GNDS
5 GNDA
4 IN3
3 VCC
2 IN2
1 IN1

Version 4.0

September 2003 1/24

1
 Table of Contents

1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 TYPICAL PERFORMANCE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9 INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 APPLICATION HINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.1 How to choose the high supply voltage value (VDD) in DC coupling mode . . . . . . . . . 12
10.2 Arcing Protection: schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
10.3 Arcing protection: layout and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.4 Video response optimization: schematics in DC-coupling mode . . . . . . . . . . . . . . . . . 14
10.5 Video response optimization: outputs networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.6 Video response optimization: inputs networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.7 Video response optimization: layout and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10.8 AC - Coupling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10.9 Stand-by mode, spot suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10.10 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/24

2
 STV9555

1 BLOCK DIAGRAM

OUT1 GNDP OUT2 OUT3

11 8 10 9
STV9555

VDD GNDP VDD GNDP

VDD 7

VCC 3

VREF

6 1 5 2 4
GNDS IN1 GNDA IN2 IN3

2 PIN DESCRIPTION

Pin Name Function

1 IN1 Video Input (channel 1)
2 IN2 Video Input (channel 2)
3 VCC Low Supply Voltage
4 IN3 Video Input (channel 3)
5 GNDA Ground Analog
6 GNDS Ground Substrat
7 VDD High Supply Voltage
8 GNDP Ground Power
9 OUT3 Video output (channel 3)
10 OUT2 Video output (channel 2)
11 OUT1 VIdeo output (channel 1)

3/24

3
STV9555

3 ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VDD High supply voltage 120 V
VCC Low supply voltage 16.5 V
ESD susceptibility
VESD Human Body Model (100pF discharged through 1.5KΩ) 2 kV
EIAJ norm (200pF discharged through 0Ω) 300 V
IOD Output source current (pulsed < 50µs) 80 mA
IOG Output sink current (pulsed < 50µs) 80 mA
VIN Max Maximum Input Voltage VCC + 0.3 V
VIN Min Minimum Input Voltage - 0.5 V
TJ Junction Temperature 150 °C
TSTG Storage Temperature -20 + 150 °C

4 THERMAL DATA
Symbol Parameter Value Unit
Rth (j-c) Junction-Case Thermal Resistance (Max.) 3 °C/W
Rth (j-a) Junction-Ambient Thermal Resistance (Typ.) 35 °C/W

4/24

3
 STV9555

5 ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions Min. Typ Max Unit

SUPPLY parameters (VCC = 12V, VDD = 110V, Tamb = 25 °C, unless otherwise specified)
VDD High supply voltage 20 110 115 V
VCC Low supply voltage 10 12 15 V
IDD VDD supply current VOUT = 50V 15 mA
VCC : switched off (<1.5V)
IDDS VDD stand-by supply current 60 µA
VOUT: low (Note 1)
ICC VCC supply current VOUT = 50V 40 mA
STATIC parameters (VCC = 12V, VDD = 110V, Tamb = 25 °C)
VOUT DC outpout voltage VIN = 1.90V 77 80 83 V
dVOUT/dVDD High voltage supply rejection VOUT = 50V 0.5 %
dVOUT/dT Output voltage drift versus temperature VOUT = 80V 15 mV/°C
Output voltage matching versus
d∆VOUT/dT VOUT = 80V 1 mV/°C
temperature (Note 2)
RIN Video input resistor VOUT = 50V 2 kΩ
VSATH Output saturation voltage to supply I0 =-40mA (Note 3) VDD - 6.5 V
VSATL Output saturation voltage to GND I0 =40mA (Note 3) 11 V
G Video gain VOUT = 50V 20
LE Linearity error 17 V<VOUT<VDD-15 V 3 8 %
VREF Internal voltage reference 5.6 V

Note 1: The STV9555 goes into stand-by mode when Vcc is switched off (<1.5V).
In stand-by mode, Vout is set to low level.
Note 2: Matching measured between each channel.
Note 3: Pulsed current width < 50µs

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3
STV9555

ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Conditions Min. Typ Max Unit

DYNAMIC parameters (see Figure 1)
tR Rise time VDC=50V, ∆V=40VPP 8.3 ns
tF Fall time VDC=50V, ∆V=40VPP 10.3 ns
OSR Overshoot, white to black transition 5 %
OSF Overshoot, black to white transition 0 %
∆G Low frequency gain matching (Note 4) VDC = 50V, f=1MHz 5 %
BW Bandwidth at -3dB VDC=50V, ∆V=20VPP 37 MHz
tSET 2.5% Settling time VDC=50V, ∆V=40VPP 15 ns
VDC=50V, ∆V=20VPP
CTL Low frequency crosstalk f = 1 MHz 50 dB
VDC=50V, ∆V=20VPP
CTH High frequency crosstalk f = 20MHz 32 dB
DYNAMIC parameter in PICTURE BOOST condition (Note 5)
tPB Rise/fall time VDC=50V, ∆V=60VPP 12 ns
Overshoot white to black or black to white
OSPB VDC=50V, ∆V=60VPP 9 %
transition
Note 4: Matching measured between each channel.
Note 5: PICTURE BOOST condition (video amplitude at 50V or above) is used in some applications when displaying
still picture or moving video. In this condition the high level of contrast improves the pictures quality at the
expense of the video performances (tR, tF and Overshoot) which are slightly deteriorated.

Figure 1. AC test circuit

12V 110V

VCC VDD VDC ∆V

3 7
50Ω

1
OUT RP = 200 Ω
11
IN
CL=8pF
8
VREF
GNDP
STV9555
5
GNDA

6/24

3
 STV9555

6 THEORY OF OPERATION

6.1 General
The STV9555 is a three-channel video amplifier supplied by a low supply voltage: VCC (typ.12V) and a
high supply voltage: VDD (up to 115V).
The high values of VDD supplying the amplifier output stage allow direct control of the CRT cathodes (DC
coupling mode).
In DC coupling mode, the application schematic is very simple and only a few external components are
needed to drive the cathodes. In particular, there is no need of the DC-restore circuitry which is used in
classical AC coupling applications.
The output voltage range is wide enough (Figure 2) to provide simultaneously :
– Cut-off adjustment (typ. 25V)
– Video contrast (typ. up to 40V),
– Brightness (with the remaining voltage range).
In normal operation, the output video signal must remain inside the linear region whatever the cut-off,
brightness and contrast adjustments are.

Figure 2. Output signal, level adjustments

VDD

(A) Top Non-Linear Region

15V (B) Cut-off Adjust. (25V Typ.)

(C) Brightness Adjust. (10V Typ.)

Linear region

Blanking pulse

(D) Contrast Adjust. (40V Typ.)

Video Signal

17V (E) Bottom Non-Linear Region

GND

7/24

3
STV9555

6.2 Output voltage

A very simplified schematic of each STV9555 channel is shown in Figure 3.
The feedback network of each channel is integrated with a typical built-in voltage gain of G=20 (40k/2k).
The output voltage VOUT is given by the following formula:
VOUT = (G+1) x VREF - (G x VIN)
for G = 20 and VREF = 5.6V, we have
VOUT = 117.6 - 20 x VIN

Figure 3. Simplified schematic of one channel

VDD

40k
2k
IN - OUT
+
VREF

GNDA GNDP

8/24
 STV9555

7 POWER DISSIPATION
The total power dissipation is the sum of the static DC and the dynamic dissipation:
PTOT = PSTAT + PDYN.
The static DC power dissipation is approximately:
PSTAT = (VDD x IDD )+ (VCC x ICC)
The dynamic dissipation is, in the worst case (1 pixel On/ 1 pixel Off pattern):
PDYN = 3 VDD x CL x VOUT(PP) x f x K (see Note 6)
where f is the video frequency and K the ratio between the active line and the total horizontal line duration.
Example:
for VDD = 110V, VCC = 12V,
IDD = 15mA, ICC = 40mA,
VOUT = 40 VPP, f = 35MHz,
CL = 8pF and K = 0.72.

We have:
PSTAT = 2.13 W and PDYN = 2.66 W

Therefore:
PTOT = 4.79W.
Note 6: This worst thermal case must only be considered for TJmax calculation. Nevertheless, during the average life
of the circuit, the conditions are closer to the white picture conditions.

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STV9555

8 TYPICAL PERFORMANCE CHARACTERISTICS

VDD=110V, VCC=12V, CL=8pF, RP=200Ω, ∆V=40VPP, unless otherwise specified - see Figure 1

Figure 4. STV9555 pulse response Figure 5. VOUT versus VIN

tr= 8.3ns
STV9555 Vout vs Vin
Overshoot = 5%
120

100

80

Vout (V)
60

40

20

0
tf= 10.3ns
0 1 2 3 4 5 6
Overshoot = 0%
Vin (V)

Figure 6. Power dissipation versus frequency Figure 7. Speed versus temperature

6.00
Vdd=110V
11.5
5.00
Power dissipation (W)

Vdd=100V 11
Tf
4.00 10.5
Speed (ns)

Vdd=90V 10
3.00
9.5
2.00 9
8.5
1.00 Tr
8
0.00 50 60 70 80 90 100
Case Temperature (°C)
10 20 30 40
Frequency (MHz)
(72% active time)

Figure 8. Speed versus offset Figure 9. Speed versus load capacitance

14
14
13
13
12
12
Speed (ns)

Tf
Speed (ns)

11
11
Tf
10 10
Tr
9 Tr 9

8 8
40 45 50 55 60 65 70
7
Offset (Vdc)
8 10 12 14 16 18 20
Load capacitor (pF)

10/24
 STV9555

9 INTERNAL SCHEMATICS

Figure 10. RGB inputs Figure 11. RGB outputs

VDD
VCC

OUT
IN pins 9, 10, 11
pins 1, 2, 4

GNDS

GNDS

Figure 12. VDD Figure 13. VCC

VDD VCC

GNDS
GNDS
Figure 14. GNDP Figure 15. GNDA

GNDA
GNDP
GNDS
GNDS

11/24
STV9555

10 APPLICATION HINTS

10.1 How to choose the high supply voltage value (VDD) in DC coupling mode
The VDD high supply voltage must be chosen carefully. It must be high enough to provide the necessary
video adjustment but set to minimum value to avoid unecessary power dissipation.
Example (see Figure 2):
The following example shows how the optimum VDD voltage value is determined:
– Cut-off adjustment range (B) : 25V
– Max contrast (D) : 40V
Case 1:
10V Brightness (C) adjusted by the preamplifier :
VDD = A + B + C + D + E
VDD = 15V + 25V + 10V + 40V + 17V = 107V
Case 2:
10V Brightness (C) adjusted by the G1 anode:
VDD = A + B + D + E
VDD = 15V + 25V + 40V + 17V = 97V

10.2 Arcing Protection: schematics

As the amplifier outputs are connected to the CRT cathodes, special attention must be given to protect
them against possible arcing inside the CRT.
Protection must be considered when starting the design of the video CRT board. It should always be
implemented before starting to adjust the dynamic video response of the system.
The arcing network that we recommend (see Figure 16) provides efficient protection without deteriorating
the amplifier video performances.
The total resistance between the amplifier and the CRT cathode (R10+R11) protects the device against
overvoltages. We recommend to use R10+R11 > 200 Ω.
Spark gaps are strongly recommended for arcing protection.

12/24
 STV9555

Figure 16. Arcing protection network (one channel)

VDD
R19(**)

C12(*) 33-40Ω
100nF/250V C24 C18
VDD
4.7µF/150V 100nF
D12
FDH400

OUT R10 L1 R11 A CRT

STV9555 0.33µH
110Ω/0.5W 110Ω/0.5W
D13 F1
C29(***)
FDH400 Spark gap
GNDS 0.22µF
200V B
GNDA GNDP

R29(***)
1-10Ω

(*): To be connected as close as possible to the device

(**): R19 must be mandatorily used
(***): Ground separation network

10.3 Arcing protection: layout and decoupling

Several layout precautions have to be considered to get the optimum arcing protection:

Sparkgap grounding: when an arc occurs, the energy must flow through the CRT ground without
reaching the amplifier. This is obtained by connecting the sparkgap grounding (point B) to the CRT
ground (socket) via a wide/short trace. Conversely the point B must be connected to the amplifier
ground via a longer/narrower trace.

Grounding separation: In order to set apart the amplifer ground and CRT ground, the R29/C29 net-
work (Figure 16) can be used.

Amplifier grounding: The 3 grounds GNDS, GNDA and GNDP must be connected together as
close as possible to the device.

13/24
STV9555

10.4 Video response optimization: schematics in DC-coupling mode

The dynamic video response is optimized by carefully designing the supply decoupling of the video board
(see Section 10.7), the tracks (see Section 10.7), then by adjusting the input/output component network
(see Section 10.5).
For dynamic measurements such as rise/fall time and bandwidth, a 8pF load is used (total load including
the parasitic capacitance of the PC board and CRT Socket).
When used in kit with the STV921x preamplifier from ST, the preamplifier bandwidth register (BW, register
13) must be set to minimum (o dec) for an application with t R/tF>5.5ns.

Figure 17. Video response optimization for one channel - DC coupling application

C11 C10(*) C12(*) C24

4.7µF 100nF 100nF 4.7µF
R19(***)
VDD
VCC VDD 33-40Ω
Reference
Input Network #1
C1
STV9555
1.5nF
STV921x

IN OUT
OUT
R10 L1 R11
- CRT
R1(**) C2 +
110Ω 0.33µH 110Ω
51Ω 10pF VREF

GNDS

GNDA GNDP

Caution: For Application with Tr/Tf>5.5ns, the PreAmplifier bandwidth register (BW, Register 13)
must be set to minimum value (0 dec)

(*): To be connected as close as possible to the device

(**): R1 must be not be higher than 100Ω
(***): R19 must be mandatorily used

2 other Input Networks (Network #2 and #3 below) can be used in replacement of the reference Input Network #1.
See Application note AN1510 for complete description.

Input Network #2 Input Network #3

L1
0.33µH
IN IN

R1 C2 R1 C2
82Ω 10pF 33Ω 15pF

14/24
 STV9555

10.5 Video response optimization: outputs networks

The output network (R10/L1/R11) is used to adjust the amplifier video performances. Once R10 and R11
resistors are set to protect the application against arcing (R10 + R11>200Ω), it is possible to increase the
bandwidth by increasing L1.

10.6 Video response optimization: inputs networks

The input network also plays an important role in the device dynamic behaviour. We recommend to use
the reference input network #1, which is described in Figure 17, but 2 other networks (#2 and #3) can be
used to better match the required performances and the video board layout. Refer to the application note
referenced AN1510 for the complete description of these input networks.

10.7 Video response optimization: layout and decoupling

The decoupling of VCC and VDD through good quality HF capacitors (respectively C10 and C12) close to
the device is necessary to improve the dynamic performance of the video signal.
Careful attention has to be given to the three output channels of the amplifier.
Capacitor: The parasitic capacitive load on the amplifier outputs must be as small as possible.
Figure 9 from Section 8 clearly shows the deterioration of the tR/tF when the capacitive load
increases. Reducing this capacitive load is achieved by moving away the output tracks from the other
tracks (especially ground) and by using thin tracks (<0.5mm), see Figure 17.

Cross talk: Output and input tracks must be set apart. The STV9555 pin-out allows the easy separa-
tion of input and output tracks on opposite sides of the amplifier (see Figure 21).

Length: Connection between amplifier output and cathode must be as short and direct as possible.

15/24
STV9555

10.8 AC - Coupling mode

The STV9555 can be used in AC-Coupling mode in kit with the TDA9207/9212 preamplifier from ST. As
for the DC-coupling mode, the STV9555 drives perfectly the video signal in PICTURE BOOST conditions.
A typical schematic is given on the Figure 18 below.

Figure 18. Video response optimization for one channel - AC coupling application

C11 C10(*) C12(*) C24

4.7µF 100nF 100nF 4.7µF
R19(***)
VDD
VCC VDD 33-40Ω
Reference
Input Network #1 (****)
C1
STV9555
1.5nF
OUT
C
OUT IN
R10 L1 C1 R11
- CRT
TDA9207

R1(**) C2 +
51Ω 10pF VREF 110Ω 0.33µH 1µF 110Ω

GNDS

Vrestore GNDA GNDP

Cut-off

DC Restore
circuitry
Caution: For Application with Tr/Tf>5.5ns, the PreAmplifier bandwidth register (BW, Register 13)
must be set to minimum value (0 dec)

(*): To be connected as close as possible to the device

(**): R1 must be not be higher than 100Ω
(***): R19 must be mandatorily used
(****): Input Networks #2 and #3 can be used as well

The advantage of such an architecture is to use smaller VDD and therefore to have smaller power
consumption. This is due to the fact that the STV9555 provides only the video signal and not the cut-off
adjustment. The disadvantage is to have an application with more components (DC restore circuitry).
Note that it is mandatory to keep the output video signal (point C) inside the linear area of the amplifier
(from 17V to VDD - 15V).

16/24
 STV9555

10.9 Stand-by mode, spot suppression

The usual way to set a monitor in stand-by mode is to switch-off the Vcc (12V).
The STV9555 has an extremely low power consumption (I DDS = 60 µA when VCC<1.5V) in stand-by mode
and the outputs are set to low level (white picture).
To avoid the display of a spot effect during the switch-off phase, it is necessary to adjust the G1 circuitry
(Resistors Rx and Cx, see Figure 19) to pull the G1 voltage to low value during a sufficient time duration.

Figure 19. Stand-by mode, spot effect

+80V

Cathode
0V

Case #1: Low Rx.Cx

-30V A spot might appear during
G1 the switch-off phase
Case #2: High Rx.Cx
-120V No spot effect

EHT
(27kV)

Typical G1 generator circuitry

R1 G1

Cx Rx
-120V -30V

17/24
STV9555

10.10 Conclusion
Video response is always a compromise between several parameters. For example, the rise/fall time
improvement leads to the overshoot deterioration.
The recommended way to optimize the video response is:
1 To set R10+R11 for arcing protection (min. 200 Ω)
2. To adjust R20 and R10+R11.
Increasing their value increases the
tR/tF values and decrease the overshoot
3. To adjust L1
Increasing L1 speeds up the device but increases the overshoot.
4. To adjust the input network for the final dynamic tunning (e.g.: critical damping)
We recommend our customers to use the schematic shown on Figure 23 as a starting point for the video
board and then to apply the optimization they need.

18/24
 STV9555

Figure 20. STV9555/9553/9556 + TDA9210/STV9211 + STV9936S/P DC-coupling demonstration

board: Silk Screen and Trace

19/24
STV9555

Figure 21. Outputs trace (from figure 19)

Figure 22. CRT socket trace (from figure 19)

20/24
 HS R1 100Ω

C1 110V
BLK R25 100Ω 100pF R29 39Ω

ABL C26 8V 12V C10 C18

5V R4 100pF 10nF/250V 4.7µF/160V
2.7Ω R11 2.7Ω
D1 U1 C8 C7
47µF/25V 110V
Blue 1N4148 R2 15Ω C3 100nF 1 20 100nF
IN1 BLK
5V

3
R3 D3 D2
J1 2 19
75Ω 1N4148 ABL HS/CLP
1 D4 C31 1.5nF FDH400

Vcc
Vdd
2 1N4148 R9 51Ω L1
Green C4 100nF 3 18 1 11 R6 R7 RK
3
4 5V IN2 OUT1 In1 Out1
R5 D5 R8 15Ω C23 110Ω/0.25W D10 110V 0.33µH 110Ω/0.25W
5 F2
6 75Ω 1N4148
C9 100nF 4
FDH400 200V CRT small neck
D6 GNDL VCCP 17 C33 1.5nF 10pF
D7
U2 R
video Red 1N4148 R12 15Ω C6 100nF 5 IN3 R13 51Ω
OUT2 16 FDH400
D8 STV9555 R14 L2 R15
R10 C24 2 10 GK G
C22 100nF C5 100nF In2 Out2
75Ω 6 15 10pF 0.33µH 110Ω/0.25W
1N4148 GNDA GNDP C36 1.5nF 110Ω/0.25W 110V F4
D12 B
R16 2.7Ω R17 51Ω 200V
7 14 FDH400
VCCA OUT3 D9
5V C25
8 13 R19 2.7kΩ FDH400
U3 OSD1 SDA 10pF 4 R22 L3 R23 BK
9
SDA R38 100Ω 1 R46 5.6kΩ C35 10nF R40 100Ω In3 Out3
16 110Ω/0.25W 0.33µH 110Ω/0.25W
SDA AVSS 9 12 R21 2.7kΩ D13 F1
OSD2 SCL
R39 100Ω R45 15kΩ R47 100Ω 200V

GNDA
GNDS
GNDP
SCL 2 15 Rp SCL FDH400
SCL RP 10 11

5
6
8
9 H2
5 G1
7 G2
1 GND

OSD3 FBLK
10 H1
12 GND

R35 100Ω Vco R44 5.6kΩ C34 10nF C13

VS 3 14
VS VCO 100pF 5V
R43 TDA9210 Heater
HFLY R41 100Ω 4 HFLY AVdd 1MΩ J10 4.7nF/2kV
AVDD 13 L4 1µH 3.3V 1 110V GND C14
SDA C19
2 100nF F3
L5 1µH 5 12 C2 C37 3 J7
3.3V DVDD FBLK C21 1.5Ω
100nF 100µF/25V 4
C12 10nF/250V
C28 100nF G1 R27
6 11 100pF I2C R28 0Ω optional
DVSS BOUT R31
R36 330Ω 150Ω/0.25W D11 C20
C32 7 10 30Ω/0.5W
TEST GOUT 1N4004 4.7nF/1kV
100µF/25V R32 330Ω 12V
8 OVDD ROUT 9 8V
J8
R33 330Ω 110V HS1
STV9936S/P G2
5V 1
J16 C16 2
R34 330Ω 1 3
2 47µF/25V
3 C15
J17 4 RadAB20
47µF/25V STMicroelectronics
7 G1 5 BLK Monitor Business Unit - Video application
6 6 3.3V CMG - Imaging and Display Division (IDD)
5 HEATER 7 12, rue Jules Horowitz - B.P. 217
8 R37 51Ω
4 38019 Grenoble cedex - FRANCE
3 VS
2 HS ABL ZD1 C27
Power
1 HFLY 3V0 47µF/25V
C27
Sync 47µF/25V EVALCRT52/STV955x demoboard (AB25)
Version 1.4 Rev.
C
Wednesday October 3, 2001
Figure 23. STV9555/53/56 + STV9936 + TDA9210/STV9211 DC-coupling demo-board schematic
STV9555

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STV9555

11 PACKAGE MECHANICAL DATA

11 PIN - CLIPWATT

V1
H3
A S H2
Shaded area ewposed from plastic body
C H1 Typical 30 µm
V2 V1

L3
V1 V1
R2
L2
R
L1

R1
V
R3
D

R3 R3
B

LEAD#1 G F
E F1
M1 M G1

Millimeters Inches
Dimensions
Min. Typ. Max. Min. Typ. Max.
A 2.95 3 3.05 0.116 0.118 0.12
B 0.95 1 1.05 0.037 0.039 0.041
C - 0.15 - - 0.006 -
D 1.3 1.5 1.7 0.051 0.059 0.061
E 0.49 0.515 0.55 0.0.019 0.02 0.021
F 0.78 0.8 0.86 0.03 0.031 0.034
F1 - 0.05 0.1 - 0.002 0.004 (6)
G 1.6 1.7 1.8 0.063 0.067 0.071
G1 16.9 17 17.1 0.665 0.669 0.673
H1 - 12 - - 0.472 -
H2 18.55 18.6 18.65 0.73 0.732 0.734
H3 19.9 20 20.1 0.783 0.787 0.791 (5)
L 17.7 17.9 18.1 0.696 0.704 0.712
L1 14.35 14.55 14.65 0.564 0.572 0.576
L2 10.9 11 11.1 0.429 0.433 0.437(5)
L3 5.4 5.5 5.6 0.212 0.216 0.22
M 2.34 2.54 2.74 0.092 0.1 0.107
M1 2.34 2.54 2.74 0.092 0.1 0.107
R 1.45 - - 0.057 - -

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 STV9555

Millimeters Inches
Dimensions
Min. Typ. Max. Min. Typ. Max.
R1 3.2 3.3 3.4 0.126 0.13 0.134
R2 - 0.3 - - 0.012 -
R3 - 0.5 - - 0.019 -
S 0.65 0.7 0.75 0.025 0.027 0.029
V 10deg. 10deg.
V1 5deg. 5deg.
V2 75deg. 75deg.
Note 5: “H3 and L2” do not include mold flash or protrusions
Mold flash or protrusions shall not exceed 0.15mm per side.
Note 6: No intrusions allowed inwards the leads

Critical dimensions:
Lead split (M1)
Total length (L)

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STV9555

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of
STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication
supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as
critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a trademark of STMicroelectronics.

© 2003 STMicroelectronics - All Rights Reserved

Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent.
Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard
Specifications as defined by Philips.

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4
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