2017 International Conference on circuits Power and Computing Technologies [ICCPCT]
An Investigation of FinFET Based Digital Circuits for
Low Power Applications
Ashok Kumar Kuna, Kavindra Kandpal, Karri Babu Ravi Teja
Department of Electrical and Electronics Engineering
BITS Pilani, Pilani Campus
Rajasthan, India
Abstract— This paper presents a design methodology of flip-
flops for low power applications using FinFET. It presents an
investigation of the basic characteristics of p-FinFETs and n-
FinFETs in various configurations. An Inverter, the simplest
digital circuit is implemented and extensively studied to
understand the concepts of sizing and optimal choice of the
configurations. Multiplexer based approach for implementing
the flip-flop has been chosen for demonstration. The Predictive
Technology Model (PTM) FinFET 32nm library has been used
on HSPICE for implementing the designs. The designed flip-flops
operates with 0.9V and consumes a power of 11.4 μW.
Keywords— FinFET; flip-flop; transmission gate; inverter ;
I. INTRODUCTION
CMOS technology has remained a major workhorse for
electronic designers over the past few decades due to its
advantages like low power consumption and low cost per chip.
Sir Gordon Moore the cofounder of Intel, in his Moore’s
law[1] has predicted the dominance of CMOS technology in
the world of electronics. Over the decades, researchers and
engineers across the world have worked hard to keep Moore’s
law still in action. These efforts have almost come to a halt
since the fundamental limits have been reached. The
advancements with the lower technology nodes where short
channel effects are highly pronounced are feasible by
modifying the circuit architecture rather the device itself.
These architectural changes may not give a long run solution,
since the leakage current that which increases the static power
consumption of a circuit is a serious concern with short
channel devices [2]. Ways to mitigate the problem of static
power consumption need to be thoroughly investigated.
Leakage current can be handled effectively at the device level
rather than the circuit level. So a large number of alternatives
like CNTFET, Tunnel FET, MUGFET etc. are under
investigation from various research groups. These alternate
devices spans across a wide range of materials. The physics
behind their operation has also changed from that of the
conventional classical transport theory to quantum mechanics.
Since Silicon based electronics has been studied for a long
time from now it has matured. Replacing the existing
978-1- 5090-4967- 7/17/$31.00 © 2017 IEEE
technology by a completely new process involves a lot of
financial resources. So, alternatives that are compatible with
the existing CMOS process technology is the need of the day.
MUGFET (Multi-Gate FET) technology, which is a slight
modification of planar CMOS has picked up progress in the
last decade. FinFET, is one variant of MUGFET where the
gate terminal surrounds the raised channel region and appears
in the form of a fin. FinFET based SRAM cell design has a
received a lot of attention from the research community [3-5].
The prime objective of this paper is to present the design
methodology for designing a flip-flop, a single bit storage
element using FinFET. A detailed study of inverters,
transmission gates, which are building blocks of flipflop are
discussed first.
II. FINFET CHARACTERISTICS
MOSFET is a voltage controlled current source. The
current flowing through the channel is controlled by the
voltage applied on the gate terminal. In shorter channel
MOSFET (L<100nm) the gate terminal is no longer able to
control the channel current effectively. In addition, the gate
leakage current which goes up exponentially with gate
insulator thickness has increased exponentially [6]. In order to
provide the gate terminal full control over the channel new
class of MOSFET called MUGFET are proposed [7,8]. In
these MUGFET technology, there is more than one gate and
hence derive their name from the gate count e.g. Double Gate
FET (DGFET), TriGate FET, Circular Gate FET, etc.
Whatever may be the gate terminal structure the idea is to
create and sustain an electric field all around the channel so
that, the carriers in the channel region are solely under the
influence of gate terminal and are least affected by the
interfering electric fields from adjacent terminals like Drain.
The structure of FinFET is shown in Fig.1. Unlike the
MOSFET FinFET is a three dimensional structure. The source
and drain regions are raised. The channel region is surrounded
by the gate on three sides as shown in Fig.1. The major
advantage of this structure is its resemblance with MOSFET.

Fig. 1 Structure of FinFET as reported in [8]
The layout of this structure is similar to MOSFET. This
provides the leverage to designers who are well versed with
MOSFET. Existing design methodologies also can be quickly
applied on FinFET circuits with slight modifications. The
design parameters are still the width W and the length L. The
definition of width W is given in eq.1.
W = 2 × H fin + W fin
Where Hfin denotes the vertical height of the fin and Wfin
denotes the width of the fin. NFIN which denotes the number
of fins and NF which denotes the number of fingers per fin are
additional design parameters that can be used to increase the
width. The expression for width as shown in eq.1. is in general
an overestimate, since it doesn’t take the fringe field into
account.
The circuit symbols of FinFET are shown in Fig.2. The
additional terminal is referred as back gate.
Fig. 2 Symbols of FinFET (a) shorted gate (SG) mode n-FinFET (b)
independent gate (IG) n-FinFET (c) shorted gate (SG) p-FinFET (d)
independent gate (IG) p-FinFET
Unlike a MOSFET which can operate in only one mode of
operation (mode of operation is different from the region of
operation), FinFET can operate in any of the three modes.
These modes are named after the properties FinFET exhibit in
these configurations. Shorted gate (SG) mode, in which both
the front and back gate are tied together, Fig.2.a.,c.,
independent gate (IG) mode in which the both gate terminals
are independent of each other Fig.2.b.,d. and a hybrid mode
often termed as independent gate low power mode (IG/LP). In
hybrid mode the back gate is tied to a suitable potential which
leads to low power (LP) operation.
III. INVERTER TOPOLOGIES
A. Performance analysis of inverter
1. Shorted gate (SG) FinFET Based Inverter: Both
the front and back gate are tied together and the input
is applied to this combined gate terminal Fig.3.a. In
this configuration of the device since there is
virtually only a single gate. The overall power
consumption increases as the leakage and switching
currents are more. The current drive capability is also
more and results in less delay. The figure of merit for
a digital circuit power delay product (PDP) is least in
this mode of operation.
2. Independent gate (IG) FinFET Based Inverter:
Unlike the SG mode, which is similar to the
conventional MOSFET Fig.3.b. In this mode the
front gate and back gate are treated as independent
terminals and are driven separately. Leakage currents
are almost comparable to SG mode FinFETs, while
the switching currents are less, as a result power
consumption and delay are moderate. The power
delay product (PDP) is also moderate for this mode
(1) 3. Independent gate low Power (IG-LP) FinFET
Based Inverter: This is a hybrid mode aimed for low
power consumption. The back gates of p-FinFET
and n-FinFET are separately tied to voltage levels
Fig.3.c. In total 4 different combinations of these
potentials exist. They are referred as (1.1,-0.2),
(1.1,0), (0.9,-0.2), (0.9,0) where the coordinate pair
(a, b) denotes the voltage applied at the back gate of
p-FinFET and n-FinFET respectively (VDD=0.9V,
GND=0). The last combination is simply an IG mode
FinFET.
Fig. 3 FinFET based inverter topologies (a) shorted gate inverter (b)
hybrid mode inverter (c) independent gate mode inverter
IV. DESIGN OF FLIP-FLOPS
Flip-flops are the basic building block of any sequential
circuit. So their design and optimization is necessary to design
better digital systems. Flip-flops can be implemented using
multiplexers (MUX) and inverters. Such implementation has
an advantage in terms of power delay product (PDP)
compared to other designs [9,10]. The implementation of
MUX based on transmission-gate (TG) logic is presented
below. TG can be implemented using either SG or IG-LP as
shown in Fig.4. and Fig.5.s SG implementation is usually
faster than IG-LP mode due to its more current drive
capability [11]. In IG-LP mode, for optimal performance back
gate of n-FinFET is to be connected to VHIGH = 1.1V while the
back gate of p-FinFET is to be connected to VLOW = -0.2V
[9]. A Positive latch built using MUX and inverters is shown
in Fig.6 and a negative edge triggered flip flop is shown in
Fig.7. The detailed performance analysis of these architectures
is presented in section-V.
Fig. 4 shorted gate transmission gate implementation of multiplexer
Fig. 4
Fig. 5 hybrid mode transmission gate implementation of multiplexer
Fig. 6 multiplexer based implementation of positive latch
Fig. 7 negative latch implementation based on multiplexer
V. SIMULATION RESULTS
A. Transfer Characteristics
The input and output transfer characteristics of n-type
and p-type FinFET are shown in Fig.8-11. In both input
and output transfer characteristic curves, SG mode
FinFET gives better performance, which means it has
more driving capability than other modes. IG-LP mode
FinFET has least driving capability and IG-mode FinFET
has moderate driving capability.
Fig. 8 ID Vs VDS characteristics of n-FinFET in various modes
Fig. 9 ID Vs VGS characteristics of n-FinFET in various modes
Fig. 10 ID Vs VDS characteristics of p-FinFET in various modes
 C. Propagation Delay as a function of sizing ratio ȕ
The ratio of the aspect ratios of p-FinFET and n-FinFET is
termed as ȕ. Ideally a good design is the one which has equal
delay for both low to high (TPLH) and high to low transition
(TPHL). Fig.1 shows the variation of TPLH and TPHL as a
function ȕ. It results out to be, for SG-mode (ȕ=2.4), for IG-
mode (ȕ=2.0) and IG-LP (ȕ=2.1). This ratio can be used for
designing static complementary logic families. Table-I
compares various parameters of an inverter. The numbers in
the parenthesis indicate the number of FINS in p-FinFET and
n-FinFET. In case of IG-LP mode the supply voltages at the
back gate of p-FinFET and n-FinFET are also shown.

D. Power Delay Product (PDP) as a function of Supply

Fig. 11 ID Vs VGS characteristics of p-FinFET in various modes
B. Scaling of Supply Voltages
To find the optimum supply voltage for FinFET, the
impact of VDD scaling on the voltage transfer characteristics is
plotted in all the modes of operation Fig.13. It can be observed
that the VTC curve reaches ideal shape as VDD scales down.
Voltage
Dependence of power delay products (PDP) on supply
voltages is shown in Fig.14. The propagation delay product is
plotted as the supply voltage spans from 0.6 V to 1.3V it can
be seen that the propagation delay product increases rapidly
from 0.9V. So the optimal power supply is 0.9V for this
technology.

Fig. 13 average propagation delay of FinFET based inverters in various modes as a function of ȕ (a) shorted gate (b) independent gate (c) hybrid
mode

Fig. 12 voltage transfer characteristics of FinFET based inverters and its dependence on supply voltage scaling (a) shorted gate mode (b) independent gate
mode (c) hybrid mode
 Fig. 14 power delay product of FinFET based inverters as a function of supply voltage

Table I A comparative study of various parameters of an inverter implemented using different modes of FinFET for varying number of P--
FINS and N-FINS

Leakage Switching Total Power Delay Switching

PFINS, NFINS Delay (pS)
Power (nW) power (μW) Power(μW) Product (aJ) threshold (V)
SG (1,1) 21..21 3.78 3.80 1.84 6.96 0.37
IG (1,1) 21.20 3.76 3.78 2.50 9.40 0.48
IG-LP (1,1) (1.1/-0.2) 1.30 2.59 2.59 3.74 9.69 0.41
IG-LP (1,1)(1.1/0) 1.30 2.54 2.54 3.68 9.36 0.38
IG-LP (1,1) (0.9/-0.2) 21.20 2.63 2.65 3.77 9.91 0.42

SG (2,1) 42.41 4.71 4.75 1.45 6.81 0.47

IG (2,1) 42.39 3.76 3.80 2.50 9.40 0.48
IG-LP (2,1) (1.1/-0.2) 2.59 3.12 3.12 2.83 8.80 0.48
IG-LP (2,1)(1.1/0) 2.59 3.07 3.07 2.76 8.45 0.46
IG-LP (2,1) (0.9/-0.2) 42.39 3.11 3.15 2.77 8.63 0.50

SG (1,2) 21.21 4.41 4.43 1.85 8.15 0.30

IG (1,2) 21.21 3.84 3.86 3.36 12.91 0.32
IG-LP (1,2) (1.1/-0.2) 1.30 3.07 3.07 4.08 12.53 0.36
IG-LP (1,2)(1.1/0) 1.30 3.03 3.03 4.01 12.15 0.32
IG-LP (1,2) (0.9/-0.2) 21.21 3.19 3.21 3.86 12.34 0.37

Table II A Comparison of Transmission gate, Multiplexer, Latch and Flip-flop implementation using Shorted Gate (SG) mode and
Independent Gate- Low Power (IG-LP) mode of FinFET

Parameters Transmission gate Multiplexer Latch Flip-Flop

SG IG-LP SG IG-LP SG IG-LP SG IG-LP
Rise Time (pS) 4.287 3.504 4.180 4.410 9.972 12.465 9.903 12.341
Fall Time (pS) 2.955 2.799 3.513 3.508 10.372 12.869 10.23 12.759
Low to High propagation delay (pS) 0.734 0.667 0.746 0.869 7.566 10.417 6.287 7.971
High to Low propagation delay (pS) 0.705 0.661 0.880 0.858 7.455 10.383 5.399 7.554
Average delay (pS) 0.720 0.664 0.813 0.863 7.510 10.400 5.843 7.763
Average Power (μW) 1.501 1.464 2.166 2.017 11.179 5.626 24.965 11.399
Power Delay product (aJ) 1.080 0.973 1.762 1.742 83.964 58.513 145.88 88.493
 ) FinFETs," in IEEE Transactions on Electron Devices, vol. 61, no. 4,
E. Flip Flop pp. 1123-1130, April 2014.
A negative edge triggered Flip-Flop as shown in Fig.7 is [5] K. Kang, H. Jeong, Y. Yang, J. Park, K. Kim and S. O. Jung, "Full-
Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET
implemented, the MUX is realized using TG designed Technology for Low-Voltage Operation," in IEEE Transactions on
earlier. The detailed results are tabulated in Table II. It can Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, pp.
be clearly observed that the power delay product (PDP) of 1342-1350, April 2016.
the circuits implemented in IG-LP is at-least 50% better [6] Nam Sung Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, Jie S.
than the SG mode. It can also be observed that the TPHL and Hu, M. Irwin, M. Kandemir and V. Narayanan, "Leakage current:
Moore's law meets static power", Computer, vol. 36, no. 12, pp. 68-
TPLH are almost equal in case of IG-LP where as in the SG 75, 2003.
mode they vary a bit more. [7] Chenming Hu, J. Bokor, Tsu-Jae King, E. Anderson, C. Kuo, K.
Asano, H. Takeuchi, J. Kedzierski, Wen-Chin Lee and D. Hisamoto,
VI. CONCLUSION "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm",
IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, 2000
Based on the analysis done on FinFET the following [8] J. Colinge, FinFETs and other multi-gate transistors, 1st ed. New
conclusions are drawn and can be used as general guidelines York: Springer,2008.
for the design of FinFET circuits for digital applications [9] S. A. Tawfik and V. Kursun, "Low-power and compact Sequential
circuits with independent-gate FinFETs," IEEE Transactions on
• In order to reduce power consumption, one should Electron Devices, vol. 55, no. 1, pp. 60–70, Jan. 2008.
prefer IG mode over SG mode. [10] J. M. Rabaey, A. P. Chandrakasan, B. Nikolic, C. Rabaey, and N.
rakasan, Digital Integrated circuits: A design perspective. New Delhi,
• IG-LP mode of FinFET in (1.1,-0.2) gives a better India: Prentice-Hall of India Pvt., 2009.
voltage transfer characteristic (VTC) curve. [11] A. N. Bhoj and N. K. Jha, "Design of logic gates and flip-flops in
• SG has the minimum PDP among the three types of high-performance FinFET technology,"IEEE Transactions on Very
inverters. Large Scale Integration (VLSI) Systems, vol. 21, no. 11, pp. 1975–
1988, Nov. 2013.
• The number of fins used for IG mode of FinFET is
less compared to SG mode of FinFET, due to
effective usage of back gate in IG mode of FinFET.
• Proper range of VDD is from 0.8V to 1.1V. Mostly
0.9V is used. Reduction of VDD results in the ideal
VTC for an inverter, but this is not desirable since
the noise margins degrade drastically.
• In terms of speed, SG mode Latches/Flip-Flops
give better results, whereas in other cases such as
power and area, IG-LP mode Latches/Flip-Flops
perform better.
• Transistor sizing for equal TPLH, TPHL at the output
are as follows SG mode (ȕ=2.2), IG mode (ȕ=2.1)
and IG-LP mode (ȕ=2.25)
• For transmission gate, either in SG mode or IG-LP
mode, the number of p-fins and n-fins is equal to 1.
• While designing Flip-Flops, Transistor sizing is a
key parameter, based on output size of transistors,
sizing of preceding stage changes. For example, if
output stage has 2/1 sizing, preceding stage need
4/2 size, to drive the output stages correctly.

REFERENCES

[1] R. R. Schaller, "Moore's law: past, present and future," in IEEE

Spectrum, vol. 34, no. 6, pp. 52-59, Jun 1997.
[2] V. De and S. Borkar, "Technology and design challenges for low
power and high performance [microprocessors]," Proceedings. 1999
International Symposium on Low Power Electronics and Design (Cat.
No.99TH8477), San Diego, CA, USA, 1999, pp. 163-168.
[3] A. Asenov et al., "Variability Aware Simulation Based Design-
Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM
Cooptimization," in IEEE Transactions on Electron Devices, vol. 62,
no. 6, pp. 1682-1690, June 2015.
[4] P. K. Pal, B. K. Kaushik and S. Dasgupta, "Design Metrics
Improvement for SRAMs Using Symmetric Dual- k Spacer (SymD- k