Technology challenge of TMSC’s claim of

3nm EUV at year 2022

Introduction:
Miniaturization puts more transistors per square inch on an IC doubling the computing power every two
years this is known as Moore’s Law. This trend continued from 1975 to 2004 but the law seems to be dead
because of limitations of materials and production processes.
Search for alternative material and Production process are still being able to revive moor’s law i.e.
In(GaAs) quantum well transistors (TEFT) providing a wider band gap, graphene sheets and nanowire FETs
provide better electrostatics at relaxed nanowire diameter. Processes like Deep ultraviolent (DUV) and
extreme ultra-violent (EUV) lithography.
Feature size(lithography) = k1 λ/ numerical aperture (N.A.)
N.A.=ηSinθ
η= refraction index
thus featuring size can be controlled by controlling λ and N.A.
Extreme ultraviolet lithography (EUVL) type of optical lithography uses wavelengths in the range of 11 to
14 nm shrinking the size and keeping k1 values at acceptable levels. The technology achieves good depth
of focus and linearity for both dense and isolated lines with low-NA systems without OPC. The robust 4X
masks are patterned using standard mask writing and repair tools, and similar inspection methods can be
used as for conventional optical masks. The low thermal expansion substrates provide good critical
dimension control and image placement. Experiments have shown that existing DUV resists can be
extended for use with EUV. Chip makers are hoping it will allow them to extend Moore’s Law another 10
years, but EUV technology “it is too expensive and uses too much power.”

The News:
TSMC announces plans for $16 billion foundry to push the envelope on 5nm, 3nm process nodes as early
as 2022 as it aims for industry leadership, the news came recently, TSMC will need 50 to 80 hectares (123
to 198 acres) of land for an investment worth about NT$500 billion ($15.7 billion). The Company’s
planned advanced 3nm fab will be located in the Tainan Science Park to fully leverage the company’s
existing cluster advantage and the benefit of a comprehensive supply chain. TSMC recognizes and is
grateful for the government’s clear commitments to resolve any issues, including land, water, electricity
and environmental protection. 46% Increase in Electricity Usage by TSMC around 720 megawatts of
electricity is required by 5nm and for 3nm fab would require more energy because of EUVL integration.
The ASML Claims Major EUV Lithography Milestone. ASML is the only company in world to claim this,
Intel, global Foundries Samsung and TSMC have highly funded and invested in this project. TSMC orders
an EUV lithography system from ASML. TSMC will be the first dedicated foundry conducting onsite EUV
development. A report in the financial weekly Barron’s cited an analyst who said TSMC had ordered five
of them at a cost of US$550 million.
Challenges for EUV technology:
Following are the technical challenges that are hurdles for EUVL technology industrialization.
 Flare Evaluation:
Flare is the undesired scatter light due to the surface roughness of the reflective optical components and
masks used in EUVL. Because flare is inversely proportional to squared wavelength and the wavelength of
the light used in EUVL is only 13.5 nm, EUVL suffers from rather high flare level. In addition, the non-
uniformity of pattern distribution and the flare periphery effect (the central region of a chip receives much
more flare than the peripheral region) result in large flare variation across a chip. Both the high flare and
variation can damage the control of CD uniformity.
 Shadowing Effect:
The incident light in EUVL has an angle (usually 6◦) relative to the axis perpendicular to the mask plane.
Consequently, the oblique illumination and absorber thickness result in shadows around patterns
represented by the absorber shapes, making patterns wider during an exposure process.
 Heat dissipation (power loss):
Both the dramatic decrease in feature sizes of semiconductor devices and the high-resolution
requirement make high-voltage single e-beam lithography systems popular in photomask fabrication. An
input layout is first split into subfields and the patterns are written by beam deflection and stage
movement. Conventionally, the high-voltage beams write subfields in a contiguously sequential manner,
causing considerable amount of heat deposited in a small area and resulting in CD distortion
 EUVL resist process:
Resolution enhancement and roughness reduction are urgent in resist technology. Infrastructures such as
outgas inspection and advanced exposure tool should be prepared as a development platform.

Opinion:
 Since Wafer foundries are energy hungry due to use of advance and sophisticated technologies, the
biggest challenge is high-power light sources, one need almost 180 watts of power as your baseline,
in my opinion usage of fiber lasers instead of traditional LASERs can help in reduction of power
requirement this is in just lab scale, it can also help in tackling heat dissipation problem.
 The exploding tin droplets create a great deal of debris in the machine that is not easily cleaned out
thus contamination in my opinion more cleaning standards can help in reduction of this problem.
 Creating defect-free masks (the mirrors on which the pattern of the chip to be produced is written).
So-called line-edge roughness (current leakage) is another problem, more leakage more power,
fundamental cause of line-edge roughness is an interaction between the optics and the photoresist.
 Cooling System also a Question mark and main culprit is heat dissipation, experimental EUV at NTU
has a power output of only a 0.001 W, but the cooling system takes up a full room, with massively
bigger power outputs, dissipating the heat will be a complex technical challenge plus cooling systems
also consume a lot of energy. This heat dissipation (power loss) in my opinion can be due to the
presence of grain boundaries in lattice of crystal structure, enhancing the purer form of crystal can
solve this problem.
References:
1. EUV and E-Beam Manufacturability: Challenges and Solutions, (ieeexplore.ieee.org).
2. Extreme Ultraviolet Lithography Still Beset by Problems, (spectrum.ieee.org).
3. Challenges and solutions for extreme ultraviolet lithography at 22nm, (spie.org).
4. Technology challenges in silicon devices beyond the 16 nm node, (www.researchgate.net).
5. Areas of Focus and List of Challenges for EUV Lithography at 7nm, 5nm and 3nm Nodes,
(www.electroiq.com).
6. EUV lithography update (spie.org).
7. Three different roads to the 3-nanometer chip, (www.theregister.co.uk).
8. TSMC announces plans for $16 billion foundry to push the envelope on 5nm, 3nm process nodes,
(www.extremetech.com).
9. TSMC to Build 3nm Fab in Tainan Science Park, (www.tsmc.com).
10. Can Taiwan Power TSMC’s Dream? (english.cw.com.tw.).
11. Extreme ultraviolet lithography, (en.wikipedia.org).
12. ASML Claims Major EUV Lithography Milestone (www.extremetech.com).
13. Extending EUV Beyond 3nm (semiengineering.com).
14. TSMC Aims to Build World’s First 3-nm Fab (www.eetimes.com).
15. Multi-Patterning Issues at 7nm, 5nm (semiengineering.com)