Parasitics in VLSI Circuits
and the Role of Layout Verification
N.P. van der Meijs, A.J. van Genderen and T. Smedes
Delft University of Technology, Faculty of Electrical Engineering
P.O. Box 5031, 2600 GA Delft, the Netherlands
Abstract
Integrated circuits consist of active devices
and an interconnection network fabricated on
a semi-conducting substrate. The properties
of the interconnections and the substrate are
increasingly important factors affecting the
performance and operation of the circuit as
a whole, amplifying the need for layout verifi-
cation. In this paper, we discuss the behavior
of IC interconnections and substrates, their
electrical significance, and what constitutes
an effective model for them. We conclude by
reviewing the increased importance and new
requirements of post-layout design verifica-
tion.
1 Introduction
The properties of IC interconnections and the
substrate are increasingly important factors
affecting the performance and operation of
an IC. They must be considered in the IC de-
sign loop. A failure to do so may result in
lower than expected performance, higher than
expected dissipation and/or unreliable or in-
correct circuit behavior.
In this paper, we will review appropriate
models and scaling behavior of IC intercon-
nections, based on the analysis in [1]. Then,
we will discuss two examples of undesired
behavior caused by interconnect parasitics
and the problem of substrate noise. We con-
clude by discussing the new requirements of
IC verification tools.
2 IC Interconnection Modeling
The electromagnetic behavior of IC intercon-
nections is governed by Maxwell’s equations.
Because of the complexity of solving these
equations, approximations are needed. An
important approximation leads to the model-
ing of IC interconnections as a set of lossy
coupled transmission lines. They are usu-
ally considered otherwise ideal, i.e. linear,
frequency-independent, without skin effect,
etc. Except for diffused conductors, this is
usually an accurate approximation of IC in-
terconnections when the operating frequen-
cies are below 1 Ghz. However, in many
cases (depending on e.g. the source, load,
line length and frequency), much simpler ap-
proximations are also accurate. In this sec-
tion, we will discuss the applicability of such
approximations.
For that purpose, let us first introduce the fol-
lowing notation:
l Length of an interconnection.
r, c, h Resistance, capacitance, induc-
tance of a line, per unit length.
R, C , L Total resistance, capacitance, in-
ductance of a line.
The following equations are useful for calcu-
lating the delay caused by a line. The RC
delay of a lossy line is given by:
tRC = 21 rcl2 = 21 RC (1)
In the case of lossless and homogeneous
transmission lines, supporting TEM waves,
Table 1. Typical IC interconnect parameters. Table 2. Dominant circuit components for
rpoly 20
/m interconnections in typical technologies.
rmetal 20 m
/m technology, wire dominant
c 150 aF/m current level length circuit elements
h 0.5 pH/m FET short C
v 1.2 cm/ns low long C, R
Z0 60
FET short C, R, (L)
high long C, R, L
h and c are related as Bipolar short C
low long C, R, (L)
hc =  ; (2) Bipolar short C, L, (R)
with  and  the permittivity and permeabil- high long C, R, L
ity of the medium, respectively. Although
Equation (2) is only valid for a single line Current level. For power lines, supporting
and IC interconnections are neither lossless large currents with large spikes, Faraday’s
nor homogeneous, it is usually an acceptable law can determine the significance of line in-
approximation. ductance. The resulting noise is proportional
For TEM lines, the characteristic impedance to LdI =dT , and is called dI=dT noise [1].

q
Z0 and propagation speed v are given by

Signal rise time and driver impedance.
When the signal rise time tr tRC or
= L=C 
= 1=p = c0=prr
Z0 (3)
tr tLC , the RC or LC delay of the line
v (4) can be ignored, respectively. Furthermore,
with c0 the speed of light in vacuum and r while tr obviously depends on the circuit
and r the relative permittivity and perme- characteristics and speed of the signal that
ability of the medium, respectively. On sil- drives the line driver, it also depends on the
icon IC’s, v varies between 0:3c0 and 0:5c0 ratio between driver impedance Zs and line
[2]. Equations (2) and (4) can be combined impedance Z0 . It turns out that if Zs  Z0 ,
to give the transmission line delay tLC of a the line inductance can be ignored.
line:
tLC = l=v = l p
 =l
p hc =
p LC (5)
The results of this section are summarized in
Table 2, which is adapted from [3].

For standard technologies a value of 150

aF/m is a useful estimate for c. With
v = 0:4c0 , the above equations determine h
and Z0 as given in Table 1. This table also
contains typical values of other IC intercon-
nect parameters, but not all types of parasitics
are always equally significant. This depends,
for example, on the following.
Length of the interconnection. For exam-
ple, we can neglect the inductive behavior of
signal lines when tRC 
tLC . By compar-
3 IC Interconnection Scaling
The continuous improvement in the charac-
teristics of integrated circuits is the result of
scaling. With scaling, physical dimensions
are reduced. As a result, the speed of the
devices and the circuits improve. In order
to avoid problems caused by strong electrical
fields, voltages should also be reduced and
doping levels increased. Since this would in-
troduce many other practical problems, pro-

p
ing Equations (1) and (5), we find that this is portional scaling of voltages and doping lev-
equivalent to RC LC or els is not strictly applied in practice. Yet, it
q
= rl 
is usually assumed in the analysis of scaling
R L=C = Z0 (6) to more clearly illustrate its trend.
Table 3. Ideal scaling of MOS devices [4].
parameter factor
physical dimensions 1=S
substrate doping S c
voltages 1=S
intrinsic device delay 1=S
device area 1=S 2
device power 1=S 2
Because it ignores many second order effects,
uniform scaling as defined above is called
ideal scaling [4]. Typical results are sum-
marized in Table 3. In what follows, we will
present the scaling relations for interconnec-
tion parasitics.
We first distinguish between local and global
interconnections. Local interconnections are
between individual devices, and their length
is proportional to 1=S . Global interconnec-
tions are between modules on a chip. Their
length is proportional to the size of the chip,
which increases with every new technology
generation. When SC is used to denote this
chip scaling factor, the length of the global
interconnections is proportional to SC .
Now, note that the unit-length interconnect
resistance r is inversely proportional to the
interconnect cross-sectional area, and thus
scales as S 2 . Furthermore, the unit-length
interconnect capacitance c is, in the case of
ideal scaling, constant.
Together with the scaling behavior of l, the
RC
/
delay scaling of interconnections is thus
described by RC = rcl2 l2 S 2. Since the
intrinsic gate delay scales as 1=S , the ratio
between the local interconnect delay and the
gate delay increases by a factor of S and the
ratio of the global interconnect delay and the
gate delay increases by a factor of S 3 SC 2 .
These results are summarized in Table 4 in
the column labeled ‘ideal’. (The column la-
beled ‘lateral’ is explained below.)
So, with ideal scaling, the performance of a
chip is determined to an increasing extent by
the interconnections. The problem is so se-
vere that ideal scaling cannot strictly be ap-
Table 4. Scaling of interconnection delay.
parameter ideal lateral
unity r S2 S
1 1
local l 1=S 1=S
tRC /tDEV S 1
global l SC SC
tRC /tDEV S 3S 2 C S 2S 2C
tLC /tDEV SC S SC S
plied. Instead, the lateral dimensions of the
interconnections are scaled more than the ver-
tical dimensions.
Another reason to maintain the thickness
of the interconnections is the occurrence of
electromigration. When the current density
in a metal line exceeds a certain material-
dependent value, material of the line is dis-
placed and the line can break, resulting in
an open circuit. Thus, the current conduc-
tion capability of interconnections must be
maintained by (relatively) large vertical di-
mensions.
For purposes of illustration, we will consider
the case in which vertical dimensions are not
scaled at all, which we will call lateral scal-
ing. The results are also indicated in Table
4, assuming that c remains constant. While
this is not strictly the case, it is justified for
practical linewidths [5].
The scaling of IC’s also deteriorates crosstalk
and signal-to-noise ratios, and the detailed
behavior again depends on what type of scal-
ing is applied. For example, in the case
of ideal scaling, cground =ccoupling is indepen-
dent of S , but in the case of lateral scaling,
cground =ccoupling/ S because of the change
in cross-sectional shape of the conductors.
Moreover, severe problems are also likely to
occur with the on-chip power distribution.
Both the resistive and inductive noise volt-
age drops will increase because of the scal-
ing properties of the interconnection parame-
ters, but also because reduced voltages and
increased frequencies both imply increased
currents. The combined effect of increased
 Table 5. Scaling of signal-to-noise ratios.
parameter ideal lateral
cground =ccoupling 1 S
IR noise S 3 SC 2 S 2 SC 2
SN R (IR) 1 / S 4 SC 2 1 / S 3 SC 2
LdI=dt noise S 3 SC 2 S 3 SC 2
SN R (dIdt) 1 / S 3 SC 3 1 / S 3 SC 3

25fF
50fF

25fF
50fF Figure 2. SPICE analysis of the network and
25fF
50fF response
excitations in Figure 1.
25fF
50fF
vdd out
25fF
fast nominal slow crosstalk

Figure 1. Five-conductor bus illustrating the

effects of coupling capacitance.

noise and decreased operation voltages ac-

counts for severe deterioration of signal-to-
noise ratios, as summarized in Table 5.
in vss

4 Examples Figure 3. Example of a CMOS driver layout.

Consider the case of five parallel lines as
shown in Figure 1. Each line is driven by
=2 diffusion resistance. The
an inverter and different input patterns (ex-
citations) are applied as shown. Each exci-
tation has a label that indicates the resulting
behavior at the far end of the middle line,
and the result of SPICE simulations is pre-
sented in Figure 2. The waveforms show the
output of the middle line in Figure 1, labeled
‘response’. The timing and shape of the ex-
citations is indicated by the signal ‘in 1’ in
Figure 2. The simulation illustrates that the
delay of a signal can depend on the wave-
forms of neighboring lines.
Also consider the CMOS driver layout in Fig-
ure 3. The parasitic drain and source resis-
tances severely limit its performance, as can
be seen from the SPICE simulation in Fig-
ure 4. This simulation compares the output
waveform of the driver when interconnect re-
sistance is ignored to that when the driver is
modeled as in Figure 5. This simulation as-
sumes 15 nm gate oxide, 40pF load capaci-
tance and 75
signal rise time changes from 15.4 ns to 27.4
ns.
5 Substrate Modeling
The traditional ‘ideal ground plane’ model
of the substrate of VLSI chips is becom-
ing invalid in a growing fraction of all the
chips that are designed. Instead, its semi-
conducting nature must be taken into account
to predict various parasitic couplings between
distant subcircuits. For example, in mixed
signal IC’s, the digital parts can induce noise
into sensitive analog parts.
A typical example of substrate coupling is il-
lustrated in Figure 6. Because of the switch-
ing actions in the digital part, a spike is intro-
duced on the interconnect between the bias
bondpad and the substrate contact. Via the
resistive bulk, this spike reaches the feed-
back resistor of the amplifier circuit, and de-

Figure 4. SPICE simulation of the CMOS
driver.
vdd
in
vss
Figure 5. Equivalent network of the CMOS
driver.
grades its signal-to-noise ratio. The problem
can lead to rather unexpected system behav-
ior if the digital noise is concentrated in a
narrow frequency band, for example around
the digital clock frequency.
The problem can be seen as a sender-
medium-receiver problem. The senders are
the sources of ‘substrate pollution’. These
senders can, for example, be the substrate
contacts or the collector substrate junctions.
RI + LdI/dT
L
L R
VSS
DIGITAL
Substrate Contact
The medium is the substrate itself. Depend-
ing on the fabrication technology, this can
consist of a number of layers such as bulk
layer, epi layer and channel-stopper layer,
with particular doping levels. For VLSI ver-
ification purposes, it will usually be accept-
able to neglect minority carriers and to only
consider the resistive nature of the substrate.
With very high frequencies, however, the
substrate must be treated as a lossy dielec-
tric [2]. The receivers are the sensitive nodes
of the circuit. For example, the MOS drain-
source current can be modulated by the sub-
vdd strate noise via the body effect.
While substrate noise has been a practical
problem before [6]. it will become a far
greater problem with scaling because of the
following. (1) The senders will become
out
stronger. For example, the RI +LdI=dt noise
in Figure 6 scales as indicated in Table 5. (2)
The receivers will be more sensitive. For ex-
ample, with thin gate oxides the body effect
increases. (3) The devices will be closer to-
vss
gether, giving stronger transmission.
6 Conclusion
The analysis in Section 2 clearly demon-
strates the growing significance of IC inter-
connect parasitics. While it can be argued
that the presented examples are somewhat
extreme1, it can also be argued that many
circuits cannot tolerate even a fraction of the
parasitics assumed in that analysis. Such
circuit examples are easily found in analog
circuits, digital circuits employing precharge
schemes and/or tri-state buffers, memory ar-
rays employing sense amplifiers and so on.
For example, a discussion of the capacitive
Analog
Output coupling problem for bit lines in DRAM’s
Diffused
can be found in [7].
Resistor
In particular, the crosstalk example showed
-
that large coupling capacitances between par-
+

Silicon 1However, the CMOS driver example corresponds

to a real industrial design that after fabrication did not
Figure 6. Illustration of a substrate coupling perform as expected, because the interconnect resis-
tance was neglected during design and simulation.
problem.
allel lines can cause uncertain delay because
signal waveforms can depend on the sig-
nals on neighboring lines. This effect makes
the problem of predicting electrical behavior
more difficult, and virtually mandates exten-
sive post-layout verification. Alternatively,
large safety margins that reduce performance
and/or increase area must be maintained dur-
ing the design phase.
With respect to substrate noise, note that it
has been a practical problem before [6], but
today it can even lead to the necessity of sep-
arating analog and digital functions into two
chips [8]. However, when considering the
scaling analysis in Section 5 together with
the fact that the required precision of analog
subcircuits generally increases, it is clear that
substrate noise will become an even more im-
portant design issue.
Since parasitics are becoming much more im-
portant and abundant, they must be extracted
automatically, without requiring a designer to
first identify them. Moreover, the extraction
accuracy should be high in order not to re-
quire uneconomically large safety margins.
Consequently, a new generation of design
verification tools is being developed [9]. See,
also, [5] and [10] and the references therein,
as well as and [11] for a numerical technique
for calculating a substrate model.
Of course, the list of important (emerging)
layout verification topics is not exhausted by
the discussion in this paper. For example,
the topics of reliability verification [12], ther-
mal verification [13] and latchup verification
[14] are also being studied. Interestingly, the
problems of thermal and latchup verification
are mathematically strongly related to that of
substrate noise.
Of course, IC designers can and will develop
guidelines and techniques to cope with the
problem. Nevertheless, new verification tools
will help to obtain a competitive advantage.
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