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Flash Analog-to-Digital (ADC) Converter

Avelino, Anne Loraine L., Galang, Vincent N., Nañoz, Allona Jane M., Punzalan, Justine Roy A.
College of Engineering
School of Technology
First Asia Institute of Technology and Humanities

Abstract— This paper aims to create a simulation and an actual ADC is the fastest kind of analog-to-digital converter. The actual
design of a 3-bit flash analog-to-digital converter (ADC) using op implementation of the ADC uses 8 op amps to produce the desire
amps and priority encoder. 3-bit digital outputs.

Flash analog-to-digital converter (ADC) was generated in this The circuit in Figure 2.1 shows the basic configuration of the
experiment. In this paper, it features three segments: Flash ADC Flash ADC. This circuit is also the basis in the simulation. The
section, the inverter and encoder section and the seven-segment reference voltage is set to 8V. However, in biasing the resistors,
display section. the circuit in Figure 2.2 was followed. The resistor is set to 1kilo-
ohms and thus, the first and last resistors were 1.5 kilo-ohms and
Flash ADC, also called the parallel A/D converter, is the 500 ohms respectively.
simplest to understand. It is formed of a series of comparators,
each one comparing the input signal to a unique reference voltage.
The comparator outputs connect to the inputs of a priority encoder
circuit, which then produces a binary output.

Not only flash converter is the simplest in terms of operational

theory, but it is the most efficient of the ADC technologies in
terms of speed, being limited only in comparator and gate
propagation delays. Unfortunately, it is the most component-
intensive for any given number of output bits. In order to
determine the number of comparators, use the formula: 2 n-1. The
three-bit flash ADC requires seven comparators (23-1). A four-bit
version would require fifteen comparators (2 4-1). With each
additional output bit, the number of required comparators
doubles. Through this, the flash methodology quickly shows its

An additional advantage of the flash converter is the ability for

it to produce a non-linear output. With equal-value resistors in the
reference voltage divider network, each successive binary count
represents the same amount of analog signal increase, providing
a proportional response.

Lastly, ADCs are used virtually everywhere where an analog

signal has to be processed, stored or transported in digital form.
Some examples are cellphones, digital voltmeters and digital
oscilloscope. Figure 2.1: Flash Analog to Digital Converter


3-Bit Flash ADC Converter (Simulation and Actual


A flash ADC (also known as a direct-conversion ADC) is a

type of analog-to-digital converter that uses a linear voltage
ladder with a comparator at each "rung" of the ladder to compare
the input voltage to successive reference voltages. The Flash

Figure 2.4: Seven-Segment Display

The seven-segment display in Figure 2.4 is a common

cathode display. The display needs a decoder to identify the given
input. The said input is the output of the priority encoder. The
output of the priority encoder needs to be inverted as well before
connecting to the decoder.

This inversion of inputs and outputs is done in the actual

Figure 2.2: Bias Resistors of the ADC implementation and later explain in this section.

Figure 2.5: Actual Circuit Implementation of ADC

Figure 2.3: Priority Encoder Figure 2.5 shows the actual circuit implementation of the
ADC. This is divided into three parts (which is separated into
The priority encoder used in Figure 2.3 is 74148 IC. The three breadboards as shown): The Flash ADC section, the inverter
IC is an active-low priority encoder with 8 inputs and three bit and encoder section, and the seven-segment display section.
binary outputs. That’s why there is a need to invert the output of
the comparators before connecting to the IC. This is done in the The Flash ADC section is composed of the comparators.
actual implementation of the circuit. In the actual implementation, the reference voltage was increased
from 8V to 16V. This is to adjust the precision in the output.

The inversion of the outputs of the comparators is to
comply with the logic input of the encoder. The encoder needs a
logic 0 input in the MSB to give a binary output of 111. However,
the first output of the encoder for decimal “7” is logic 000. But
the decoder needs logic 111 for the “7”, and thus the binary output
is to be inverted.

Other changes applied are the maximum swing of the

comparators, and the addition of the inverters as discussed earlier.
The maximum swing applied in the actual circuit is +5V and -5V.


The design of a Flash converter was used to demonstrate the Figure 3.1
Analog-to-Digital Converter in actual. This design is considered
to be the fastest ADC, which is the side-effect of the unequal Complement to the computation of the ideal voltage, the
values of resistors. actual input voltage of each comparator is measured. The
counterpart of the 1V is 1V, as shown in Figure 3.2.
Setting a constant of 16V as the reference voltage, and a
maximum voltage swing of ±5V in each comparator, the results
of the ADC are then determined.

Computations for the ideal input voltage for the comparator is

performed and set to be the basis of the simulation and also a basis
of for the actual. The computations are shown below.

𝟎𝟎𝟏 = (16 𝑉) = 𝟏𝑽
7.5𝑘Ω + 500Ω
𝟎𝟏𝟎 = (16 𝑉) = 𝟑𝑽
6.5𝑘Ω + 1500Ω
𝟎𝟏𝟏 = (16 𝑉) = 𝟓𝑽
5.5𝑘Ω + 2500Ω Figure 3.2 Figure 3.3
𝟏𝟎𝟎 = (16 𝑉) = 𝟕𝑽 Figure 3.3 shows the counterpart of 3V which is of the
4.5𝑘Ω + 3500Ω
same value. Meanwhile, Figure 3.4 is the counterpart of 5V which
4500Ω is equal to 5.01V and Figure 3.5 shows the equivalent of 7V
𝟏𝟎𝟏 = (16 𝑉) = 𝟗𝑽
3.5𝑘Ω + 4500Ω which is 7.01V.
𝟏𝟏𝟎 = (16 𝑉) = 𝟏𝟏𝑽
2.5𝑘Ω + 5500Ω

𝟏𝟏𝟏 = (16 𝑉) = 𝟏𝟑𝑽
1.5𝑘Ω + 6500Ω

This concludes that the input voltage to have an output

of a binary 001 is 1V. For 010 is 3V, for 011 is 5V, for 100 is 7V,
for 101 is 9V, for 110 is 11V, and for 111 is 13V. Summarized
results of the output with respect to its corresponding input is
plotted and shown in Figure 3.1.

Figure 3.4 Figure 3.5

The Figure 3.6 shows a voltage reading of 9.02V which

is the counterpart of 9V and Figure 3.7 shows the equivalent of
the 11V, which is equal to 11.02V. Then, the Figure 3.8 shows a
voltage of 13.03V which is the counterpart of the 13V.
Figure 3.10
Figure 3.6 Figure 3.7

Figure 3.11

Adjusting the input voltage to 1V, the simulated result

can be seen in Figure 3.12, which shows an output of 1 and the
LED indicator for the LSB is turned on (high). However,
Figure 3.8 performing the adjustment in actual, the same result will only be
achieved once the voltage is equal to 1.2V, which is evident in
Shown in Figure 3.9 is the summarized and plotted Figure 3.13. This is because the comparing voltage in the
values of the actual ADC output to be easily compared with its comparator is 1V and to satisfy this, the input voltage must be
ideal value. greater than it.

Figure 3.12

Figure 3.9

With an initial value of 00.2V in the input voltage

(VANALOG), it is shown in Figure 3.10 that the LED indicators are
all turned off (low). The three LED represents the binary output
of the ADC which means that the output of the 00.2V is 000.
When the circuit is simulated, the result is still the same as shown
in Figure 3.11.

Figure 3.13

Following the computation for the ideal input voltage, a
3V is set as the input voltage as shown in Figure 3.14. A digital
output of 2 can be seen in the seven segment display and the
second LED indicator is turned on, which represents 010 in

Figure 3.14

Figure 3.15 shows the same result as the simulated

Figure 3.17
circuit, the only difference is the voltage use in comparing with
the input. Testing the circuit in actual, an input voltage of 2V
already outputs the result of a 3V-input in the simulation. And
according to the measurement of the comparing voltage, it must
exceed 3V in order to output a binary 010.

Figure 3.18

According to the computations above, an output of 4 or

100 in binary, is achieved when the input voltage is set for about
7V. Using Multisim for simulation, the input must be equal to
7.1V to have the desired output as shown in Figure 3.18, which
complies with the comparing voltage of 7V for the ideal.

Figure 3.15

With an input voltage of 5V, equivalent to the computed

value above, a digital output of 3 is shown in Figure 3.16 and the
LED indicators display 011 in binary.

Figure 3.19
Figure 3.16
Figure 3.19 shows the results in the actual circuit. The
Similar to the previous case, in able to achieve the same input voltage which is supposed to exceed the 7.01V to produce
result as the simulation, their input voltages vary. Once the actual the desired result, is not complied for the circuit already produces
circuit is supplied with a greater value than the comparing voltage the desired output with only a 4V input. Comparing this case to
of the third comparator, 5.02V, the seven segment will display 3 the previous ones, it can be observed that the voltage difference
and the two LED indicators are turned on. However, with only a increases as the desired output increases.
3V input, shown in Figure 3.17, it has already the desired output.
This leads to an observation that the comparing voltage in each
comparator is not satisfied.

Figure 3.20

The input voltage is set to 9.1V and an output of 5 is

displayed in the seven segment. Also shown in Figure 3.20, the
LED indicators are 101 which is the binary equivalent for 5.

Figure 3.23

An input voltage of 7.6V is enough to output 6 (110),

shown in Figure 3.23, not complying with the comparing voltage
of 11.02V. This results to an estimated voltage difference of 3V.

Figure 3.24
Figure 3.21
Adjusting the input voltage to 13.1V, an output of 7 is
produced as displayed in the seven segment shown in Figure 3.24.
The testing of actual circuit is shown in Figure 3.21 with
The three LED indicators are all turned on representing a binary
the same output as the simulation. Instead of setting the input
equivalent of 111.
voltage that exceeds 9.02V to achieve an output of 5, only 5V is
needed to produce that output. Regarding the voltage difference
between the simulation and the actual testing, it can be observed
that the difference increments a value of 1 as the voltage

Figure 3.22

With an input voltage 11.1V shown in Figure 3.22, the

LED indicators used to determine the output shows 110 which is Figure 3.25
equal to 6 and is displayed in the seven segment.
Having an input of 11.7V, the result of a 13V comparing
voltage is already achieved in the actual circuit as shown in Figure
3.25. Similar to the actual simulations above, a voltage difference
is present although it is smaller now.

The input voltages of the computed values, the simulated

values, and the actual values differ from each other producing
different voltage differences. This is due to the change in the
reference voltage and the functionality of the operational
amplifier used. The reference voltage is supposed to be 8V but Computations for the Integral Non-Linearity (INL) error
the actual circuit became sensitive to changes and the range of using the formula, 𝑰𝑵𝑳 = 𝑰𝑵𝑳(𝒐𝒖𝒕) + 𝑫𝑵𝑳, is shown below.
output values are limited. That is why the group increased the
voltage reference to 16V to achieve a distinctive output value. 𝟎𝟎𝟎: 𝟎 + 𝟎 = 𝟎

The voltage difference between the computed and actual 𝟎𝟎𝟏: 𝟎 + 𝟎 = 𝟎

began with a value of 1. Then as the comparing voltage increases,
𝟎𝟏𝟎: 𝟎 + 𝟎 = 𝟎
the previous value of the voltage difference will be incremented
by 1. The highest voltage difference is 4V; it is when the output 𝟎𝟏𝟏: 𝟎 + 𝟎. 𝟎𝟏 = 𝟎. 𝟎𝟏
should be 101. After that, the voltage difference began to decrease
for the succeeding inputs. 𝟏𝟎𝟎: 𝟎. 𝟎𝟏 − 𝟎. 𝟎𝟎𝟓 = 𝟎. 𝟎𝟎𝟓

𝟏𝟎𝟏: 𝟎. 𝟎𝟎𝟓 + 𝟎. 𝟎𝟎𝟓 = 𝟎. 𝟎𝟏

Regarding the operational amplifier used, the
functionality of the LM741 is not stable, disregarding the main 𝟏𝟏𝟎: 𝟎. 𝟎𝟏 + 𝟎 = 𝟎. 𝟎𝟏
operation of the comparator which compares the voltage across
𝟏𝟏𝟏: 𝟎. 𝟎𝟏 + 𝟎. 𝟎𝟎𝟓 = 𝟎. 𝟎𝟏𝟓
the effective resistance and the input voltage.

Shown below is the computation for the Differential

Plot of the INL error results are shown in Figure 3.27
Non-Linearity (DNL) error using the formula, 𝑫𝑵𝑳 = below.
𝑽𝒘𝒊𝒅𝒕𝒉 (𝒂𝒄𝒕𝒖𝒂𝒍) − 𝑽𝒘𝒊𝒅𝒕𝒉 (𝒊𝒅𝒆𝒂𝒍)

𝑽𝒓𝒆𝒇 𝟏𝟔
𝟏 𝑳𝑺𝑩 = = 𝟑 =𝟐
𝟐𝒏 𝟐

𝟎𝟎𝟎 = 𝟎

𝟏− 𝟏
𝟎𝟎𝟎 𝒕𝒐 𝟎𝟎𝟏 = = 𝟎
(𝟑 − 𝟏) − (𝟑 − 𝟏)
𝟎𝟎𝟏 𝒕𝒐 𝟎𝟏𝟎 = = 𝟎
(𝟓. 𝟎𝟐 − 𝟑) − (𝟓 − 𝟑) Figure
𝟎𝟏𝟎 𝒕𝒐 𝟎𝟏𝟏 = = 𝟎. 𝟎𝟏
𝟐 3.27
(𝟕. 𝟎𝟏 − 𝟓. 𝟎𝟐) − (𝟕 − 𝟓)
𝟎𝟏𝟏 𝒕𝒐 𝟏𝟎𝟎 = = −𝟎. 𝟎𝟎𝟓 DNL error observed from three to five were
symmetrical. However, from digital value of five to six, DNL
(𝟗. 𝟎𝟐 − 𝟕. 𝟎𝟏) − (𝟗 − 𝟕) crossed center line (zero). As it approaches seven (final value)
𝟏𝟎𝟎 𝒕𝒐 𝟏𝟎𝟏 = = 𝟎. 𝟎𝟎𝟓
𝟐 DNL error is back to its positive value (0.005). Thus, the
(𝟏𝟏. 𝟎𝟐 − 𝟗. 𝟎𝟐) − (𝟏𝟏 − 𝟗) characteristic of DNL observed applies with the graph for INL
𝟏𝟎𝟏 𝒕𝒐 𝟏𝟏𝟎 = = 𝟎 error.
(𝟏𝟑. 𝟎𝟑 − 𝟏𝟏. 𝟎𝟐) − (𝟏𝟑 − 𝟏𝟏)
𝟏𝟏𝟎 𝒕𝒐 𝟏𝟏𝟏 = = 𝟎. 𝟎𝟎𝟓

The DNL error results above are plotted and is shown Upon simulation, Flash ADC worked smoothly on
in Figure 3.26. Multisim12 using LM741 as comparators. Its output is then fed
to the input of LM7148 (priority encoder) and works just fine. In
contrast to its actual simulation, the group encountered series of
problems along the way. Output voltage of operational amplifiers
was not stable. The group tried first to hook the voltage swing of
the op amp to ground (-) and +5V (+). Although outputs vary,
still, more than 1 V is equivalent to low output. This output cannot
be read as voltage low input for a priority encoder. This is
equivalent to high output which is acceptable since all indicators
were high with the given parameters above. Thus, grounding the
negative swing is inappropriate. The group found solution to the
Figure 3.26 problem by connecting negative voltage to the negative swing.

By doing so, outputs of op amps have now readable
outputs for the encoder. Moreover, an inverter is needed to negate
the outputs of the comparators before being fed to priority
encoder. This includes inverting the outputs of priority encoder
and leaving the enable input to ground. Also, the group found out
that as the voltage reference increases, accuracy of the output
becomes more evident. However, there is a limit in increasing
voltage reference because it can degrade the operation of

Therefore, voltage reference and the op amp’s

characteristics is a big factor in designing Flash ADC. Since a
very small difference results to very high output (that is,
multiplying gain to the difference), it is important that a negative
supply is imposed on the negative swing of the comparator rather
than connecting it to ground.

Anne Loraine L. Avelino

Vincent N. Galang

Allona Jane M. Nañoz

Justine Roy A. Punzalan

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