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SOC FloorPlanning Article PDF
SOC FloorPlanning Article PDF
Floor planning is among the most crucial steps in the design of a complex system-on-a-chip (SoC), as it
represents the tradeoffs between marketing objectives and the realities of silicon at the targeted process
geometry. We will begin by describing the impact on Moore’s Law of successive generations of silicon
design. Then, we will detail the opportunities that next-generation silicon provides to marketing in
creating the functionality of a new design. An explanation of the growing need to implement security in
next-generation SoC designs follows. Next, the discussion details the tradeoffs the design architect
makes to accommodate large third-party intellectual property (IP) blocks, including memory. It
concludes with a description of the give and take between adding peripherals to the SoC and the impact
on the SoC’s I/O pads and silicon area.
Background
Creating an SoC destined for today’s portable consumer electronics products presents a challenge for
both engineering and marketing in a semiconductor company. Both teams must make tradeoffs between
market demands, competitive pressure, and the engineering constraints of getting a design into silicon
in a narrow market window. Consider the competitive pressure confronting semiconductor
manufacturers to create the chips that system manufacturers demanded after Apple introduced the iPad.
The die area and its floor plan drive marketing and engineering to make the tradeoffs needed to bring a
design to market. Ultimately, the system architect determines the final die size and floor plan. This
discussion will examine the forces that determine what the final floor plan will be. Beginning with the
realities of Moore’s Law, the discussion next examines marketing’s contribution to the design
requirements. It will then explore silicon and I/O pads cost and the role each plays in determining the
SoC’s functionality.
2. During floor planning, an SoC architect may use a placement tool such as Cadence’s Encounter Digital Implementation
(EDI) System to enable the automatic creation and implementation of multiple power domains to implement on-chip power
management systems. (courtesy of Cadence Design Systems)
During floor planning, an SoC architect may use a placement tool such as Cadence’s Encounter Digital
Implementation (EDI) System to enable automatic creation and implementation of multiple power
domains to implement on-chip power management systems (Fig. 2). Block placement within each
domain is connectivity aware, with well-connected blocks staying together. This reduces the net length
and improves the efficiency of the final layout. The architect may refine the results further by providing
the tool with additional constraints such as no overlaps, either within boundaries or with respect to net
criticality.
The processing units are a critical element in the SoC floor plan because of the area and power they
consume, which directly affects the user experience by comprising a more responsive, more feature-
rich, power-efficient device. When it comes to power, the architect also has two components to
consider: static and dynamic power consumption.
The foundry process determines static power consumption. All CMOS processes leak whether the
circuit is operating or not, so long as the circuit is powered on. Varying the voltage will reduce leakage,
but varying it too much affects functional behavior. Dividing the design into power islands and then
turning off inactive islands will reduce leakage to zero but may require some state restoration latency
when the circuit is to be used again.
Dynamic power is the power required to produce work, whereas static power is the cost of having the
power on. We derive dynamic power consumption using a simple equation:
PD = CV2f
where C is the capacitance at the node, V is the voltage at which the node switches, and f is the
switching frequency. A common technique for optimizing dynamic power is to employ hardware
accelerators to perform functions that would have otherwise been a software-intensive, power-
consuming load on the CPU.
Accommodating SRAM
One commodity in abundance on next-generation SoCs is SRAM. It often feeds the on-chip processors’
enormous appetite for data bandwidth. SRAM is ideal in SoC designs because it is standard CMOS-
compatible and requires no added steps during manufacturing. SRAM is an easy answer to the
designer’s question of what to do with the enormous number of additional transistors that become
available with each new process generation.
SRAMs provide caches for on-chip CPUs, such as scratch pads for holding motion-estimation results
for video codecs and still-image data. SRAMs offer a power-efficient alternative to operating out of
external DRAM, especially during sleep mode. External accesses to DRAM consume power from
switching I/O voltage. We might add additional SRAM if it lends more capability or power efficiency
to the design and there is silicon real estate to accommodate it.
3. The system architect must be able to easily add and edit I/O constraints to configure the sides and order of the pads as
well as and the layer and pitch for the pins. Place and route tools such as Mentor Graphics’ Olympus-SoC provide a Port
Properties editor, which displays I/Os graphically and allows the architect to align and assign sides, layers, and pitches for
the I/O pins. (courtesy of Mentor Graphics)
The system architect must be able to easily add and edit I/O constraints to configure the sides and order
of the pads as well as and the layer and pitch for the pins. Place and route tools such as Mentor
Graphics’ Olympus-SoC provide a port properties editor, which displays I/Os graphically and allows
the architect to align and assign sides, layers, and pitches for the I/O pins (Fig. 3). Olympus-SoC can
also infer, or derive, constraints based on an existing I/O pad (and partition pin) placement, providing a
useful starting place for further constraint editing.
Summary
Each new logic CMOS process generation will deliver twice the number of transistors as the previous
generation. The task for marketing and engineering will be to produce SoCs that provide entirely new
functionality to address a new market, integrate existing functions to grab a larger share of an existing
market, or slash die cost in hope of capturing low-end market share whether due to competitor
displacement or low price attracting new customers.
In developing this next-generation chip, the system architect must decide what IP blocks to add that
enhance the user experience while maintaining a strict cost and power budgets: compute engines,
accelerators, the latest generation peripherals, and/or more memory.
References
1. “Report of Final Project,” UC San Diego Design of SPARC CPU SoC
2. “Automatic Placement for Custom Layout in Virtuoso Layout Suite GXL”
3. “Design Planning Strategies to Improve Physical Design Flows—Floorplanning and Power
Planning”
4. “Experience implementing a complex SoC, leveraging a reusable low power specification”
5. “Concurrent Hierarchical Design with IC Compiler Real Life Application on Mobile Multi-
Media Processor”
6. “Real Design Challenges of Low Power Physical Design Implementation”