MicroBlaze Overview

Theresa Chou

© Memec (MG 000-00) 04.01.04

Agenda

MB OverView
MB Bus & IP
SW Flow
MB OS & 3’th party tool

© Memec (MG 001-04) 02.27.04

MB architecture
Embedded soft RISC Processor
32-bit data
32-bit instruction word (three addresses and two addressing modes)
32 registers (32-bit wide)
3 pipe stages (single issue)
Big-endian format
Buses
Full Harvard-architecture
OPB (CoreConnect), instruction and data
LMB for connecting to local BRAM (faster), instruction and data

MicroBlaze is a soft processor core

that can be implemented into any Virtex architecture:

© Memec (MG 001-04) 02.27.04

 MB architecture

ADD/SUB

PROGRAM
SHIFT/LOGICAL
COUNTER
MULTIPLY

BUS BUS
IF IF
INSTRUCTION
DECODE

REGISTER FILE
INSTRUCTION 32b X 32b
BUFFER

MICROBLAZE CORE

See more in http://www.xilinx.com/ipcenter/processor_central/microblaze/architecture.htm

© Memec (MG 001-04) 02.27.04
 MB performance

All instruction takes one clock cycle except

Load and store (two clock cycles)
Multiply (two clock cycles)
Branches (three clock cycles, can be one clock cycle)

See more in http://www.xilinx.com/ipcenter/processor_central/microblaze/performance.htm

© Memec (MG 001-04) 02.27.04
MicroBlaze Memory Space

Memory and peripherals

0xFFFF_FFFF
The MicroBlaze processor uses Peripherals
32-bit addresses
Special addresses
MicroBlaze processors must have
user-writable memory from
0x00000000 through 0x00000017 OPB Memory
BRAM size limits
The amount of BRAM memory
that can be assigned is limited
LMB Memory
The largest supported BRAM 0x0000_0018
memory size for Virtex and Interrupt Address
0x0000_0010
Virtex-E is 16 kilobytes; for Virtex-II, 0x0000_0008 Exception Address
it is 64 kilobytes 0x0000_0000 Reset Address

© Memec (MG 001-04) 02.27.04

 IBM CoreConnect Bus

The IBM CoreConnect standard provides three buses for

interconnecting cores, library macros, and custom logic:
Processor Local Bus (PLB)
On-chip Peripheral Bus (OPB)
Device Control Register (DCR) bus

Arbiter Master Arbiter

Master/
Master Slave

Slave Slave Slave

See more in http://www-3.ibm.com/chips/products/coreconnect/

© Memec (MG 001-04) 02.27.04
IBM CoreConnect Busses

© Memec (MG 001-04) 02.27.04

MicroBlaze – Busses

Local Memory Bus (LMB)

32-bit high speed memory access
Single-cycle to on-chip BRAM
ILMB (Instruction LMB)
DLMB (Data LMB)

On-Chip Peripheral Bus (OPB)

32-bit processor interface
8/16/32-bit peripheral interface
IOPB (Instruction OPB)
DOPB (Data OPB)

© Memec (MG 001-04) 02.27.04

MicroBlaze Bus Example

IOPB Bus IIC

ILMB Bus
UART
MicroBlaze
ILMB IOPB Ext Mem GPIO
BRAM
Ethernet
DLMB DOPB

LCD
DLMB Bus DOPB Bus
BRAM
All buses are 32 bits
INTC

OPB
ARB

© Memec (MG 001-04) 02.27.04

Example MicroBlaze System

DLMB DOPB UART RS-232

JTAG JTAG
UART Header
OPB
Interface GPIO DIP
Input Switches

MicroBlaze GPIO 7-Segment

Processor Output LED

Data
50MHz
Memory
Clock
Dual Port
Memory Reset
Controller Memory
Switch
(8K Bytes)

Instruction
Memory

ILMB FPGA External

© Memec (MG 001-04) 02.27.04

Free Cores

OPB Arbiter PPC System Reset

OPB TimeBase/WDT DCR Interrupt Controller
OPB Timer/Counter DCR Interface
OPB GPIO PLB Arbiter
OPB UART-Lite PLB EMC Memory Controller
OPB JTAG UART PLB BRAM Controller
OPB EMC Memory Controller PLB DDR Controller
Flash PLB SDRAM Controller
SRAM
ZBT
System ACE PLB2OPB Bridge
OPB BRAM Controller OPB2PLB Bridge Bus-to-Bus
OPB DDR Controller OPB2OPB Bridge communication
OPB SDRAM Controller OPB2OPB Bridge-Lite

© Memec (MG 001-04) 02.27.04

Custom IP - dkgpio
dkgpio
OPB Bus

opb_ipif_ssp0 dk_logic

IPIC
OPB IPIF Interface Interface LED[0:3]

IPIC is a simplified IPIF interface

© Memec (MG 001-04) 02.27.04

Hardware / Software Flow
Hardware Flow Software Flow

HW Block SW Flow
Diagram Chart

HW EDK Create SW
Description source

Synthesize
Compile
P&R Simulate
ISE

BIT File/ DATA2BRAM ELF File/

Download Download

Design Debug (HW and SW)

© Memec (MG 001-04) 02.27.04

Xilinx EDK

Embedded Development Kit

Xilinx Platform Studio (XPS) – GUI interface
Supports MicroBlaze and PPC development
Tools for HW and SW platform specification
Xilinx Microprocessor Debug (XMD)
Board Support Package (BSP) generator
Interface to industry standard simulation tools
MicroBlaze Core & License
Peripheral IP (Parameterizable)
GNU Tools (Compiler, Debugger)
Application Examples

© Memec (MG 001-04) 02.27.04

Hardware Flow

Specify Processor,
Bus & Peripherals,
Hardware Configuration

Automatic Hardware
Platform Generation

Xilinx Implementation
Flow

Bitstream PLB
EMC
OPB
JTAG GPIO
CNTL

PLB2OPB
PLB / Bridge OPB /
PPC405
Arbiter OPB2PLB Arbiter
Bridge

Download to FPGA PLB

BRAM
I/F
BRAM
Block
OPB
UART

© Memec (MG 001-04) 02.27.04

Hardware Flow – MHS
Microprocessor Hardware MHS Specify Processor,
Specification File (MHS) Bus & Peripherals,
Hardware Configuration

A text file that describes the hardware

structure Automatic Hardware
Processor Platform Generation
Bus architecture
Peripherals Xilinx Implementation
Connectivity of the system Flow
Interrupt request priorities
Address space Bitstream

Download to FPGA

© Memec (MG 001-04) 02.27.04

 Hardware Flow – MHS
Auto-Generated MHS File

# Parameters BEGIN microblaze

PARAMETER VERSION = 2.0.0 PARAMETER INSTANCE = mblaze
PARAMETER HW_VER = 2.00.a
MicroBlaze port
# Global Ports IO Port Delcarations PORT CLK = sys_clk connections, bus
PORT sys_clk = sys_clk, DIR = IN BUS_INTERFACE DLMB = d_lmb organization and
PORT sys_rst = sys_rst, DIR = IN BUS_INTERFACE ILMB = i_lmb
PORT rx = rx, DIR = IN BUS_INTERFACE DOPB = myopb
parameters
PORT tx = tx, DIR = OUT END

# Sub Components BEGIN lmb_v10

BEGIN bram_block PARAMETER INSTANCE = d_lmb
PARAMETER INSTANCE = bram_lmb PARAMETER HW_VER = 1.00.a
PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0
BUS_INTERFACE PORTA = ilmb_porta PORT LMB_Clk = sys_clk
BUS_INTERFACE PORTB = dlmb_portb PORT SYS_Rst = sys_rst
END END

BEGIN lmb_bram_if_cntlr Peripherals (memory, BEGIN lmb_v10

PARAMETER INSTANCE = my_ilmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x0000_0000
PARAMETER C_HIGHADDR = 0x0000_1FFF
BUS_INTERFACE SLMB = i_lmb
BUS_INTERFACE BRAM_PORT = ilmb_porta
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = my_dlmb_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x0000_0000
PARAMETER C_HIGHADDR = 0x0000_1FFF
BUS_INTERFACE SLMB = d_lmb
BUS_INTERFACE BRAM_PORT = dlmb_portb
END
etc…) PARAMETER INSTANCE = i_lmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
LMB/OPB Bus
END Specifications
BEGIN opb_v20
PARAMETER INSTANCE = myopb
PARAMETER HW_VER = 1.10.b
PARAMETER C_EXT_RESET_HIGH = 0
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END

© Memec (MG 001-04) 02.27.04

Hardware Flow – MPD
Microprocessor Peripheral Specify Processor,
MHS
Definition (MPD) Bus & Peripherals,
• Template that specifies ports MPD Hardware Configuration
and parameters of
peripherals and IP
Lists ports and default Automatic Hardware
connectivity for bus Platform Generation
interfaces
Lists parameters and default
Xilinx Implementation
values Flow
Any MPD parameter is
overwritten by the equivalent
Bitstream
MHS assignment

Download to FPGA

© Memec (MG 001-04) 02.27.04

 Hardware Flow – MPD Format
BEGIN opb_uartlite, IPTYPE=PERIPHERAL, EDIF=TRUE, HDL=BOTH Peripheral name, type and
OPTION SIM_MODELS = BEHAVIORAL : STRUCTURAL HDL source code type
BUS_INTERFACE BUS=SOPB, BUS_STD=OPB, BUS_TYPE=SLAVE

# Generics for vhdl or parameters for verilog Bus interface information

PARAMETER C_BASEADDR = 0xFFFF8000, DT=std_logic_vector
PARAMETER C_HIGHADDR = 0xFFFF80FF, DT=std_logic_vector
PARAMETER C_OPB_DWIDTH = 32, DT=integer
PARAMETER C_OPB_AWIDTH = 32, DT=integer Parameters/Generics that can
PARAMETER C_DATA_BITS = 8, DT="integer range 5 to 8"
PARAMETER C_CLK_FREQ = 125_000_000, DT=integer
be customized by user.
PARAMETER C_BAUDRATE = 9600, DT=integer Includes default values and
PARAMETER C_USE_PARITY = 1, DT=integer variable type.
PARAMETER C_ODD_PARITY = 1, DT=integer

# Global ports
PORT OPB_Clk = "", DIR=IN, BUS=SOPB, SIGIS=CLK
PORT OPB_Rst = OPB_Rst, DIR=IN, BUS=SOPB
PORT Interrupt = "", DIR=OUT, EDGE=RISING, SIGIS=INTERRUPT
# OPB slave signals
PORT OPB_ABus
PORT OPB_BE
=
=
OPB_ABus,
OPB_BE,
DIR=IN,
DIR=IN,
BUS=SOPB,
BUS=SOPB,
VEC=[0:C_OPB_AWIDTH-1]
VEC=[0:C_OPB_DWIDTH/8-1]
OPB Port Declarations.
PORT OPB_RNW = OPB_RNW, DIR=IN, BUS=SOPB These get automatically
PORT OPB_select = OPB_select, DIR=IN, BUS=SOPB connected since they are
PORT OPB_seqAddr =
PORT OPB_DBus =
OPB_seqAddr,
OPB_DBus,
DIR=IN,
DIR=IN,
BUS=SOPB
BUS=SOPB, VEC=[0:C_OPB_DWIDTH-1]
specified to be part of the OPB
PORT UART_DBus = Sl_DBus, DIR=OUT, BUS=SOPB, VEC=[0:C_OPB_DWIDTH-1] Slave Bus Interface
PORT UART_errAck = Sl_errAck, DIR=OUT, BUS=SOPB
PORT UART_retry = Sl_retry, DIR=OUT, BUS=SOPB
PORT UART_toutSup = Sl_toutSup, DIR=OUT, BUS=SOPB
PORT UART_xferAck = Sl_xferAck, DIR=OUT, BUS=SOPB
# uart signals
PORT RX = "", DIR=IN User Ports.
PORT TX = "", DIR=OUT

END

© Memec (MG 001-04) 02.27.04

 Hardware Flow – Platform Generator
Platform Generator (PlatGen)
MHS Specify Processor,
Uses MHS and MPD files to Bus & Peripherals,
create the hardware platform MPD Hardware Configuration
Creates netlist files
Creates support files for
downstream tools Automatic Hardware
Platform Generation
Creates HDL wrappers

Xilinx Implementation
Flow

Bitstream

Download to FPGA

© Memec (MG 001-04) 02.27.04

Hardware Flow – Implementation
Implementation Flow Specify Processor,
MHS
XFLOW Bus & Peripherals,
MPD Hardware Configuration
• Batch Mode Place & Route
flow.
ProjNav
Automatic Hardware
• ISE Project Navigator Platform Generation
GUI Place & Route flow

Xilinx Implementation
Flow
Xflow /
ProjNav
Bitstream

Download to FPGA

© Memec (MG 001-04) 02.27.04

 Software Flow
After peripheral hardware definition, the
software flow is independent of the
Specify Software
Architecture hardware flow.

Automatic Software
BSP/Library Generation

Software Compilation

Executable Hardware Flow

Executable
in on-chip
memory
Executable
in off-chip
? Data2BRAM Bitstream
memory PLB OPB
GDB / JTAG
CNTL
EMC
PLB2OPB
GPIO

Download to FPGA PPC405

PLB / BridgeOPB /
OPB2PLB
Arbiter Arbiter Download to FPGA
XMD PLB
BRAM
Bridge
BRAM OPB
Block UART
I/F

© Memec (MG 001-04) 02.27.04

 Software Flow – MSS
Specify Software
Architecture
Automatic Software
BSP/Library Generation
ƒ Microprocessor Software
Specification (MSS)
• Auto-generated/user
MSS modifiable file
• Contains all project
software options (C-
compiler options, driver
info, etc.)

Software Compilation

Executable Hardware Flow

Executable
in on-chip
memory
Executable
in off-chip
? Data2BRAM Bitstream
memory PLB OPB
GDB / JTAG
CNTL
EMC
PLB2OPB
GPIO

Download to FPGA PPC405

PLB / BridgeOPB /
OPB2PLB
Arbiter Arbiter Download to FPGA
XMD PLB
BRAM
Bridge
BRAM OPB
Block UART
I/F

© Memec (MG 001-04) 02.27.04

 Software Flow – MSS Format
ƒ Auto-Generated MSS File
PARAMETER VERSION = 2.0.0
PARAMETER HW_SPEC_FILE = system.mhs
BEGIN PROCESSOR
PARAMETER HW_INSTANCE = my_microblaze
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.00.a
PARAMETER EXECUTABLE = executable.elf
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
PARAMETER DEBUG_PERIPHERAL = my_jtaguart
PARAMETER STDIN = my_uartlite
PARAMETER STDOUT = my_uartlite
END
BEGIN DRIVER
PARAMETER HW_INSTANCE = myethernet
PARAMETER DRIVER_NAME = emac
PARAMETER DRIVER_VER = 1.00.b
PARAMETER LEVEL = 0
PARAMETER LIBRARY = XilNet
END
BEGIN DRIVER
PARAMETER HW_INSTANCE = my_uartlite
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.00.b
PARAMETER LEVEL = 0
END
© Memec (MG 001-04) 02.27.04
Software Flow – Library Generator

Specify Software
Library Generator (LibGen)
Configures libraries and device
Architecture MSS

drivers
• Creates xparameters.h include
Automatic Software file for driver definitions
BSP/Library Generation
• Creates libc.a, libm.a, libxil.a
libraries that contain functions
Software Compilation
that the processor can access

Executable

© Memec (MG 001-04) 02.27.04

 Software Flow – Compiler
XPS Supports
GNU Compiler for
MicroBlaze

Specify Software
Architecture MSS

Automatic Software
BSP/Library Generation

Software Compilation .c

Executable

© Memec (MG 001-04) 02.27.04

 Easy to Use Flow

Ž Design your Cpu and Cpu Bus by Graphic

Ž Set each component attribute , port , memory mapping

Ž Finish your CPU design

Ž Use tool bar to run your HW and SW flow

© Memec (MG 001-04) 02.27.04

Starting a New Project

Step through the XPS Hardware Flow

Create a new project
Setup project options
Insert peripherals
Make connections
Create ports
Set parameters
Set STDIO

© Memec (MG 001-04) 02.27.04

 Starting a New Project

Open XPS by selecting Start>Programs>Xilinx Embedded Development

Kit>Xilinx Platform Studio
Select the location of the
Project File (.xmp)
If you have an existing MHS
file, Browse to Import
Select the Target Device
Peripheral Repository Directory
Allows you to select the
location of your peripherals
if they are not local to your
project area.

© Memec (MG 001-04) 02.27.04

Project Options – Device and
Repository

From the XPS Menu

Options>Project Options

Target Device
Allows you to retarget the
design to another device

Peripheral Repository
Directory
Allows you to specify the
location of your
peripherals

© Memec (MG 001-04) 02.27.04

Project Options – Hierarchy and
Flow

Design Hierarchy
Allows you to place the
design as a sub-module
within another design
Netlist Generation
Targets the synthesis tool
and allows for flat netlist
creation
Implementation Tool Flow
Targets Xflow or ISE Project
Navigator

© Memec (MG 001-04) 02.27.04

Project Options – HDL and
Simulation
HDL
Selects the language of the
peripheral wrappers
Simulator
Selects between ModelSim or
Verilog-XL
ModelSim Libraries Path
Browse to the directories
where you have compiled the
Xilinx Models
Simulation Models
Select the models desired for
simulation
Refer to “Getting Started
Guide” for library compile info

© Memec (MG 001-04) 02.27.04

Processor Block Diagram
ƒ Processor
Block
Diagram (PBD)
• Auto-generated/user
modifiable file
• Block diagram format of
MHS file
• Good as reference, but
keep closed to avoid
MHS conflicts

© Memec (MG 001-04) 02.27.04

Define Hardware Platform

All hardware information is

stored in the MHS file and
can be edited in multiple
ways using XPS

Select Project>Add/Edit
Cores…(dialog)

This dialog allows you to add

Peripherals, Bus
Connections, Ports,
Parameters, etc.

© Memec (MG 001-04) 02.27.04

Hardware Implementation

Generate Netlist

Hardware Directories

Generate Bitstream

© Memec (MG 001-04) 02.27.04

Software Implementation

Generate Libraries
MicroBlaze BSP
MHS MSS

Library Structure
Library LibGen Libraries
MDD
MDD
MDD
Driver
Xmdstub.elf *.h *.a

Drivers for IP

© Memec (MG 001-04) 02.27.04

Downloading Bitstreams

Downloading Bitstreams
Tools>Download
Runs iMPACT in batch
mode
Uses download.cmd batch
file from the etc directory
to properly describe
JTAG chain
User must create
download.cmd for their
system

© Memec (MG 001-04) 02.27.04

DEMO Flow

© Memec (MG 001-04) 02.27.04