CpE 351 / 353 Drill Chapter #1

What are the major components of computer systems

Describe briefly the two computing models. Which one is better? Why?

What are the primary and secondary design quality metrics.

Discuss the impact of increasing the data bus size, address bus size, clock frequency, number of pins
on the chip, number of transistors on the chip, the current supplied to the chip, the transistor power
consumption and the number of cores

Consider modern laptop, desktop and workstation class processors and give typical numbers for: Data
& Address bus size, Number of transistors, Process (Fab or Node), Number of cores, Number of
memory channels, Number of power lines, Number of contacts (pins), Number of instructions, Clock
frequency, Voltage, Chip & Core, Power consumption, Cache, L1, L2 & L3, Number of registers,
Operating temperature, MIPS & GFLOPS performance, price, etc.

A source code in Python of around 10 KLine, estimate the object code size when compiled for Apple
M1 & AMD Ryzen processors. Estimate the numbers of another two similar processors

Compare the power efficiency, number of instructions per joule, of the two CPUs; A: 1 W / 16 MHz /
5 CPI & B: 10 W / 1 GHz / 3 CPI. Which is better and by how much?

Which is more power efficient, Processor A: 120 MHz / 10 W or its clone B: 450 MHz / 25 W,
assuming similar CPI performance

Estimate the impact of doubling the clock frequency, doubling the number of cores and both on the
performance if the work load is compute-bound and highly parallel.

Compute the number of contacts a 120 W / 1.5 V CPU has if the wire Ampacity is 0.33 A

Estimate the monthly electric power bill of your desktop assign it is on 8 hours power day

Estimate the annual electric power bill of a data center with 20 racks, each rack is 24 KW and needs
equal amount for networking and cooling. Get the tariff of the national electric power grid for your
estimation

An 8 GB SDRAM, 512 GB SSD, 3.2 GHz notebook computer with 3-cell Lithium-Ion battery, 20
KWH & 3.8 V per cell. Estimate the power rating of the processor if a drain test gets it depleted in 4
hours

Today’s commercial desktop computers are $500 and offer 50 GFLOPS of performance. Estimate the
performance of such a class of computers faster 4 years

Give examples of applications that will never make use of higher core counts, and others that do
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Today, 7nm process is in use by many fabs, with nearly 10 billion transistors per square centimeter?.
What is the expected density after 5 years? after 10 years from now?

A processor with 4 classes of instructions; class A takes 3 cycles, B takes 4 cycles, C takes 6 cycles
and D takes 8 cycles. In a typical mix we found these instruction counts: class A has 500, B has 200
instructions, C has 800 instructions and D has 100 instructions. Compute the CPI, IPC and MIPS at
100 MHz

Doubling the clock frequency does not double the performance, and doubling the number of cores in a
processor or the number of processors in a system does not double the performance either. Why? An
input/output-intensive code runs to completion in a minute. How long will it take if we quadruple the
clock?

A program runs to completion in 10 minutes on a system with 3 GHz dual core processor. How long it
takes to complete if we replaced the processor by a quad core of the same model and clock it at 4
GHz?

A processor design is implemented with three performance levels for notebooks, desktop and
workstation; the dual core has 1.2 billion transistors, the quad core has 1.8 Billion transistors and the
Octa core has 2.6 billions. Explain why the transistor count is not in proportion with the number of
cores

How long does it take a specific class of processors to upgrade performance by one order of
magnitude?

Apple’s M1 SoC integrates 16 Billion transistors on 1cm x 1cm die, What is the area that one needs to
build the same chip using discrete transistors, resistors, wires, etc.. How much it takes to do that?
space, money, time, etc.? Is the Engineering campus & Medical campus enough?

We can pack 10 Billions of transistors on a small chip & 10 such chips will give 100 Billions
transistors, matching the number of neurons in a human brain, and yet this is way far from reaching its
mental power. Why?

Why vendors can integrate 1000s of GPU cores on a chip but only 10s of CPU cores

In your very own words and using numbers, explain what "memory wall" means

How many low performance 8-bit microcontroller units you can buy with your monthly pocket
money?

Compare the price of discrete transistors with integrated transistors (in a modern processor chip for
example)?

A symmetrical clock signal of 1 GHz appeared non inverted at the output of an inverter. Explain
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Instructions Per Cycle (IPC) is an architectural performance metric. Today, microprocessors can
achieve IPC > 100 with less than10 cores, which means IPC > 10 per core. But the theoretical limit of
any pipeline is IPC=1 no matter how deep or efficient it is. How do you think the cores achieve those
numbers then?

A source code with 1853 lines generated 2658 instructions when compiled for a CISC machine. The
number of instructions if compiled for another CISC machine would be .... & the number of
instructions for a RISC would be?

Name three reasons why the number of contacts in a high core count µP chip to be in 1000’s

CISC µPs have instructions that can perform operations on two operands using absolute mode, while
RISC µPs do not, and have to load operands in register then write back the result. Does this mean
CISC are much faster in doing such operations? Explain

Typically, a CISC CPU can add two variable in memory in one instruction, how many does it a RISC
CPU to do that? Explain

Why does a single core µP running at 5 GHz take around 3 ns to compute the dot product of two 2-
element vectors of single precision floating point (SPFP) numbers, while it takes only 6 ns to compute
the dot product of two 16-element vectors? 8 times the computational effort done in twice the amount
of time

How much time does it take a commercial µP to multiply a pair of single precision floating point
numbers? 10 pairs one after another? 100 pairs one after another?
We want to design a controller for traffic lights on a busy intersection. What kind of specs such a
microprocessor will likely have regarding: data bus, address bus, number of cores, number of pins,
power consumption, clock frequency and cost.

Find the address space of a µP with 52-bit address bus, assuming it is a byte-index, and assuming it is
a longword-indexed (each longword, 32-bit word, has an index or address)

Transistor in processors are used as switches; when it is ON the voltage is quite low and hence the
power consumption is low, and when it is OFF the current is quite low and hence the power
consumption is low. Why power consumption goes higher by increasing the frequency?

How long does it take a specific class of processors to upgrade performance by one order of
magnitude?

If your desktop processor is a high end one then it might be rated at 100W, and knowing that
processors operate at 2V means it draws nearly 50A. How come then the circuit breaker of your home
does not break even if rated at 20A?

Why do we connect a 100 nF ceramic capacitor ?between the power and ground of every IC on the
motherboard?
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Today, the cost of GFLOPS performance is only 2 cents. Use Moore's law to predict the cost in the
mid 80's of the last century and then search to verify the answer

Instruction sets vary in size, RISC can go as low as 30 instructions although some are 200 and CISC
generally exceeds 200. The question is: what is the minimum? Can we design a computer with just 1
instruction? And hence no operation code and no decoding time and easy control logic. This is
something to investigate and not a Yes/No question.

Today, we can pack ten billions of transistors on a small chip, and 10 such chips will match the
number of neurons in a human brain, and yet this is way far from reaching its mental power. Why?

Despite the fact that we can fabricate transistors that can switch at 1 THz, building a system that runs
at 20 GHz is a challenge. Why?

An 58 WH battery in a laptop with 3.6 GHz / 4 W processor and 8 GB SDRAM may last for .... hours

The maximum power rating of desktop class 4.2 GHz microprocessor with 468 power contacts and
400 mA wire Ampacity is around ....

Compute the speed up of a 12 seconds task if the clock frequency is increased by 30%

What is the memory space size (in GB) of a byte indexed processor with 40-bit address pins and 64-
bits data pins

How long does it take a 20 GIPS µP class to get to the 100 GIPS performance level?

What happens if a 4 GHz processor is overclocked, run at 5 GHz let us say, for long time?

What is the problem of having a single memory channel in a processor with 8 cores? And what is the
solution?

Given that processor annual performance growth is 40% and memory performance growth is 8%,
Estimate the annual system performance growth assuming a workload with 67% of the time
computations, 27% of the time memory accesses.

We are to build 57 BTr Apple M1 Max SoC chip using discrete transistors. Assume that the transistor
and its passive components requires one square centimeter of space.
- Estimate the land area be be used assuming that all connection layers are on top
- Can this processor run at the M1 Max clock rate of 3.2 GHz? Explain

A workload running on a 2-core / 4 GHz processor takes too long to complete. We want reduce the
time by one third by either utilizing more cores or increasing the clock frequency. Discuss the two
scenarios, assuming 70% degree of parallelism & 75% of computations workload

What is the impact on the transistor density when we go from 5 nm node to 3 nm node
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We are to build Apple M1 Max processor using discrete transistors 5mm by 5mm on a land with
connections layers above it. Estimate the land area be be used

Compare the two major processor design styles in terms of instruction set size, number addressing
mode, instruction length, control logic real estate, compiler design, number of instructions in object
code
If you look into a microprocessor spec, you may find sources reporting various CPI values. How is
that?, since we are talking about the same processor

Define: CPU, GPU, DSP, NPU, GPGPU, APU, TPU, MMU, RISC, CISC