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LEARNING OBJECTIVES
CHARACTERISTICS OF MEM ORY SYSTEM (ii) Direct access: Individual blocks Or records have a
unique address based on physical location.
I. Location: The term refers to whether memory is internal or Example: Magnetic disks
external to the cornputer. The location of mermry may be
(iii) Random access: Each addressable location in
nxmory has a unique, physically wired-in addressing
• Internal (main)
mechanism. The time to access a given location is
• External (secondary)
independent of the sequence of prior accesses and is
2. Capacity: The capacity of internal memory is expressed in
terms of bytes.The capacity specified using Example: Main memory
• Word size
• Number of words (iv) Associative: This is a random accesstype of memory
that enables one to make a comparison Of desired bit
3. Unit of transfer locations within a word for a specified match.
• For internal memory. the unit Of transfer is equal to the
number of data lines into and out of the memory module 5. perfirmance: Three performance parameters arc:
The unit Of transfer need not equal a wvvd an address- (i) Access time (latency):
able unit. • For random memory. this is the time it takes to
• For external memory, data are onen transferred in mtxh perform a read or mite operation
larger units than a word, and these are referred to as • For non-random-access memory, access time is the
blocks. time it takes to positton the read-write mechanism at
the desired location.
4. Access method: The various methods of accessing units of
data arc (iii Memory cycle time: For a random access memory
it consists of the access time plus any additional time
(i) Sequential access: Memory is organized into units of
required a second access can commence.
data. called records.
(iii) Transfer rate: This is ratc at which data can be
Example: Magnetic tapes
transferred into or out of memory unit.
For Random accessmemory. Registers: The fastest. smallest and most expensive
type of memory consists Of the registers internal to
Transfer rate the
Cycle Time
Main memory: The principal internal memory
For non-randomaccessmemory, T& — system of the computer is main memory. Each
location in main memory hasa unique address.
Where,TV Averagetimeto reador writeN-bits.
T, = AverageacXesstime (iii) Cache: Main memory is usually extended With a
Number of bits higher speed.stnaller cache. The cache is not visible
R = Transfer rate in bits per second to the programmer or, indeed to the processor. It is
a device for staging the movement of data between
6. Physical type: The physical type Ofa "Emory Will
i. Semiconductor
main memory and pr€Xessor registers to improve
ii. Magnetic
These three forms of memory are volatile and
iii. Optical
employ semi conductor technology.
iV Magneto-optimal
7. Physical characteristics: The memory may be (ivi Magnetic tapes and disks: Data are stored more
• Volatile/non-volatile permanently on external mass storage devices, of
• Erasable/non-erasable Which the most common are hard disk and removable
Figure I
To summarize.
Address length (s + w) bits
Figure 2 (b) Nurntx•r of Addressable wordsor bytes
sin lim• sin 2" words or bytes
Elements of Cache Design Number ofbkx•ks in main memory = 2' Number
l. Cache size
of lines in cache M 2'.
2. Mapping function
• Direct Sree Of Tag (s —r) bits
Word
Compare
mapping bccomcs
Ot ( Hexa)
m—I.2m— 1.3m—
ou:m4. . FFm04
Note: NO two blocks that map into the same line numtx•r same line, regardlessWhat the StatusOfthe Othercache line
have the same tag number.
•lhis can produce a low hit ratio. even ifonly a very small
Advantages:
of the caclu• ISeffectively used
• Simple and cheap
• The tag field is short; only those bits have to stored Associative maning techmque overcomes the disad-
which are not used to address the cache. Vantage of direct mapping by permitting each main memory
• Access is very fast. bkx•k to bc loaded Into any line ofthc cache Here the cache
control log.c interprets a memory address as two fields.
Disadvantages: A given block fits into a fixed cache loca-
tion, i.e., a given cvacheline will be replaced whenever there 1. Tag
2. Word
is a reference to another memory block which fits to the
Figure shows asscxiative mapping technique:
Memory address
Tag Word
Tag
Tag
Compare
TO determine whether a block is in the cache, the cache con- Address length —(s + w) bits
trol logic must simultaneously examine every linc tag for a Number of addressable units = 2"" words or bytes
match. NO field in the addres corresponds to line number. Block size = line size = 2•words or bytes
so that the number of lines in the cache is not determined by
of blocks in main memory
the address format.
Number of lines in cache • undeterrnined
To sum m aria,
Size of tag s•bits
Tag
Tag
BbCk
Here the tag in a memory address is much smaller and (ii) FIFO (First-in-first-out): Replace the block in the set
is only compared to the K tags within a single set. TO that hasbeen in the cache longest.
summarize. (iii) (Least frequently used): Replace the block in
Address length (s + w) bits the set that hasexperienced the feuest references.
Number OfAddressable units words bytes (ivi Random
Block size line size 2' words bytes
Write policy
Number of blocks in main memory
When a block that is resident in the cache is to be replaced.
Number oflines in set K there are two cases to consider.
Number Of sets V
Number Of lines in cache = K V = K x 24 If the old blcw•k in the cache has not been altered then
it may be over-written With a new block Without first
writing out the old block _
(ii) If at least one write operation has been performed on
Example 3: Cache capacity 64 KB
a word in that line of the cache, then main memory
Block swe = 4 B
must updated by writing the line of cache out
Main memory capacity = 16 MB
of the block of memory before bringing in the new
x 60 See I min
2 RPMS
x 60 Sec/lmin
RPM (avg sectortirack)
Notes:
Diskette
Write
union • Portable. convenient to use
cyErO-' to Main Standards
• mch capacity 360 KW disk
• 31/,inch capxity 144 MB,'disk(about 700 pages
Of A. text)
Magnetic Tape
Magnetic talE is made up fmm a layer of plastic which is
coated with iron oxide. The oxide can be magnetized in
different directions to represent data, The operation uses a
similar principle as in the caseof a tape recorder.
Main features
o access (access time about I $5)
• [ligh value of storage(50 MBJtapc)
• InexFnsive
It is onen used for Batch up or archive purpose.
Optimal Memory WORM (Write Once Read Memory) CD: A lower beam
CD-ROM (Compact disk ROM): The disk surface is of modest intensity equipped in the disk drive is used to
imprinted With microscopic holes which record digital irnryint the hole pattern.
information. When a low-powered Ivan' shines on • Good for archival by providing a permanent
the surface. the intensity Of the reflected light changesas it record of large volumes of data.
encounters a hole, The change is detected by a photo
and converted into a digital signal. Erasable Optical Disk: Combination Of Laser technology
and magnetic surface technique.
• Huge capacity 775 MB/disk diskette)
• Can be reß•atedly written and overvvTitterv
• Inexpensive replication, cheap pnxltxtlon
• High reliability and longer life than magnetic disks.
• Removable. read only
• Long accesstime (could be halfa second)
EXE
main memory. Used With a 16-bit processorthat issues has a first-uxrd (4 bytes) accesstime Of SOns and an
24-bit address.Then the number Of bits used to repre- acx•ess time Of 5ns for each nord thereafter. What is the
sent set field is time when there is a cache miss?
(A) 2-bits (B) 10-bits (A) 130ns (B) 149.4 ns
(C) 12.bits (D) 14-bits 2.375 ns 8.875 ns
Practice Problems 2 3. A disk pack have 16 surfaces, with 128 tracks per sur-
face and 256 sectors per track. 512 of data are
Directions questions to 20: Selc•ctthe correct alterna-
stored in a bit serial manner in a sector. The number of
tive from the given choices.
bits required to specify a particular sector in the disk is
l. If average accesstime of CPU is 20 accesstime Of
main memory is 110 ns and the cache time is 10 11 (D) 19
us. What is the hit ratio?
4. A disk has 19456cylinders. 16headsand 63 sectors per
(A) 100%
track. The disk spins at rpm, Seek time between
adjacent tracks is 2 ins. Assuming the read/write head
2. A hard disk spins at 180 revolutions per minute. What is already at track O,how long does it take to
is the average rotational latency? read the entire disk?
(A) 0.16 sec (B) 032sec (A) 48 min (B) SS min
(D) 0.4 sec (C) 64 min (D) 72
5. A certain moving arm disk storage With one has (C) LOW consumption
following specifications: (D) All or these
Number of tracks'recording surface = The menuwy that hasthe shortest accesstime is
Disk Rotation Speed = 2400 rpm (A) Magrruc t*lbble (B) Magneuccue memory
Track storagecapacity = 62500-bits (C ) CA-he menuy-y (D) RAM
The averagelatency time (assuming that headcan 14. Cache memory
from one track to another only by traversing the entire (A) greater capacity than RAM.
track) is (B) enhances secondarystorage accesstime.
(A) 0.125 sec (B) 1.25 sec (C) is faster to access than reglsters.
(C) 0.0125 sec (D) 12.5sec (D) is fæstcrto accessthan main memory
6. In Memory managementsystem.cache memory access 15. Consider a disk pack with 16 surfaces 128 tracks per
time is 100 ns and main memory access time is 200 ns_ surface and 256 sectors per track. 512 bytes Of data are
Number of CPU references is 100 and number ofhits is stored in bit and serial manner, Then the capacity of the
IO. Average access time is
(A) 150ns (B) 100ns (A) 256 MB (B) 256 KB
(C) 190ns (D) 2S0ns $12 MB (D) 64 MB
7. The seek time of disk is 40 m sec. It rotates at the rate 16. Principle of locality justifies the use Of
of 40 rps. The capacity of each track is 4(Ki words. The (A) Cache (B) DMA
access time is Disk (D) RAM
(A) 50m sec (B) 53 m sec 17. The main memory ofa computer has 2ab blocks while
(C) 60 m sec (D) 63 m sec cache has 20 blocks. If the cache uses the set asso-
8. An Associated cache and one million -word rnain ciative 'napping scheme with blocks per sel. then
memory are divided into 256 word blocks. How many block k of main memory maps to the set:
blocks are there? (k (B) (k mod a) Of cache
(C) (k nu»d 2") of cache (D) (k mod 2ah) of cache
(D) 23 18. mlich Of the following factors do not affect the hit
9. The average access time of a disk is ration of cache?
(A) Seek time + Rotational latency time (A) Bkxk replacement algorithms.
(B) Seek time (B) Block frame size
(C) Rotational latency + transfer time + seek time (C) Cycle counts
(D) Rotation latency + transfer time. (D) Main memory size
10. What will bc the size of the memory whose last mem- 19. In which ofthe following mapping function, there is no
Ory location is FFFF? need of replacement algorithm?
(A) 64k (B) 32k (A) Direct Mapping
(C) 10k (D) 24 k (B) Set-asqxiative mapping
I I. Data from a casscttc tape is obtained by associative
(D) Both (A) and (B)
(A) Parallel (B) Serial 20. In a direct mapping, the index field equals to
(C) Sequential D) Random (A) Sum of tag and word fields
12. For a memory system, the desirable characteristics is' (B) Sum of block and word fields
(C) Sum of tag an block fields
(A) Speed and reliability (D) Same as block field
(B) Durability and comßEtness
Consider a small tuo-w•ay set-associative cache Common data ror questions 7, 8 and 9: Consider a ma-
memory, consisting Of four blocks. For che»sing chine with a 2•way set associative data cache of sin 64K-
block to replaced use the least recently used (LRU) bytes and block size I (Fbyles. The cache is managed using
scherne.The number of cachemisses ror tix following 32-bit virtual addressesand the page size is 4Kbytes. A
sequence Of block addresses is 8, 12. O. 12. S 120041 pnvram to be run on this machine begins as follows:
double ARR (10241 [10241 ;
int i, j;
2. Consider a direct mapped cache Of size 32 KB Initialize array ARR to 0.0
with block size 32 bytes. The CPU generates 32 for (i = i < 1024;
bit addresses. The number of bits needed for cache for (j O;j < 1024;H)
indexing and the number of tag bits are respectively ARR = 0.0:
120051
size of double is 8 Bytes. Array ARR is located in
(A) 10, 17 (B) 10,22
memory starting at the beginning of virtual page OXFFOOO
(C) 15, 17 (D) 5, 17
and stored in row major order. The cache is initially empty
Common data ror questions 3 and 4: Consider cache
and no prefetching is done. The only data memory refer-
organizatioms: The first one is 32 KB 2-way ences made by the program are those to array ARR.
With 32-byte block size. The second is of same size
but direct mapped. The size ofan address is 32 bits in 7. The total size Of the tags in the cache directory is
cases. A 2-to-l multiplexer has a latency of 0.6 ns "hile a 120081
k-bit comparator has a Eatencyof k' 10 ns. The hit latency of (A) 32K-bits (B) 34K-bits
the setassQR'ative
organizationis h, while that of the direct (C) 64K-bits (D) 68K -bits
mapped one is hr
S. Which of the following array elements has the same
3. The valueof hJis:
cache index as ARR [01 [OJ? 120081
(A) 2.4ns (B) 2.3 ns
(A) ARR101[41 (B) ARR (41 101
(D) 1_7ns
(D) ARR [5] [0]
4. The valueof h: is: 120061
9. -n.e cache hit ratio for this initialization loop is
Data for question 5: Consider a rnachine with a byte
120081
addressable main memory Of bytes. Assume that a
direct mapped data cache consisting of 32 lines of 64 bytes
each is used in the system. A 50 50 tuo-dimensional
array Of bytes is stored in the main memory starting from 10. Consider a 4-way set associative cache (initially
memory location 1100 H. Assume that the data cache empty) with total 16 cache blocks. The main mem-
is initially empty. The complete array is accessedtwice. Ory consists Of 256 blocks and the request for mem-
Assume that the contents of the data cache do not change Ory blcxks is in the following order: 120091
in between the two accesses.
u 2", 133, 159, 216, 32, 73,
5. Which of the following lines of the data cache will 92, 155.
replaced by new blocks in accessingthe array for the Which one of the following memory block will NOT
second time? 120071 be in cache if LRU replacement policy is used?
(A) line 4 to line II (B) line4 to line 12
(C) line 7 line O to line S
(C) 129 (D) 216
6. For inclusion to hold bct•.vecn two cache Icvcls L and
in a multi-level cache hierarchy, which of the fol- Common data questions I I and 12: A computer system
lowing arc necessary? 120081 has an LLcache, an L: cache,and a main memory unit
(i) l.. mustbe a write-throughcache connectedas shown below. The block size in L, cache is 4
words. The block size in cache is 16 words. The mem-
(iii l.: mustbe a write-throughcache
(iii) The associativity Of must greater than that Ory access times are 2 nanoseconds. 20 nanoseconds and
200 nanoseconds.for L. cache,L, cacheand main memo-
(iv) The L: cachemustbe atleastas largeas theL, ry unit reslx•ctively.
cache
(A) (ivy only (B) (i) and L, L?Cx:he
met-no ry
(C) (i), (ii) and (ivy only (D) (ii), (iii) and (iv)
and 40 memory operand write The cache • 27. A file system an in • memory cache to cache disk
hit ratio is 0.9. The average menuwy access time (in blocks. The miss rate ofthe cache is shown in the fig-
nanoseconds) in executing the sequence Of instnk•- ure. The latency to read a block from the cache is I
trons IS 120141 ms and to read a block fn•m the disk is I Oms. Assume
23. Assume that for a certain a read request that the cost of checking whether a block exists in the
takes 50 nanoseconds on a cache miss and 5 nano- cache is negligible. Available cache sizes are in multi-
seconds on a cache hit. Suppose while running a ples of I OMB-
program. it was observed that 80% of the processor's The smallest cache size required to ensure an average
read requests result in a cache hit. The average read read latency of less than 6 ms is 120161
access time in nanoseconds is 120151
24. A computer system implements a 40-bit virtual
90
address, page size of S kilobytes. and a 12S-cntry
translation look-aside buffer (TUB) organized into 32 80
sets each having four ways. Assume that the TLB tag
70
does not store any process id. The minimum length of
60
the TLB tag in bits is 120151
25. Consider a machine With a byte addressable main
memory of 2N bytes, blcRk size of 16 bytes and a 40
direct mapped cache having 2 1: cache lines. Let the 30
addresses of txvo consecutive by-tes in main memory
be and are the tag and 20
cache line address (in hex) for main address 10
(E201F)16? 120151
(A) E, 201 (B) F,201 o 10 20 3040 sooo 70 so 90
(C) E,E20
26. The Width Of the physical address on a machine is 40
bits. The width of the tag field in a 512KB S-way set
cache is 120161
ANSWER Keys
EXE ROSES
Practice Problems
10. A
11. B 12. c 13. D 14. B 15. A 17. B 18. A 19. B
Practice Problems 2
10. A
11. c 13. c 14. D 17. B 18. D 19. A
Time: 60 min.
Directions for questions to 30: Select the correct alterna- Which of the following statement is true?
rive from the given choices. (A) Floating point representation is better than fixed
point representation.
Which Of the following register keeps track of instrue
(B) Fixed point representation is better than floating
tion execution sequence?
point representation.
(A) Accumulator ( B) Program counter
(C) Datapath is same as ALU.
(C) Stack pointer (D) Instruction register
(D) Both (A) and (C)
2. Consider the following Register Transfer Language:
9. Which of the following statements correctly specifies
R, + MIR, + Rd about overflow"?
WhereRt, R: andR, arethe CPU registers •M• is a 0) When adding tuo unsigned numbers the carry
memory location in primary memory. which a&fressing out. from the MSB position serves as the overflow
mode is suitable for above register transfer language? indicator.
(A) Indirect (B) Direct (ii) Overflow can occur only by adding two signed
(C) Indexed (D) Displacernent numbers that have the same sign.
3. Which of the following Ware advantage(s) of using a (A) (i) only (B) (ii) only
multiple-bus architectureover a single-busarchitecture? (C) Both (i) and (ii) {D) Neither (i) nor (ii)
(i) Multiple-bus architecture reduces propagation
10. A certain prxessor supports only the immediate and
delay. direct addressing modes. Which of the following pro-
(ii) Multiple-bus architecture reduces bottleneck
gramming language features cannot be implemented
effects.
this prcxessor?
(A) (i) only (B) (iii only (A) Pointers (B) Arrays
(C) Both (i) and (ii) (D) Neither (i) nor (ii) (C ) Records All of these
4. Which of the following statement is false with The special m.rpose location(s) used by both
to Booth k Multiplication Algorithm? ALU and CU are
15. In Which addressing mode, the effective address Of the 23. HOWmany cycles are required to perform two-
operand is generated by adding a constant value to the ogx•randOFrations using one bus datapath?
content of a register.'
(A) Absolute mode (B) Indirect mode (D) Can't be determined
(C) Immediate mode (D) Index mode 24. Which of tlw following is a rounding mode in I EEE754
16. What is the number of instructions required to add •n'
numbers and store the result in metmry• using only (i) round to O
one-address instructions? (ii) round towards
(iii) round towards
(D) inderw•ndentOf n (ivi mum] to nearestrepresentablenumber
17. Which unit Of a computer system executes prcwram, (A) (ivi only (B) (ii). (iii) only
communicates with and often controls the operation of (C) only (D) (ii). (iii), (iv)
other subsystems? 25. What is the normaliæd form of 0.00000110 X 16101?
(A) CPU (B) ALU (B) 1.10x
(C) 1/0 module (D) DMA O_110x (D) 0.110 x
18. The multiplicand register and multiplier register of a 26. What is the representation of—7, using 4-bits for
hardware circuit implementing tMothS algorithm have the bias?
IOOI and 1100 respectively. The resultant will be (A) 0111
(A) 10011100 (B) 00011 100 (D) 1001
(C) 01101100 27. What is the total resultant after adding A = —7and B =
19. A floating point number has sign bit O, Excess-64 —6using signed complement representation?
exponent is 1010100 and fractional part is (A) 0100 (B) 11101
000000000001 1011_ After converting this to (C) 1101 (D) Overflow occurs
normalized form, the exponent (in decimal) Will be 28. What is the total number of additions and subtractions
(A) 20 required using BQK'thsmultiplication algorithm for the
(C) 31 multiplier II
20. In IEEE floating point single precision representation,
the number Of bits in the fractional 1Mrtis 30 (D) Can't be determined
(A) 24
Common data questions 29 and 30: Consider a 12-bit
(B) 23
floating point format in which base b 2, a 5-bit exponent
(C) 32
e with a bias = 16 and 6•hit normalized mantissa m. Given
(D) Depends on the architecture
two floating point numbers:
21. After multiplying the binary numbers and
10001 011011
1101 10 using multiplication algorithm, the
Will be
(A) -1242 (B) 1242 29. After adding and B, the resultant will bc
(C) 230 (D) -230
1 10001
22. The IEEE standard 754 single precision t%atiræ
0 10001 0«jooo
representation of (0.0000001 101 10100101 is.
(D) 0 10001 000001
(A) 0 11011010010100000000000
30. After subtracting B from A, the resultant will bc
(C) 0 101101001101000000000000 110101 (B) 0 10001 110101
1 10001 110110 (D) 0 10001 110110
ANSWERS KEYS
10. D
11. c 12. C 13. B 14. A 15. D 16. C 17. A 18. B 19. B 20.
21. D 22. D 23. B 24. D 25. B 26. C 27. D 28. B 29. C 30. D