Professional Documents
Culture Documents
■ 80MHz RISC MCU and 80MIPS Kalimba DSP CSR8610 1-mic Mono Headset
■ Internal ROM, serial flash memory and EEPROM
interfaces
■ Mono codec with 1 analogue input and 1 digital 1-mic CVC Audio Enhancement
microphone (MEMS) interface
■ Radio includes integrated balun
■ CSR's latest CVC technology for narrowband and Fully Qualified Single-chip
wideband voice connections including wind noise
reduction Bluetooth® v4.0 System
■ Wideband speech supported by HFP v1.6 profile
and mSBC codec Production Information
■ Voice recognition support for answering a call,
enables true hands-free use
CSR8610A04
■ Multipoint HFP connection to 2 phones for voice
■ Multipoint A2DP connection enables a headset
(A2DP) connection to 2 A2DP source devices for Issue 2
music playback
■ Secure simple pairing, CSR's proximity pairing
■ External crystal load capacitors not required for MCU Audio In / Out
typical crystals
Kalimba
■ 3 LED outputs DSP Debug SPI
Note:
CSR8610 BGA is a ROM-based device where the product code has the form CSR8610Axx. Axx is the specific
ROM-variant, A04 is the ROM-variant for CSR8610 1-mic Mono Headset.
Minimum order quantity is 2kpcs taped and reeled.
Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your
local sales account manager or representative.
Contacts
2
I C/SPI LED PWM
SPI Serial Flash UART USB v2.0
Master Control and Clock
(Debug) Interface 4Mbps Full-speed AUX ADC
/Slave Output Generation
3.3V
PIO Port
TX
DMA ports
Bluetooth Bluetooth Radio
BT_RF
Baseband and Balun
RX
MIC_AN
High-quality ADC
MIC_AP
Memory
Management
Unit
SPKR_AN
High-quality DAC
SPKR_AP
DMA ports
Audio
Interface VDD_AUDIO
VDD_AUDIO_DRV
ROM
Switch
PIO Port
VBAT
PM 0.85V to SENSE VBAT_SENSE
80MHz MCU PMU 1.35V 1.35V
Digital 1.2V 1.8V 1.35V
Interface Low-voltage Low-voltage
Microphone 2 Low-voltage Switch- Switch- Bypass Li-ion
DM1 80MHz DSP PCM1 / I S and VDD_ANA VDD_AUX
Input VDD_DIG mode mode LDO Charger CHG_EXT
BIST Linear Linear
VM Accelerator (MEMS) Linear Regulator Regulator
Engine Regulator Regulator
DM2 (MPU) Regulator VCHG
SENSE SENSE SENSE SENSE SENSE
Digital MIC
Digital Audio
VREGIN_DIG
VDD_DIG_MEM
VDD_ANA_RADIO
VDD_AUX_1V8
VDD_AUX
LXL_1V8
SMPS_1V8_SENSE
LX_1V35
SMPS_1V35_SENSE
3V3_USB
G-TW-0009561.1.1
Production Information Page 5 of 109
This material is subject to CSR's non-disclosure agreement CS-208517-DSP2
© Cambridge Silicon Radio Limited 2011-2012 www.csr.com
Document History
Revision Date Change Reason
List of Figures
Figure 1.1 Device Pinout .................................................................................................................................. 14
Figure 2.1 Simplified Circuit BT_RF ................................................................................................................. 23
Figure 3.1 Clock Architecture ........................................................................................................................... 25
Figure 5.1 Kalimba DSP Interface to Internal Functions .................................................................................. 28
Figure 6.1 Serial Flash Interface ...................................................................................................................... 29
Figure 7.1 Universal Asynchronous Receiver .................................................................................................. 31
Figure 7.2 Example I²C EEPROM Connection ................................................................................................. 33
Figure 8.1 LED Equivalent Circuit .................................................................................................................... 35
Figure 9.1 Audio Interface ................................................................................................................................ 36
Figure 9.2 Audio Codec Input and Output Stages ............................................................................................ 37
Figure 9.3 Audio Input Gain ............................................................................................................................. 38
Figure 9.4 Microphone Biasing ......................................................................................................................... 41
Figure 9.5 Differential Input .............................................................................................................................. 42
Figure 9.6 Single-ended Input .......................................................................................................................... 42
Figure 9.7 Speaker Output ............................................................................................................................... 43
Figure 9.8 Side Tone ........................................................................................................................................ 43
Figure 9.9 PCM Interface Master ..................................................................................................................... 46
Figure 9.10 PCM Interface Slave ....................................................................................................................... 46
Figure 9.11 Long Frame Sync (Shown with 8-bit Companded Sample) ............................................................ 47
Figure 9.12 Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 47
List of Tables
Table 7.1 PS Keys for UART/PIO Multiplexing ................................................................................................ 30
Table 7.2 Possible UART Settings ................................................................................................................... 31
Table 7.3 Standard Baud Rates ....................................................................................................................... 32
Table 8.1 Alternative PIO Functions ................................................................................................................. 34
Table 9.1 Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface ............................. 36
Table 9.2 ADC Audio Input Gain Rate ............................................................................................................. 39
Table 9.3 DAC Digital Gain Rate Selection ...................................................................................................... 40
Table 9.4 DAC Analogue Gain Rate Selection ................................................................................................. 40
Table 9.5 Side Tone Gain ................................................................................................................................ 44
Table 9.6 PCM Master Timing .......................................................................................................................... 50
Table 9.7 PCM Slave Timing ............................................................................................................................ 52
Table 9.8 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 54
Table 9.9 Digital Audio Interface Slave Timing ................................................................................................ 55
Table 9.10 I²S Slave Mode Timing ..................................................................................................................... 56
Table 9.11 Digital Audio Interface Master Timing .............................................................................................. 57
Table 9.12 I²S Master Mode Timing Parameters, WS and SCK as Outputs ...................................................... 57
Table 10.1 Recommended Configurations for Power Control and Regulation ................................................... 58
Table 10.2 Pin States on Reset .......................................................................................................................... 65
Table 11.1 Battery Charger Operating Modes Determined by Battery Voltage and Current ............................. 67
List of Equations
Equation 3.1 Crystal Calibration Using PSKEY_ANA_FTRIM_OFFSET .............................................................. 26
Equation 3.2 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2402.0168MHz .......................................... 26
Equation 3.3 Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz .......................................... 26
Equation 7.1 Baud Rate ....................................................................................................................................... 31
Equation 8.1 LED Current .................................................................................................................................... 35
Equation 8.2 LED PAD Voltage ............................................................................................................................ 35
Equation 9.1 IIR Filter Transfer Function, H(z) ..................................................................................................... 45
Equation 9.2 IIR Filter Plus DC Blocking Transfer Function, HDC(z) .................................................................... 45
Equation 9.3 PCM_CLK Frequency Generated Using the Internal 48MHz Clock ................................................ 54
Equation 9.4 PCM_SYNC Frequency Relative to PCM_CLK ............................................................................... 54
1 2 3 4 5 6 7 8 9 10
A A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
B B1 B2 B3 B4 B5 B6 B7 B8 B9 B10
C C1 C2 C9 C10
E E1 E2 E5 E6 E9 E10
F F1 F2 F5 F6 F9 F10
G G1 G2 G9 G10
H H1 H2 H9 H10
J J1 J2 J3 J4 J5 J6 J7 J8 J9 J10
G-TW-0007438.1.1
K K1 K2 K3 K4 K5 K6 K7 K8 K9 K10
Note:
SPI and PCM1 interfaces are mapped as alternative functions on the PIO port.
LED driver.
Alternative function: programmable
LED driver.
Alternative function: programmable
output PIO[30].
LED[1] K1 Bidirectional VDD_PADS_1 Note:
As output is open-drain, an external
pull-up is required when PIO[30] is
configured as a programmable
output.
LED driver.
Alternative function: programmable
output PIO[29].
LED[0] J2 Bidirectional VDD_PADS_1 Note:
As output is open-drain, an external
pull-up is required when PIO[29] is
configured as a programmable
output.
Charger input.
VCHG K5
Typically connected to VBUS (USB supply) as Section 12 shows.
Auxiliary supply.
VDD_AUX B2
Connect to 1.35V supply, see Section 12 for connections.
K A2 - 0.21 - G - 0.08 -
J
H A3 - 0.45 - H - 0.15 -
G
E
F
a - 0.05 - J - 0.08 -
E
D
b 0.27 0.32 0.37 n - 68 -
C
B
A
D 5.45 5.5 5.55 SD - 0.25 -
3
a C
2X A1 Corner F C D1 - 4.5 - SE - 0.25 -
Index Area C
G C Seating
Bottom View Plane E 5.45 5.5 5.55 Ball diam. - 0.3 -
2
10 9 8 7 6 5 4 3 2 1
Solder land
A E1 - 4.5 - - 0.275 -
opening
B
C
SE
D
Notes 1. Dimension b is measured at the maximum solder ball diameter,
E
parallel to datum plane C.
E1
F 2. Datum C (seating plane) is defined by the spherical crowns of
G
the solder ball.
e
H 3. Parallelism measurement shall exclude any effect of mark on
J
top surface of package.
K
Description 68-ball Very Thin, Fine Pitch Ball Grid Array (VFBGA) Package
G-TW-0007437.7.2
SD
e nX Øb 1 Size 5.5 x 5.5 x 1mm JEDEC MO-225
D1 ØH M C A B
ØJ M C
Pitch 0.5mm Units mm
VDD
_ On-chip Balun
PA BT_RF
+
VSS_BT_RF
2.2 RF Receiver
The receiver features a near-zero IF architecture that enables the channel filters to be integrated onto the die.
Sufficient out-of-band blocking specification at the LNA input enables the receiver to operate in close proximity to
GSM and W‑CDMA cellular phone transmitters without being desensitised. A digital FSK discriminator means that
no discriminator tank is needed and its excellent performance in the presence of noise enables CSR8610 BGA to
exceed the Bluetooth requirements for co‑channel and adjacent channel rejection.
For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed
to the EDR modem.
2.5 Baseband
2.5.1 Burst Mode Controller
Bluetooth
Reference Clock
Radio
G-TW-0000189.3.3
Auxiliary Digital
PLL Circuitry
2401.9832
PSKEY_ANA_FTRIM_OFFSET = ( − 1) × 220 ≈ −7
2402
Equation 3.3: Example of PSKEY_ANA_FTRIM_OFFSET Value for 2401.9832MHz
4.1 VM Accelerator
CSR8610 BGA contains a VM accelerator alongside the MCU. This hardware accelerator improves the performance
of VM applications.
Registers
Instruction Decode ALU
DSP, MCU and Memory Window Control
Program Flow DEBUG
Flash Window
DM2 DSP Data Memory 2 Interface (DM2)
G-TW-0005522.2.2
PM DSP Program Memory Interface (PM)
1.8V
Serial Quad I/O Flash
MCU Program VDD
MCU RESET#/HOLD#/IO3
WP#/IO2
MCU Data QSPI_FLASH_CLK
CLK
Memory
Serial Flash
QSPI_FLASH_CS#
Interface
Management CS#
Unit QSPI_IO[0]
DI/IO0
Kalimba DSP Program QSPI_IO[1]
G-TW-0008502.1.2
DO/IO1
Kalimba DSP
G-TW-0008555.2.2
PIO[9] or PIO[17] UART_CTS
To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated
serial port adapter card.
Table 7.2 shows the possible UART settings.
1.8V C1
R1 R2 R3 10nF
2.2kΩ 2.2kΩ 2.2kΩ U1
8 1
VCC A0
PIO[12]/QSPI_FLASH_CS#/I2C_WP 7 2
WP A1
G-TW-0008557.1.1
PIO[10]/QSPI_FLASH_CLK/I2C_SCL 6 3
SCL A2
PIO[11]/QSPI_IO[0]/I2C_SDA 5 4
SDA VSS
24AAxxx
The I²C EEPROM requires external pull-up resistors, see Figure 7.2.
CSR recommends 400kHz capable I²C EEPROMs.
Function
PIO
Debug SPI SPI Flash UART PCM EEPROM
(See Section 7.3) (See Section 6.5) (See Section 7.2) (See Section 9.3) (See Section 7.4)
PIO[13] - QSPI_IO[1] - - -
PIO[14] - - UART_RX - -
PIO[15] - - UART_TX - -
PIO[16] - - UART_RTS - -
PIO[17] - - UART_CTS - -
See the relevant software release note for the implementation of these PIO lines, as they are firmware build-
specific.
LED Supply
VDD = VF + VR + VPAD
The supply domain in Section 1.2 for LED[2:0] must remain powered for LED functions to operate.
The LED current adds to the overall current. Conservative LED selection extends battery life.
Digital
MMU Voice Port Voice Port Audio
Memory
G-TW-0009556.1.1
Differential
Audio DAC Output
Codec
Driver Differential
Register Interface Registers
ADC Input
The term PCM in Section 9.3 and its subsections refers to the PCM1 interface.
PCM_OUT SD_OUT
PCM_IN SD_IN
PCM_SYNC WS
PCM_CLK SCK
Table 9.1: Alternative Functions of the Digital Audio Bus Interface on the PCM1 Interface
CSR8610 BGA is designed for a differential audio output. If a single-ended audio output is required, use an
external differential to single-ended converter.
PIO[EVEN] Clock
Digital MIC Interface Digital Mic Digital Codec 16 Input B
PIO[ODD] Data
MIC_AP
High-quality ADC Digital Codec 16 Input A
MIC_AN
G-TW-0009557.2.2
SPKR_AN
High-quality DAC 16
SPKR_AP
Low-pass Filter
G-TW-0005535.4.3
System Gain = ADC Pre-amplifier + ADC Analogue Gain + ADC Digital Gain
CSR8610 BGA has an analogue gain stage based on an ADC pre-amplifier and ADC analogue amplifier:
■ The ADC pre-amplifier has 4 gain settings: 0dB, 9dB, 21dB and 30dB
■ The ADC analogue amplifier gain is -3dB to 12dB in 3dB steps
■ The overall analogue gain for the pre-amplifier and analogue amplifier is -3dB to 42dB in 3dB steps, see
Figure 9.3
■ At mid to high gain levels it acts as a microphone pre-amplifier, see Section 9.2.13
■ At low gain levels it acts as an audio line level amplifier
Digital Gain Selection ADC Digital Gain Setting Digital Gain Selection ADC Digital Gain Setting
Value (dB) Value (dB)
0 0 8 -24
1 3.5 9 -20.5
2 6 10 -18
3 9.5 11 -14.5
4 12 12 -12
5 15.5 13 -8.5
7 21.5 15 -2.5
9.2.8 DAC
The DAC consists of:
■ 1 fourth-order Sigma-Delta converter, see Figure 9.2
■ 2 gain stages, 1 of which is an analogue gain stage and the other is a digital gain stage
Digital Gain Selection DAC Digital Gain Setting Digital Gain Selection DAC Digital Gain Setting
Value (dB) Value (dB)
0 0 8 -24
1 3.5 9 -20.5
2 6 10 -18
3 9.5 11 -14.5
4 12 12 -12
6 18 14 -6
7 21.5 15 -2.5
Analogue Gain Selection DAC Analogue Gain Analogue Gain Selection DAC Analogue Gain
Value Setting (dB) Value Setting (dB)
7 0 3 -12
6 -3 2 -15
5 -6 1 -18
4 -9 0 -21
C1 MIC_AP
G-TW-0009558.1.1
Input
R1
C2 Amplifier
MIC_AN
+ MIC1
For the digital microphone interface to work in this configuration ensure the microphone uses a tristate
between edges.
■ The left and right selection for the digital microphones are appropriately pulled up or down for selection on
the PCB.
C1 MIC_AP
G-TW-0009558.1.1
Input
R1
C2 Amplifier
MIC_AN
+ MIC1
C1
MIC_AP
G-TW-0009560.1.1
C2
MIC_AN
G-TW-0008165.2.2
SPKR_AN
DAC
DAC Interface
Side Tone
ADC Interface
ADC
0 -32.6dB 8 -8.5dB
1 -30.1dB 9 -6.0dB
2 -26.6dB 10 -2.5dB
3 -24.1dB 11 0dB
4 -20.6dB 12 3.5dB
5 -18.1dB 13 6.0dB
6 -14.5dB 14 9.5dB
7 -12.0dB 15 12.0dB
The values of side tone are shown for information only. During standard operation, the application software
controls the side tone gain.
The following PS Keys configure the side tone hardware:
■ PSKEY_SIDE_TONE_ENABLE
■ PSKEY_SIDE_TONE_GAIN
■ PSKEY_SIDE_TONE_AFTER_ADC
■ PSKEY_SIDE_TONE_AFTER_DAC
Note:
The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.
Equation 9.1 shows the equation for the IIR filter. Equation 9.2 shows the equation for when the DC blocking is
enabled.
The filter is configured, enabled and disabled from the VM via the CodecSetIIRFilterA and
CodecSetIIRFilterB traps. This requires firmware support. The configuration function takes 10 variables in the
following order:
0 : Gain
1 : b01
2 : b02
(1 +b −1 −2 ) (1 +b −1 −2 )
01 z + b02 z 11 z + b12 z
Filter, H(z) = Gain × ×
(1 +a −1 −2 ) (1 +a −1 −2 )
z +a z z +a z
01 02 11 12
PCM_OUT
PCM_IN
PCM_CLK 128/256/512/1536/2400kHz
G-TW-0000217.3.4
PCM_SYNC 8/48kHz
PCM_OUT
PCM_IN
PCM_CLK Up to 2400kHz
G-TW-0000218.3.3
PCM_SYNC 8/48kHz
PCM_SYNC
PCM_CLK
G-TW-0000219.2.2
PCM_OUT 1 2 3 4 5 6 7 8
PCM_SYNC
PCM_CLK
G-TW-0000220.2.3
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Or
SHORT_PCM_SYNC
PCM_CLK
G-TW-0000221.3.2
PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Figure 9.13: Multi-slot Operation with 2 Slots and 8-bit Companded Samples
PCM_SYNC
PCM_CLK
PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
G-TW-0000222.2.3
Do Not Do Not
PCM_IN Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Care
B1 Channel B2 Channel
8-bit
Sample
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Zeros
Padding
A 16-bit slot with 8-bit companded sample and zeros padding selected.
Sign
Extension
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
13-bit
G-TW-0000223.2.3
Sample
PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Audio
Gain
A 16-bit slot with 13-bit linear sample and audio gain selected.
128
4MHz DDS generation.
Selection of frequency
- 256 - kHz
is programmable. See
Section 9.3.10.
512
fmclk PCM_CLK frequency
48MHz DDS
generation. Selection
of frequency is 2.9 - - kHz
programmable. See
Section 9.3.10.
48MHz DDS
- PCM_CLK jitter - - 21 ns pk-pk
generation
t dmclksynch t dmclkhsyncl
PCM_SYNC
f mlk
t mclkh t mclkl
PCM_CLK
t dmclklpoutz
t dmclkpout tr ,t f t dmclkhpoutz
G-TW-0000224.2.3
t dmclksynch t dmclkhsyncl
PCM_SYNC
f mlk
t mclkh t mclkl
PCM_CLK
t dmclklpoutz
t dmclkpout tr ,t f t dmclkhpoutz
t supinclkl t hpinclkl
t sclkh t tsclkl
PCM_CLK
t hsclksynch t susclksynch
PCM_SYNC
t dpoutz
G-TW-0000226.3.2
t supinsclkl t hpinsclkl
f sclk
t sclkh t tsclkl
PCM_CLK
t susclksynch t hsclksynch
PCM_SYNC
t dpoutz
t dpoutz
t dsclkhpout tr ,t f
t supinsclkl t hpinsclkl
Equation 9.3: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 9.4:
PCM_CLK
f =
SYNC_LIMIT × 8
PCM_OUT SD_OUT
PCM_IN SD_IN
PCM_SYNC WS
PCM_CLK SCK
Table 9.8: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface
Configure the digital audio interface using PSKEY_DIGITAL_AUDIO_CONFIG, see BlueCore Audio API
Specification and the PS Key file.
SCK
SCK
SCK
G-TW-0000230.3.2
SD_IN/OUT MSB LSB MSB LSB
I2 S Mode
- WS Frequency - - 96 kHz
t ssu t sh
t ch t cl
SCK(Input)
topd
SD_OUT
t isu t ih G-TW-0000231.2.2
SD_IN
- WS Frequency - - 96 kHz
Table 9.12: I²S Master Mode Timing Parameters, WS and SCK as Outputs
WS(Output)
t spd
SCK(Output)
t opd
SD_OUT
G-TW-0000232.2.2
t isu t ih
SD_IN
Regulators
Supply Rail
Supply
Switch-mode VDD_AUX VDD_ANA
Configuration
Linear Linear
1.8V 1.35V Regulator Regulator 1.8V 1.35V
Dual-supply
ON ON OFF OFF SMPS SMPS
SMPS
Single-supply
ON OFF ON ON SMPS LDO
SMPS
Parallel-
ON ON ON ON SMPS LDO
supply SMPS
EN
VBAT_SENSE Charger Charge Bypass Linear
OUT
50 to 200mA Reference Regulator 3V3_USB
SENSE
VBAT
IN OUT
1.35V LX_1V35
Switch-mode
EN
RegulatorSENSE
SMPS_1V35_SENSE
Reference
IN OUT
1.8V LX_1V8
Switch-mode
EN
RegulatorSENSE
SMPS_1V8_SENSE
Auxiliary Circuits
IN
VDD_ANA
OUT
Regulator VDD_ANA_RADIO
EN SENSE
Bluetooth
VDD_PADS_1
I/O
VDD_PADS_2
Audio Circuits
Mic Bias
MIC_BIAS
Audio Driver
VDD_AUDIO_DRV
Audio Core
VDD_AUDIO
VDD_DIG OUT
Regulator VDD_DIG_MEM
SENSE
EN
VBAT_SENSE Charger Charge Bypass Linear
OUT
50 to 200mA Reference Regulator 3V3_USB
SENSE
VBAT
IN SENSE
1.35V SMPS_1V35_SENSE
Switch-mode
EN
Regulator OUT
LX_1V35
Reference
IN OUT
1.8V LX_1V8
Switch-mode
EN RegulatorSENSE
SMPS_1V8_SENSE
Auxiliary Circuits
IN
VDD_ANA OUT
Regulator VDD_ANA_RADIO
EN SENSE
Bluetooth
VDD_PADS_1
I/O
VDD_PADS_2
Audio Circuits
Mic Bias
MIC_BIAS
Audio Driver
VDD_AUDIO_DRV
Audio Core
VDD_AUDIO
VDD_DIG VREGIN_DIG
OUT
Regulator VDD_DIG_MEM
SENSE
L1
4.7µH
VBAT LX_1V8 1.8V Supply Rail
LX
G-TW-0008945.1.2
1.8V Switch-mode
3V3_USB Regulator SMPS_1V8_SENSE C3
SENSE 2.2µF
C1 C2 VSS_SMPS_1V8
2.2µF 2.2µF
To 1.35V Switch-mode
Regulator Input
G-TW-0008946.1.2
1.35V Switch-
3V3_USB mode Regulator SMPS_1V35_SENSE C3
SENSE 4.7µF
C1 C2 VSS_SMPS_1V35
2.2µF 2.2µF
To 1.8V Switch-mode
Regulator Input
L1
4.7µH
LX
LX_1V8 1.8V Supply Rail
1.8V Switch-mode
G-TW-0008947.1.2
Regulator SMPS_1V8_SENSE C3
SENSE 2.2µF
VSS_SMPS_1V8
Figure 10.5: 1.8V and 1.35V Switch-mode Regulators Outputs Parallel Configuration
The integrated bypass LDO linear regulator can operate down to 3.0V with a reduced performance.
VREGENABLE should be asserted after the VBAT supply when VREGENABLE is not used as a power-on
button.
The internal regulators described in Section 10.1 to Section 10.7 are not recommended for external circuitry
other than that shown in Section 12.
For information about power sequencing of external regulators to supply the CSR8610 BGA contact CSR.
Pin Name I/O Type Full Chip Reset Pin Name I/O Type Full Chip Reset
The reset protection is cleared after typically 2s (1.6s min to 2.4s max).
If RST# is held low for >2.4s CSR8610 BGA turns off. A rising edge on VREGENABLE or VCHG is required to
power on CSR8610 BGA.
Disabled No X
Table 11.1: Battery Charger Operating Modes Determined by Battery Voltage and Current
(a) Iterm is approximately 10% of Ifast for a given Ifast setting
Standby Mode
G-TW-0005583.3.2
Trickle Charge Mode Iterm
Itrickle Vhyst
Battery Voltage
Vfast
Vfloat
The battery voltage remains constant in Fast Charge Constant Voltage Mode, the curved line on Figure 11.1 is
for clarity only.
The Vfast threshold detection has hysteresis to prevent the charger from oscillating between modes.
CHG_EXT TR 1
External Pass Device
VBAT_SENSE
Rsense
VBAT
R1
G-TW-0005585.2.3
BAT 1
220mΩ Li+ Cell
C1
4.7µF
V BA T_SENSE
Typical Headset Mode,
CHG_EXT
S1
MFB
Dual Switch-mode
K10
H9
K3
K4
K5
K7
K6
A1
A7
K8
K2
B5
B2
C2
E5
E6
J6
J7
J9
V DD_A UX_1V 8
LX _1V 35
VDD_PADS_1
VREGIN_DIG
V REGENA BLE
VBA T_SENSE
SMPS_1V 8_SENSE
SM PS_1V35_SENSE
LX _1V8
VDD_PA DS_2
V CHG
V DD_A UDIO
V BA T
V DD_DIG_MEM
V DD_A UDIO_DRV
V DD_A UX
XT1
26MHz
C1
XTAL_IN
1V35 F9 PIO_0
PIO[0]
F10 PIO_1
PIO[1]
E9 PIO_6
U2 PIO[6]
G10 PIO_7
PIO[7]
ANT 2 4 BT_RF A3 E10 PIO_8
OUT IN BT_RF PIO[8]
G9 PIO_9 PIO
CSR8610 BGA
PIO[21]
2.45GHz
LX_1V35 to Inductor
D2 AIO_0
MIC BIAS AIO[0] Analogue Input / Output
L1 to C4 Track
V SS_BT_LO_A UX
V SS_SMPS_1V 35
H10 USB_P
V SS_SMPS_1V 8
L2 to C7 Track USB_P
J10 USB_N USB (12Mbps)
USB_N
V SS_A UDIO
V SS_BT_RF
MIC_BIA S
SPK R_LN
SPK R_LP
V SS_DIG
A U_REF
MIC_AN
C4 to GND
MIC_AP
C7 to GND J3 RSTB
Reset
NC
NC
NC
NC
RST#
A6
B6
B7
B8
A2
B3
F6
A5
J8
K9
A8
MIC_1N A 10
MIC_1P A 9
MIC_BIA S B9
B4
A4
VBAT to Battery and C2 should be <1Ω from battery SP100
SPK R_LN
SPK R_LP
2u2
BLUE
G-TW-0009564.4.2
5 Li+ CELL PIO_11 5 4 PIO_13 2 6 PIO_10
C105 GND SDA VSS SO/SIO1 SCK Mic(s)
2
GND
LED_1
LED_0
7
S
PIO_n
PIO_n
PIO_n
PIO_n
PIO_n
C2 R3
470n 100k 1V35
VREGENABLE VREGENABLE
VBAT and VCHG Grounded
D
Q1 C3 C4 C5 C6 C8 C9 C10 C11
FDV301N 100n 2u2 100n 470n 15p 2u2 470n 100n
or equivalent
G
S
R2 GND GND GND GND GND GND GND
K10
K4
K5
K7
K6
H9
A1
A7
K8
K3
K2
B5
B2
C2
E5
E6
100k
J6
J7
J9
VREGENABLE
VBAT_SENSE
SMPS_1V8_SENSE
VCHG
LX_1V8
VDD_AUDIO
VDD_AUX_1V8
LX_1V35
VDD_ANA_RADIO
VREGIN_DIG
VDD_PADS_1
VDD_PADS_2
SMPS_1V35_SENSE
CHG_EXT
VBAT
3V3_USB
VDD_AUDIO_DRV
VDD_AUX
VDD_DIG_MEM
XT1
26MHz
GND GND
VREGENABLE Delay Circuit C1
XTAL_IN
VREGENABLE Should be Asserted After
The System Supply Has Risen in The Configuration.
CSR8610 BGA
2.45GHz
PIO[2]/PCM1_IN/SPI_MOSI H1 PIO_2
PIO[3]/PCM1_OUT/SPI_MISO J5 PIO_3
PIO[4]/PCM1_SYNC/SPI_CS# E1 PIO_4
PIO[5]/PCM1_CLK/SPI_CLK J1 PIO_5 PIO / PCM1 / Debug SPI / I2S
SPI_PCM# J4 SPI_PCM# SPI / PCM# High For SPI. Low For All Other Functions
A6 AIO[0] D2 AIO_0
B6
NC
NC
MIC BIAS Analogue Input / Output
B7
VSS_BT_LO_AUX
NC
VSS_SMPS_1V35
B8 USB_P H10
VSS_SMPS_1V8
NC USB_N J10
VSS_AUDIO
VSS_BT_RF
MIC_BIAS
SPKR_LN
SPKR_LP
VSS_DIG
MIC_AN
AU_REF
MIC_AP
RST# J3 RSTB
Reset
A5
A2
B3
F6
J8
K9
A8
MIC_1N A10
MIC_1P A9
B9
B4
A4
SP100
STAR C12
SPKR_LN
SPKR_LP
2u2
C13 C14
100n 100n
L4 R1
MIC_1
15nH 2k2
C17
Mic 1 15p
MIC_BIAS
Microphone Input Mono Speaker (16Ω to 32Ω )
G-TW-0010689.1.1
Note:
For a 1.8V Input Impossible to Maintain Mic Bias Performance.
CSR Recommends An External Mic Bias Supply If Required.
1V8_SMPS
1V8_SMPS 1V35_SMPS
C2 C3 L1 C4 C5 C6 L2 C7 C8 C9 C10 C11
2u2 2u2 4u7 2u2 10n 10n 4u7 4u7 15p 2u2 470n 100n
RSTB
K10
K4
K5
K7
K6
H9
A1
A7
K8
K3
K2
B5
B2
C2
E5
E6
J6
J7
J9
LX_1V8
VDD_AUX_1V8
LX_1V35
VDD_PADS_1
VDD_PADS_2
VCHG
VDD_AUDIO
VDD_ANA_RADIO
VREGIN_DIG
VREGENABLE
VBAT_SENSE
SMPS_1V8_SENSE
SMPS_1V35_SENSE
CHG_EXT
VBAT
3V3_USB
VDD_AUDIO_DRV
VDD_AUX
VDD_DIG_MEM
XT1
26MHz
C1
XTAL_IN
VBAT B1
1V35 PIO[0]
F9 PIO_0
F10 PIO_1
PIO[1]
E9 PIO_6
U2 PIO[6]
G10 PIO_7
PIO[7]
ANT 2 4 BT_RF A3 E10 PIO_8
OUT IN BT_RF PIO[8]
PIO[9]
G9
D9
PIO_9
PIO_18
PIO
Bluetooth RF PIO[18]
PIO[19]
C9 PIO_19
3 1 C10 PIO_20
GND GND PIO[20]
D10 PIO_21
CSR8610 BGA
PIO[21]
2.45GHz
H1 PIO_2
PIO[2]/PCM1_IN/SPI_MOSI
J5 PIO_3
PIO[3]/PCM1_OUT/SPI_MISO
E1 PIO_4
PIO[4]/PCM1_SYNC/SPI_CS#
PIO[5]/PCM1_CLK/SPI_CLK
J1 PIO_5 PIO / PCM1 / Debug SPI / I2S
SPI_PCM#
J4 SPI_PCM# SPI / PCM# High For SPI. Low For All Other Functions
E2 PIO_12
PIO[12] / QSPI_FLASH_CS# / I2C_WP
F5 PIO_10
PIO[10] / QSPI_FLASH_CLK / I2C_SCL
PIO[11] / QSPI_IO[0] / I2C_SDA
G2
G1
PIO_11
PIO_13
PIO / Serial Flash / I2C
PIO[13] / QSPI_IO[1]
F2 PIO_14
PIO[14] / UART_RX
D1 PIO_15
PIO[15] / UART_TX
PIO[16] / UART_RTS
F1
H2
PIO_16
PIO_17
PIO / UART
PIO[17] / UART_CTS
A6 D2 AIO_0
B6
NC
NC
MIC BIAS AIO[0] Analogue Input / Output
B7
VSS_BT_LO_AUX
NC
VSS_SMPS_1V35
B8 H10 USB_P
VSS_SMPS_1V8
NC USB_P
USB_N
J10 USB_N USB (12Mbps)
VSS_AUDIO
VSS_BT_RF
MIC_BIAS
SPKR_LN
SPKR_LP
VSS_DIG
MIC_AN
AU_REF
MIC_AP
J3 RSTB
RST# Reset
A2
B3
F6
A5
J8
K9
A8
MIC_1N A10
MIC_1P A9
MIC_BIAS B9
B4
A4
SP100
STAR C12
SPKR_LN
SPKR_LP
2u2
C13 C14
100n 100n
L4 R1
MIC_1
15nH 2k2
G-TW-0010690.2.2
Mic 1 C17
15p
Supply Voltage
Supply Voltage
Normal Operation
Combined 1.8V and 1.35V Switch-mode Regulator Min Typ Max Unit
Normal Operation
(a) Minimum input voltage of 4.75V is required for full specification, regulator operates at reduced load current from 3.1V.
Normal Operation
Load current - - 60 mA
(a) In the external mode, the battery charger meets all the previous charger electrical characteristics and the additional or superseded electrical
characteristics are listed in this table.
14.3.5 USB
Input Threshold
14.3.6 Clocks
Frequency 16 26 32 MHz
Transconductance 2 - - mS
Resolution - - - 16 Bits
Fsample
B/W = 20Hz→Fsample/2
THD+N 8kHz - 0.0041 - %
(20kHz max)
1.6Vpk-pk input
48kHz - 0.0072 - %
Resolution - - - 16 Bits
Output Sample
- 8 - 96 kHz
Rate, Fsample
Fsample Load
fin = 1kHz
B/W = 20Hz→20kHz 48kHz 100kΩ - 95.6 - dB
SNR A-Weighted
THD+N < 0.1% 48kHz 32Ω - 95.8 - dB
0dBFS input
48kHz 16Ω - 95.6 - dB
Fsample Load
Input Voltage
Tr/Tf - - 25 ns
Output Voltage
Tr/Tf - - 5 ns
Resolution - - 10 Bits
INL -1 - 1 LSB
Accuracy
(Guaranteed monotonic)
DNL 0 - 1 LSB
Offset -1 - 1 LSB
Resolution - - 10 Bits
Human Body Model Contact Discharge per 2kV (all pins except CHG_EXT; CHG_EXT
2
ANSI/ESDA/JEDEC JS‑001 is rated at 1kV)
Any test detailed in the IEC-61000-4-2 level 4 test specification does not damage CSR8610 BGA.
The CSR8610 BGA USB VBUS pin is protected to level 4 using an external 2.2µF decoupling capacitor on VCHG.
Important Note:
CSR recommends correct PCB routing and to route the VBUS track through a decoupling capacitor pad.
When the USB connector is a long way from CSR8610 BGA, place an extra 1µF or 2.2µF capacitor near the
USB connector.
No components (including 22Ω series resistors) are required between CSR8610 BGA and the USB_DP and
USB_DN lines.
To recover from an unintended reset, e.g. a large ESD strike, the watchdog and reset protection feature can restart
CSR8610 BGA and signal the unintended reset to the VM.
Table 14.2 summarises the level of protection.
1-mic CVC:
Slave SCO ■ 8kHz sampling HV3 30 12.6 mA
■ Narrowband
1-mic CVC:
Slave eSCO ■ 8kHz sampling 2EV3 60 10.8 mA
■ Narrowband
1-mic CVC:
Slave eSCO ■ 16kHz sampling 2EV3 60 10.9 mA
■ FESI
1-mic CVC:
Master eSCO ■ 8kHz sampling 2EV3 60 10.5 mA
■ Narrowband
1-mic CVC:
Master eSCO ■ 16kHz sampling 2EV3 60 11.0 mA
■ Wideband
1-mic CVC:
Master eSCO ■ 16kHz sampling 2EV3 60 10.6 mA
■ FESI
Note:
Current consumption values are taken with:
■ VBAT pin = 3.7V
■ RF TX power set to 0dBm
■ No RF retransmissions in case of eSCO
■ Microphones and speakers disconnected
■ Audio gateway transmits silence when SCO/eSCO channel is open
■ LEDs disconnected
■ AFH classification master disabled
Benzene 1000ppm
1,1,1-trichloroethane Banned
Tributyl tin (TBT) / Triphenyl tin (TPT) / Tributyl Tin Oxide (TBTO) Banned as intentionally introduced
Dibutyl Tin (DBT) and Dioctyl Tin Compounds (DOT)
SPI Flash
PS Keys
Configuration
Patches
CSR8610 SPI
G-TW-0009563.1.1
Programmable
Audio Prompts
EEPROM
PS Keys
Configuration
Patches
CSR8610 I2C
G-TW-0009562.1.1
Programmable
Audio Prompts
When using the SPI flash interface for programmable audio prompts, an EEPROM device is not required in the
CSR8610 1-mic mono headset.
17.2 6th Generation 1-mic CVC ENR Technology for Hands-free and Audio
Enhancements
1-mic CVC full-duplex voice processing software is a fully integrated and highly optimised set of DSP algorithms
developed to ensure easy design and build of hands-free products.
CVC enables greater acoustic design flexibility for a wide variety of environments and configurations as a result of
sophisticated noise and echo suppression technology. CVC reduces the affects of noise on both sides of the
conversation and smartly adjusts the receive volume levels and dynamically frequency shapes the voice to achieve
optimal intelligibility and comfort for the hands-free user.
The 6th generation CVC features include:
■ Full-duplex AEC
■ Bit error and packet loss concealment
■ Transmit and receive noise suppression including WNR
■ Transmit and receive Parametric Equalisation
■ Transmit and receive AGC
■ Noise dependent volume control
■ Receive frequency enhanced speech intelligibility using adaptive equaliser
■ Narrowband, wideband and frequency expansion operations
NDVC
Bluetooth Radio
G-TW-0010188.1.1
Auxiliary
Stream Mix
Receive Out
Receive Adaptive Noise Packet Loss
Speaker Gain Clipper Receive AGC
Equaliser Equaliser Suppression Concealment Receive
In
17.2.6 Equalisation
The equalisation filters:
■ Are independent in the send and receive signal channels
■ Are independently enabled
■ Are configurable to achieve the required frequency response
■ Each channel comprises of 5 stages of cascaded 2nd order IIR filters
■ Compensate for the frequency response of transducers in the system, i.e. the microphone and loud speaker
The PLC is enabled in all modes, HFK (full processing), pass-through and loopback by default.
17.2.11 Clipper
The clipper block intentionally distorts or clips the receive signal prior to the reference input of the AEC in order to
more accurately model the behaviour of the post reference input blocks such as the DAC, power amplifier and the
loudspeaker. The AEC attempts to correlate the signal received at the reference input and the microphone input.
Any non-linearities introduced that are not accounted for after the reference input will significantly degrade the
AEC performance. This processing block can significantly improve the echo performance in cheap non-linear system
designs.
The CSR8610 1-mic Mono Headset audio development kit is subject to change and updates, for up-to-date
information see www.csrsupport.com.
Circular Holes
Pin A1 Marker
A≥B
G-TW-0002434.3.2
B
Ø 1.5 +0.1/-0.0
8.00 MIN
2.00 ±0.10 SEE NOTE 3 Ø 1.50 MIN
4.00 SEE NOTE 1 1.75 ±0.10
0.30 ±0.05
A
16.0 ±0.3
A
G-TW-0007442.1.1
K0 R 0.5 TYP
0.66
A0
4.48
SECTION A - A
W3
Package Tape A W2
B C D Min N Min W1 Units
Type Width Max Max
Min Max
5.5 x 5.5 x
13.0 16.4
1mm 16 332 1.5 20.2 50 19.1 16.4 19.1 mm
(0.5/-0.2) (3.0/-0.2)
VFBGA
Core Specification of the Bluetooth System Bluetooth Specification Version 4.0, 17 December 2009
IEC 61000-4-2
Electromagnetic compatibility (EMC) – Part 4-2: Testing IEC 61000-4-2, Edition 2.0, 2008-12
and measurement techniques – Electrostatic discharge
immunity test
AC Alternating Current
AG Audio Gateway
BlueCore® Group term for CSR’s range of Bluetooth wireless technology ICs
Bluetooth® Set of technologies providing audio and data transfer over short-range radio connections
DC Direct Current
G.722 An ITU-T standard wideband speech codec operating at 48, 56 and 64 kbps
I/O Input/Output
IC Integrated Circuit
IF Intermediate Frequency
Kalimba An open platform DSP co-processor, enabling support of enhanced audio applications, such
as echo and noise suppression, and file compression / decompression
Kb Kilobit
LM Link Manager
Mb Megabit
NR Noise Reduction
PA Power Amplifier
PC Personal Computer
RF Radio Frequency
RX Receive or Receiver
TBD To Be Defined
TX Transmit or Transmitter
UI User Interface