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3, MARCH 2017
A New Direction for III–V FETs for Mobile
CPU Operation Including Burst-Mode:
In0.35Ga0.65As Channel
T. Rakshit, B. Obradovic, W.-E. Wang, W.-H. Kim, K.-M. Shin, S.-C. Baek, S.-W. Lee, S.-H. Kim, J.-M. Lee,
D. Kim, A. Hoover, W.-B. Song, M. Cantoro, Y.-C. Heo, R. Rooyackers, S. C. Ardila,
A. Vais, D. Lin, N. Collaert, and M. S. Rodder
Abstract — In this letter, we show that conventional
III–V MOSFETs with moderate/high In content channels
(In0.53 Ga0.47 As or In0.70 Ga0.30 As) at scaled nodes are
incompatible with mobile SoC designs, which often operate
at intermediate/high Vdd (0.7 V to ≥1 V) to achieve high
frequency including during burst-mode. The incompatibility
is due to conventional III–V FETs having too small bandgap,
and thus too high leakage when operated at the increased
voltages. We show that FETs with a more optimal lower In
content, In0.35 Ga0.65 As, have the necessary combination of
larger bandgap (∼Si) and sufficiently high injection velocity
(∼2.5 times Si) to enable both low leakage and high perfor-
mance (versus Si), across the entire Vdd range of mobile
SoC operation. We report for the first time the growth and
characterization of ultra-thin In0.35 Ga0.65 As FETs with a
standard 1nm EOT gate dielectric. Calibrated models show
that In0.35 Ga0.65 As enables the highest performance at very
low leakages at intermediate/high Vdd in short channel
FETs.
Index Terms — In0.35 Ga0.65 As, high voltage, mobile CPU,
leakage, parasitic bipolar effect, performance.
I. I NTRODUCTION
T HE majority of mobile SoC CPU devices must
achieve (1) very low leakage (Vgs = 0V, Vds = Vdd)
∼100pA/μm-few nA/μm at normal operating voltages, as
well as (2) acceptable ≤2x normal operating leakage at inter-
mediate and burst-mode operating voltages (0.7V to ≥1V).
These two constraints narrow the channel materials of choice
for III-V FETs. Significant progress has recently been made
on the topic of III-V materials for logic devices [1].
These materials, primarily In0.53 Ga0.47 As or In0.70 Ga0.30 As,
are generally benchmarked at low Vdd of 0.5V and high
Manuscript received December 15, 2016; revised January 13, 2017;
accepted January 20, 2017. Date of publication January 25, 2017; date of
current version February 22, 2017. The review of this letter was arranged
by Editor L. Selmi.
T. Rakshit, B. Obradovic, W.-E. Wang, and M. S. Rodder are
with Samsung Advanced Logic Lab, Austin, TX 78754 USA (e-mail:
titash.r@samsung.com).
W.-H. Kim, K.-M. Shin, S.-C. Baek, S.-W. Lee, S.-H. Kim, J.-M. Lee,
and D. Kim are with imec, Leuven 3001, Belgium.
A. Hoover is with Samsung Austin R&D, Austin, TX 78730 USA.
W.-B. Song, M. Cantoro, and Y.-C. Heo are with Samsung, Seoul,
South Korea.
R. Rooyackers, S. C. Ardila, A. Vais, D. Lin, and N. Collaert are with
imec, Leuven 3010, Belgium.
Color versions of one or more of the figures in this letter are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2017.2658447
0741-3106 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO.
Ioff = 100nA/um [1]–[5]. However, voltages in mobile SoC
CPUs are in a range bound by (1) low voltage defined by
Vccmin (∼0.5-0.6V) and (2) high voltage for burst-mode max
frequency applications (e.g. turning on the phone, touching
the phone to wake up, or starting up an app) [6]. Based
on the real-time user application, the operating system soft-
ware adaptively selects any processor voltage within these
bounds. Thus, operation across a wide voltage range and
with still acceptable leakage is required for III-V FETs in
a mobile SoC design. In0.53 Ga0.47 As or In0.70 Ga0.30 As FETs
operated only at 0.5V have lower effective drive current
(Ieff) than a Si FET driven close to 1V, primarily due to
low gate overdrive [7], and thus cannot deliver comparable
max frequency (vs. Si).There have been impressive work
to minimize the leakage in moderate/high In materials like
source-drain heterostructure engineering [2], ultra-thin body
channels [3], trigate [4] and gate-all-around architectures [5]
all of which still do not meet the mobile design leakage specs.
These materials may be more suitable for high leakage server
applications that are not addressed in this letter. Section II
identifies the problem with conventional III-V FETs. Then
we make the case that In0.35 Ga0.65 As FETs can achieve the
desired performance. We report for the first time, in Section III,
the growth, fabrication, and characterization of long-channel
ultra-thin (down to 6nm) In0.35 Ga0.65 As FETs with a 1nm EOT
gate dielectric. Section IV details the calibrated models that
have been developed to predict short-channel characteristics
of In0.35 Ga0.65 As and In0.53 Ga0.47 As FETs. We conclude
that high In content channel materials are incompatible for
power-constrained mobile CPU applications and propose using
In0.35Ga0.65 As for best performance at acceptable leakages
across the entire range of Vdd.
II. I NTERMEDIATE /H IGH VOLTAGE O PERATION OF
In0.53 Ga0.47 As D EVICES AND THE C ASE FOR
In0.53 Ga0.47 As
To quantify In0.53Ga0.47 As leakages at intermediate and
high voltages, long-channel In0.53Ga0.47 As QWFET source
current (Is) vs gate voltage (Vg ) for 8nm and 6nm QW widths
were measured (Fig. 1 (a)). (The device fabrication follows as
described in Section III). Note that we use Is over drain current
(Id) in this letter to deconvolve any effects of gate leakage (Ig).
While the long channel off-state leakage current (Vg = 0V)
meets the ∼100pA/μm range upto Vds = 0.95V, models
RAKSHIT et al.: NEW DIRECTION FOR III–V FETs FOR MOBILE CPU OPERATION
Fig. 1. (a) Measured long channel (10 um) leakage characteristics of
In0.53 Ga0.47 As QWFETs and (b) simulated evolution of leakage into
shorter channels based on calibrated models. Each curve for short
channel signifies lengths of 35, 25 and 15nm. Blue box signifies required
Mobile CPU leakage levels including burst mode.
Fig. 2. (a) Band Profile showing effect of PBE in a confined channel. PBE
induced increase in thermionic electron density in the off-state is also
shown. (b) Injection velocity (Ieff performance) vs Bandgap (leakage) as
a function of Indium content.
calibrated to the data in Fig. 1 (a) (parameters in Table I),
show that In0.53 Ga0.47 As FETs will have significantly higher
leakage, even at Vdd = 0.75V, as gate length is reduced
(Fig.1 (b)). This higher leakage is caused by (1) increased
diffusive leakage and by (2) the Parasitic Bipolar Effect (PBE),
if present [7]. PBE occurs in FET structures in which minority
holes generated by band-to-band tunneling (BTBT) cannot
leave the channel through a substrate, as in a standard
QWFET structure without a substrate connection due to the
sub-channel high bandgap barrier layer or as in a gate-all-
around (GAA) structure ([1]–[5]). In short channel FETs, the
trapped holes lower the source-channel barrier for electrons
resulting in bipolar gain and an increased thermionic electron
current (Fig. 2 (a)), over and above usual 2D electrostatic
degradation. As shown in Fig. 1 (b), the significantly higher
leakage (>>100pA/μm range, even at only 0.75V) from the
combination of PBE and electrostatic degradation precludes
the use of In0.53 Ga0.47 As as the channel material of choice
in III-V FETs for mobile CPU.
The root cause of the high leakage with In0.53Ga0.47 As is its
small bandgap. While confinement can increase the bandgap,
it is not sufficient to enable operation above ∼0.65V (as shown
in Fig. 5). However, the bandgap can be increased significantly
by reducing In content. The bandgap for In0.35 Ga0.65 As is
greater than 1eV, similar to Si (although direct). The injection
velocity, a key figure-of-merit for short channel FET perfor-
mance [8], is reduced by less than 10% for In0.35 Ga0.65 As
(vs. In0.53 Ga0.47 As) (Fig. 2 (b)).
III. F IRST D EMONSTRATION OF A 1 NM EOT D IELECTRIC
ON AN U LTRA -T HIN IN 0.35 GA0.65 AS C HANNEL
To compare In0.35 Ga0.65 As and In0.53 Ga0.47 As channels
with minimum process uncertainty, the two channel mate-
315
Fig. 3. (a) TEM of the 1nm EOT dielectric (1nm Al2 O3 + 3nm HfO2 )
on the In0.35 Ga0.65 As QW. (b) Measured C-V frequency dispersion from
1kHz to 1MH for In0.35 Ga0.65 As and In0.53 Ga0.47 As QWFETs at long
channel.
Fig. 4. (a) Measured Subthreshold Slope as a function of temperature
and (b) measured Isource(Is)-Gate voltage (Vg) characteristics com-
paring In0.35 Ga0.65 As and In0.53 Ga0.47 As QWFETs at long channel
(10 um). The hysteresis in I-V is around 30mV for positive to negative
sweep. The bandgap delta between the two materials leads to majority
of the shift in minimum (Imin) leakage points.
rials were grown on the same stack. 8nm and 6nm thick
quantum wells were fabricated, consistent with the channel
thickness as required in short channel FETs. The substrate
was semi-insulating InP, followed by high bandgap 400nm
In0.52 Al0.48 As buffer layer, thin QW channel, a 3nm InP etch
stop layer and n++ InGaAs S/D layer. Thus, by design, the
In0.53Ga0.47 As QW is relaxed and In0.35Ga0.65 As QW is ∼1%
tensile strained. AFM images of the two QW surfaces show
same surface roughness of 0.19nm RMS value. The two stacks
went through the same standard process flow [9], using a high
performance 1nm EOT dielectric (1nm Al2 O3 + 3nm HfO2 )
formed directly on both QWs (the 3nm InP is etched off
prior to dielectric formation). Both samples received aqueous
(NH4 )2 S treatment prior to ALD (1nm Al2O3/3nm HfO2 )
deposition. The Al2 O3 layer was deposited at 300C with
TMA (Trimethylaluminum) and H2 O as precursors while the
subsequent HfO2 layer was deposited with TMAH and H2 O
precursors at the same temperature.
To demonstrate the quality of a standard 1nm EOT dielectric
on In0.35 Ga0.65 As QW channels (Fig. 3 (a)), we evaluated
various e-test metrics. The C-Vs of the two stacks show
similar dispersion from 1kHz to 1MHz with good turn-on
(Fig. 3 (b)). The measured subthreshold slope vs. tempera-
ture for both In0.35 Ga0.65 As and In0.53 Ga0.47 As stacks show
near ideal behavior from 77K to 300K (Fig. 4 (a)). The
slope is measured from minimum leakage current (Imin) to
∼3 orders of magnitude higher current. This clearly indicates
the 1nm Al2 O3 + 3nm HfO2 dielectric formed directly on
In0.35Ga0.65 As has low interface traps similar to that for
In0.53Ga0.47 As. The C-V does not show signs of spillover
into the low mobility L valley for In0.35 Ga0.65 As channels.
316
However, as noted in several previous publications the level
of border trap induced hysteresis and frequency dispersion is
significant in direct thin highK on any ternary material system
and requires more careful extraction ([10]–[12]) that is beyond
the scope of this letter. Simulated C-V from the bandstructure
as detailed in Section IV matches closely with the measured
C-V at 77K and 1MHz where the effects of traps are mostly
mitigated [12]. Gate leakage is comparable between the two
stacks. To our knowledge, this is the first demonstration of
a high performance 1nm EOT dielectric on In0.35 Ga0.65 As
channels, vs. the thicker dielectric previously reported for a
low In content channel [13].
IV. S HORT C HANNEL M OSFET I-V F ROM
DATA -B ASED M ODELS
To simulate short-channel FET characteristics with different
In content, we first measure long-channel 6nm QWFET source
current (Is) vs. gate voltage (Vg) (Fig. 4 (b)). Reducing In
content from 53% to 35% reduces the long-channel BTBT
related minimum leakage (Imin) across all Vg by 3 orders
of magnitude at Vds = 0.95V. BTBT is the key factor
determining Ioff at long channel lengths and we calibrate key
material properties that impact tunneling from this dataset;
extracted parameters are summarized in Table I.
To quantify leakage-performance at short channels, we
simulated scaled short channel finFETs, with Lg = 15nm,
fin width = 6nm, height = 35nm, EOT = 1.0nm,
since finFETs are the state-of-the-art FET structure [16].
Source-drain heterostructure engineering although is an inter-
esting way to reduce off-state leakage [2], was not deemed
feasible at a scaled node where source-drain openings of 20nm
or less might make it difficult to grade to a higher bandgap
material abruptly. It is even more challenging to grow and
selectively etch the S/D stack in a scaled finFET structure as
required for a scaled node.
Three materials, In0.53 Ga0.47 As, In0.35 Ga0.65 As and Si were
compared across the voltage range in mobile CPUs. The
bandstructure was computed using sp3d5s∗ Tight-Binding
parameters [14]. The computation was performed for a range
of Indium fractions and channel thicknesses. For each thick-
ness/fraction combination, the injection velocity was com-
puted from the bandstructure as a function of the electron
concentration at the top of the barrier. This was performed
by numerical integration of the transport component of the
group velocity in 2-D k-space, weighted by the carrier occu-
pation. While Drift-Diffusion was used for the final device
simulation, the effect of the expected near-ballisticity of short-
channel InGaAs devices was taken into account. This was
done by using a mobility model that Matthiessen-combines
the long-channel mobility with the ballistic mobility [15], with
the ballistic mobility calibrated for each structure to insure
that the obtained electron velocity at the top of the barrier
matches the expected injection velocity. The vsat parameter
of Drift Diffusion was adjusted so that the peak velocity
near the drain obtained from short-Lg simulation matches
the ballistic velocity computed from the bandstructure at the
appropriate Vdd. While short-channel devices therefore exhibit
ballistic-like behavior by construction, devices with longer
IEEE ELECTRON DEVICE LETTERS, VOL. 38, NO. 3, MARCH 2017
TABLE I
T HE C ALIBRATED B ANDGAP AND K ANE T UNNELING M ASS mr ARE
S HOWN FOR THE T WO C HANNEL C OMPOSITIONS
AND T HICKNESSES
Fig. 5. Calibrated short channel finFET Ieff(performance)-Ioff
total(leakage) simulations show that for Vdd > 0.65V In0.35 Ga0.65 As
channels are the best solution both without PBE (a) and in pres-
ence of PBE (b) which makes leakage orders of magnitude worse for
In0.53 Ga0.47 As.
channels (>30nm or so) do show the impact of long-channel
mobility.
Fig. 5 shows performance (Ieff) ( = 0.5∗ Id@(Vds = Vdd,
Vgs = Vdd/2)+0.5∗Id@(Vds = Vdd/2,Vgs = Vdd)) vs
leakage (Ioff total) on structures without PBE (a) and with
PBE (b). Simulated short channel In0.53 Ga0.47 As finFETs,
even with superb electrostatics from 6nm fin thickness, can
barely meet 100pA/μm specs to 0.65V with or without PBE.
Beyond 0.65V, these leakage targets are not met. However, the
increased bandgap of lower In content In0.35 Ga0.65 As FETs
translates into a dramatic reduction in short-channel leakage
current beyond 0.65V due both to reduced BTBT (Fig. 5(a))
and subsequently reduced PBE driven leakage amplification
(Fig. 5(b)). The reduction in both BTBT and PBE with
lower In content allows In0.35 Ga0.65 As to be operated up to
0.95V in a bulk finFET structure (without PBE). As seen
from Fig. 5, at higher Vdd, In0.35 Ga0.65 As provides the best
Ieff-Ioff performance and outperforms short channel projected
Si performance (benchmarked using [7]) by more than 30%.
The performance gain vs Si is due to the still sufficiently high
injection velocity for In0.35Ga0.65 As.
V. C ONCLUSIONS
We show that In0.53 Ga0.47 As or higher In content channel
materials are incompatible with standard mobile SoC designs
due to high leakage of short-channel FETs across the required
voltage range of operation. We show a new direction for
III-V technology for power-aware channel material selection.
III-V FETs with In0.35Ga0.65 As channel material provides the
best trade-off between performance and acceptable mobile
CPU leakage up to 0.95V. We demonstrate for the first
time excellent properties of tensile In0.35 Ga0.65 As QWFET
channels down to 6nm with 1nm EOT dielectric. Incorporation
of In0.35 Ga0.65 As in a short channel high performance FET is
a new direction for power constrained mobile CPUs.
RAKSHIT et al.: NEW DIRECTION FOR III–V FETs FOR MOBILE CPU OPERATION
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