Professional Documents
Culture Documents
The Current Conveyor History Progress
The Current Conveyor History Progress
The Current Conveyor History Progress
A.S. Sedra
G.W. Roberts
F. Gohh
b
vq7t-
- Gd{J1n
'X
Fig. 6 Nullator-norator representations of CCIIs llS
a Positive or negative CCII 5
b Simplised representationof negative CCII Fig. 7 Comparison of C C I I - and nMOS transistor
Mplm
amp, in which case current will be restricted to flow into VDD
the X terminal. It follows that a CCII realisation that t
allows bidirectional current flow can be obtained by
placing a complementary pair of MOS transistors in the MPp MP)
op amp feedback path as shown in Fig. 9a. Observe,
however, that this circuit is now a CCII + realisation. To
obtain a CCII- circuit two additional mirrors are pb
required, as shown in Fig. 96.
In the circuits of Fig. 9 the M,-M2 pair of transistors V r \
may be thought of as a class B output stage for the op
amp. This circuit, therefore, is not much different to that
used by Wilson [l5] and Toumazou and Lidgey [16, 171
except that they sense the total supply current of a com-
mercially available op amp (simply because they do not
have access to the output stage of the op amp as would
be available in a fully integrated conveyor realisation).
We have recently fabricated a realisation based on the
circuits of Fig. 9 with Northern Telecom's 5 pm CMOS
process [21]. The design details and the measured per- t
formance of these monolithic current conyeyor circuits vss
will be reported in the following section. Fig. 9 Current conveyors
While current mirrors form an essential part of the a Positive
CCII realisation, the CCII may be thought of as provid- b Negative
ing a current mirror with greatly improved performance.
This ingenious point of view has enabled the application floating differential-input, differential-output op amp as
of current conveyors in the design of a high performance shown in Fig. lob. The significance of this correspon-
algorithmic A/D convertor [24]. dence is that it suggests alternative ways of realising a
Before leaving this section, it is interesting to point out negative current conveyor. For example, a CCII - can be
that, in addition to the similarity between a CCII- and approached quite closely by replacing the fully differen-
an ideal transistor, a similar correspondence can be tial op amp with a floating VCVS of large voltage gain A
drawn between a CCII - and an ideal fully differential op as depicted in Fig. lOc, or alternatively, with a floating
amp. The terminal behavior of a floating differential op VCCS of large transconductance as illustrated in Fig.
amp connected in a negative feedback arrangement can 10d. This approach was outlined by Huijsing and De
be represented by the nullor circuit shown in Fig. loa. It Korte [22] in the context of creating a fully integrated
should be obvious that a connection between terminals 2 nullor circuit (or more appropriately in the present
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990 81
context, a CCII -), however, they realised their nuilor will be avilable in the near future. In the mean time we
circuit in a manner similar to that described for the cir- shall present the experimental results pertaining to a
cuits of Fig. 9, the difference being that they used a 5 pm CMOS implementation of a positive and negative
current steering approach to accomplish the current buf- CCII based on the circuits of Fig. 9.
3"' c
A
X
circuit combinations. Invariably the high frequency per-
formance will suffer due to the additional stray capac-
itances at the pins, but this is an acceptable cost when
one considers the flexibility purchased.
The op amp topology is based on the popular two-
stage CMOS op amp configuration [lo] with an addi-
tional low output impedance stage. The circuit schematic
of the CMOS op amp is shown in Fig. 11. The drains of
the transistors that make up the output buffer stage (M,,
and M,,) are not connected directly to the power rails,
but rather connected to external pins of the integrated
b circuit. This provides a possible means of sensing the
current in the output stage, as required in the conveyor
d
realisations of Fig. 9. In fact, transistors M1 and M, of
the current conveyors depicted in Fig. 9 are actually tran-
Fig. 10 Correspondence between an ideal op amp and a C U I - sistors M,, and M,, of the CMOS op amp.
a Nullor reprsssntation of an ideal op amp
b Op amp equivalent circuit of a CCII -
The op amp circuit shown in Fig. 11 utilises two
c VCVS representationof a CCII -, A m
d VCCS representationof a CCII - G, m - power supplies of f.5V and is biased externally through
a resistor to obtain a bias current of 25 pA. M, and M,,
with current source M, , form the differential input stage.
fering between terminals X and Z, in contrast to the M, and M, in the current mirror configuration converts
above mentioned current mirroring approach. At the the ouput differential signal to a single-ended signal.
present time we are investigating the feasibility of using Transistor M, along with biasing transistor M, form the
floating transconductance stages in a negative feedback second stage. M, and M, provide a bias voltage for the
arrangement to realise a CCII- and hopefully results output stage consisting of MI, and M,, . Devices M,,
VDD
t1
I MS
I 150/10
Ma
402 5/5
5 1pF
95/10
M3 M&
50/10 50/10
___
"ss
Fig. 11 Circuit schematic of the CMOS op amp
~~
and M,, along with compensation capacitor C, provide input bias voltage of the p-channel current mirror. Since
the internal compensation of the op amp. MI, with bias the supply lines are limited to + 5 V, the use of current
resistor R,, supply the bias voltage for current sources mirrors with large input bias voltages would severely
M, and M,. In Table 1 we list a typical set of op amp restrict the signal swing at terminal X.
The circuit implementation of the positive current con-
Table 1 : Measured CMOS OD am0 Darameters veyor is as shown in Fig. 9. The dimensions of the PMOS
Parameters Experimental results Units transistors of the current mirror, MP, and MP,, are
U . = 25 uA) 365 pm by 10 pm, while the dimensions of the nMOS
Open loop 72.7 dB transistors, MN, and MN,, are 200 pm by 10 pm. The
gain (50 Hz) larger than minimum lengths of the transistors are used
output 1051 n to provide an improved output impedance at terminal Y,
resistance while the large W / L ratio of the transistors results in
3 dB 400 Hz
smaller input bias voltage requirements.
frequency
6.2 Netagive current conveyor
Unity gain 2.2 MHz
frequency The negative current conveyor circuit can be derived
from the positive current conveyor through the addition
Slew rate (pos) +2.26 V per p e c
of two current mirrors. Unlike the current mirrors of the
Slew rate (neg) -6.87 V per w s positive current conveyor, the additional current mirrors
Power 1.21 mW are not restricted to small input voltages. As such, either
dissipation simple or stacked current mirrors can be used to achieve
Input offset 17.4 mV different current conveyor performances.
voltage A negative current conveyor using simple current
PSRR mirrors was illustrated in Fig. 9b. The dimensions of the
100 Hz 68.3 dB transistors making up the simple current mirrors are
10 KHz 47.8 dB identical to those used in the positive current conveyor.
500 KHz 13.1 dB We depict a negative current conveyor using stacked
current mirrors in Fig. 12. The only difference between
characteristics measured from a small sample set of fabri-
cated op amps.
The requirements on the current mirrors to be used "OD
within the current conveyors are: linear current gain, t
large output impedance, wide output voltage swing, small
input bias voltage and good high frequency response.
The ability to satisfy some of the above requirements
depends upon the type of current mirror chosen. There
are basically five different types of current mirrors in
CMOS technology [lo]: (i) simple current mirror, (ii)
-
cascode or stacked current mirror, herein referred to as
the stacked current mirror, (iii) Wilson current mirror,
(iv) improved Wilson current mirror and (v) cascode
current mirror with improved biasing, herein referred to
as a modified cascode current mirror. Prior to fabrication I II
a SPICE investigation was performed to compare the
various attributes of the 5 current mirrors above and
thus we came to the conclusion that one must trade off
output impedance and current conveying accuracy for
larger output voltage swing. The simple and stacked --?----
current mirrors typify this performance tradeoff and will
be the only mirrors considered for implementation in this
+ "ss
work. Fig. 12 Negntiue current conueyor design using stacked current
mirrors
6.1 Positive current conveyor
The first circuit implemented is the positive current con- Fig. 12 and Fig. 9b is that the second pair of simple
veyor since the negative current conveyor can be con- current mirrors have been replaced by a pair of stacked
sidered an extension of the positive current conveyor. In current mirrors. The stacked current mirrors are con-
its implementation, simple current mirrors were used, structed of 342.5 pm by 5 pm PMOS transistors and
despite their low output impedance and poor current 207.5 pm by 5 pm nMOS transistors. Reduction of the
gain. The reason behind this choice follows from the channel length is possible in the stacked current mirrors
allowable signal swing at the X terminal. The positive due to the high impedance nature of the circuit. The W / L
signal swing of the X terminal (refer to Fig. 9 4 is deter- ratios of the transistors within the stacked current
mined by the state of transistor M, while the negative mirrors were increased, to reduce the input bias voltage,
signal swing is determined by M, . As long as both tran- as well as providing as much output signal swing as pos-
sistors remain saturated, the output stage of the op amp sible.
will perform as expected. Thus the negative signal swing
is restricted to V's,2 above the negative input bias 6.3 Experimental results
voltage of the nchannel current mirror, while the positive The current conveyors were constructed with the appro-
signal swing is restricted to Vk,l below the positive priate building blocks and measurements were taken to
IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL 1990 83
determine the small and large signal characteristics. Due difference i, - iz is displayed as a function of i x . If one
to the building block concept, the positive and negative excludes any offset current error, one can see from these
current conveyors can physically be constructed with the results that the CCII + has the lowest current error, fol-
same op amp and first pair of current mirrors. This pro- lowed by the CCII- (stacked mirrors) and then the
vides the opportunity to compare the effects of using CCII - (simple mirrors).
different current mirrors with additional variables intro-
duced by employing different op amps and first pair of
current mirrors. As anticipated, the voltage transfer char-
acteristics between terminal Y and X are identical for all
current conveyors since they utilise the same op amp.
The large signal voltage transfer characteristic between
terminals Y and X is shown in Fig. 13.
The test points of Fig. 13 were taken with terminal X 5ol -2-
loaded with a 10 MR probe and terminal Z grounded. U
- -4-
0
r
-6-
L-
-8 -
3-
2-
1hO lobo 10600 100000 106 10;
1- frequency, Hz
.' Fig. 14 Measured small-signal magnitude response of the voltage gain
>x 0-
- between terminals X and Y
-1
0 = CCII+
-2- A = CCII - (simplemirrors)
0 = CCII - (stocked mirrors)
-3-
40
- L - 4 - 3 - 2 - 1 o 1 2 3 4
"V." 301
Fig. 13 Measured large signal voltage characteristics between termin- Q, 20-
aJs Y and X for the positive and negative current conveyors N
I
0 = CCII+
A = CCII - (simpk mirrors)
..
L
10-
E
L
-10-
Under this 'open circuit' test condition, the maximum 2 -20-
voltage difference between Y and X did not exceed 8 mV
over the linear range. For the situation with X loaded, -30-
the large signal voltage gain remains unchanged provided
the current supplied by terminal X does not exceed the A O L '
-300
a
-200
3
-100
a
0
' "
100 200
"
300
I
.
current supplying capability of the op amp output stage.
source current Ix .PA
Thus, for linear circuit operation, the large-signal voltage
gain between terminals Y and X is 1.0 V/V. Fig. 15 Measured large signal current error
The small-signal magnitude response of the voltage = CCII+
A = CCII- (simplemirrors)
gain from terminal Y to X as a function of frequency is 0 = CCII - (stocked mirrors)
shown in Fig. 14. The same open circuit test conditions
were used for this measurement as for the above large-
signal voltage transfer characteristics. As expected, the The small-signal magnitude response of the current
bandwidth of this voltage gain response corresponds with gain from terminal X to Z as a function of frequency can
the unity-gain bandwidth of the op amp (see Table 1) and be estimated from the voltage-gains displayed in Fig. 16
is the same for all three current conveyors investigated. for the above mentioned inverting amplifier test setup.
Other large-signal parameters related to the input ter- Here we include only those measured results applicable
minals include the input resistance at terminal Y, which to the positive current conveyor and the negative current
was measured to be greater than 10 MR (the input resist- conveyor with stacked mirrors. (The frequency response
ance of the multimeter), while the large-signal input of the negative current conveyor with simple mirrors was
resistance at terminal X was found to be approximately not measured). It is evident from the various voltage-gain
0.5 R. measurements that the current-gain bandwidth is not as
The large-signal current gain between terminal X and large as should be expected, in fact it is somewhat less
Z (iJi,) was measured by loading X and 2 with 10 kR than the bandwidth of the voltage gain uu/ux as illus-
resistances while applying a voltage source at terminal Y trated in Fig. 14. We attribute this loss of current-gain
(i.e. inverting amplifier configuration). In this manner, i , bandwidth to the parasitic poles created by the stray
and iz can be controlled and measured with voltage capacitance at the pins interconnecting the amplifier and
levels, although these measurements will be affected by the various current mirrors, and the poles created by the
the output resistance at terminal Z. The results of the capacitance shunting the output resistance of the inver-
measurements are plotted in Fig. 15 where the current ting amplifier. This was the price we paid for fabricating
84 IEE PROCEEDINGS, Vol. 137, Pt. G, N o . 2, APRIL I990
our conveyor circuits in building block form and for 7 Filter circuits using current conveyors
using a voltage gain to estimate a current gain. It is inter-
esting to note that the effective unity-gain-bandwidth 7.1 Inductance Simulation
In the area of active filter design, inductor simulation has
product exhibited by these current conveyors circuits is
attracted considerable interest. The advantage of design-
larger than the gain-bandwidth product of the op amp.
ing active filters by simulating the inductors of a passive
LCR realisation of the filter include low component sen-
sitivities and the ability to utilise the extensive knowledge
50-
of LCR filter design. One of the methods in which an
RX:lOOkQRZ:lOkfl inductor can be simulated is through the use of a gyrator
LO - and a single capacitor. A gyrator can be realised by con-
necting together two current conveyors of opposite
:- 30-
R X :lkn.RZ ;lOkA
polarity [ll] as shown in Fig. 17. By terminating one of
;
0
:7
20
9 10
RX:lOknbRZ=lOkn I -~
o-
-10 '
-h-
a
I XI .
6 5
1
10
1
15
1 1
20
frequency, kHz
C
b Passband frequencyresponse
e Photograph of the measured frequency response illustrating both passband and
stopbaod operation
10 100 1000 10000
frequency.Hz
mode filter circuits. We will realise the current amplifiers
with the monolithic current conveyors described in the Fig. 20 Ideal and measured frequency response of current amplifer
last Section. By simply grounding the Y terminal of the based SAB circuit
current conveyor, a virtual ground is created at terminal 0 = Measured
- = Ideal
X from which current entering terminal X will be con-
veyed to terminal Z, thus realising a current amplifier.
Fig. 19a shows the well known Sallen and Key SAB ideal transfer function. As is evident, the measured results
filter circuit, and Fig. 19b shows the corresponding agree quite closely with the expected results.
current amplifier based filter circuit; see Reference 26. At
the present time, our lab is not equipped with a current 8 Conclusions
source generator or an oscilloscope with an accurate
current probe, so we had to improvise to measure the Although more than twenty years old, the current con-
transfer function of the circuit of Fig. 19b. By exploiting veyor appears to be an 'idea whose time has come'. This
the fact that a virtual ground exists at terminal X, one optimistic view is based on the growing interest in ana-
can inject current into this circuit by simply using a logue current-mode signal processing, the improved fully
voltage source and a series resistance. The output current integrated conveyor realisations and the vast literature
can be derived from the voltage across the resistor con- on the application of current conveyors.
86 IEE PROCEEDINGS, Vol. 137, Pt. G, No. 2, APRIL I990
9 Acknowledgments 12 SMITH, K.C., and SEDRA, AS.: ‘Realization of the Chua family of
new non-linear network elements using the current conveyor’, IEEE
Thanks are due to Kin Chan who has conducted a liter- Trans, 1970, CT-17, pp. 137-139
ature search that has uncovered over 100 papers on 13 SEDRA, AS.: ‘A new approach to active network synthesis’. PhD
Thesis, University of Toronto, Canada, 1969
current conveyors. This work was supported by NSERC 14 BLACK, G.G.A., FRIEDMANN, R.T., and SEDRA, A.S.: ‘Gyrator
and by the Information Technology Research Centre. implementation with integrable current conveyors’, IEEE J., 1976,
sc-6, pp. 395-399
15 WILSON, B.: ‘High performance current conveyor implementation’,
10 References Electron. Lett., 1984,20, (24), pp. S 9 9 1
16 TOUMAZOU, C., and LIDGEY, F.J.: ‘Accurate current follower’,
1 SMITH, K.C., and SEDRA, AS.: ‘Simple wideband linear voltage-
Electron. Wire. World, 1985,91, (1590). pp. 17-19
to-frequency converter’, Electron. Eng., 1968, pp. 1 4
17 TOUMAZOU, C., and LIDGEY, F.J.: ‘Floating-impedanceconver-
2 GILBERT, B.: ‘A new wide-band amplifier technique’, IEEE J.,
tors using current conveyors’, Electron. Lett., 1985, 21, (IS), pp.
1968, SC-3,pp. 353-365
-2
4 summary appeared in 1968 International Solid-state Circuits 18 KUMAR, U., and SHUKLA, S.K.: ‘Recent developments in current
Digest of Tech. Papers, pp. 116115, February 1968
3 WILSON, G.: ‘A monolithic junction FET-npn operational ampli- conveyors and their applications’, Microelectron. J . 1985, 16, pp.
47-52
fier’, IEEE J. 1968, SC-3,pp. 341-348
A summary appeared in 1968 International Solid-state Circuits 19 HUERTAS, J.L.: ‘Circuit implementation of current conveyor’,
Digest of Tech. Papers, February 1968 Electron. Lett., 1980, 16, (6). pp. 22S227
20 NISHIO, M., SATO, H., and SUZUKI, T.: ‘A gyrator constructed
4 SMITH, K.C., and SEDRA, A.S.: ‘The current conveyor-a new
circuit building block’, IEEE P r w . 1968.56. pp. 1368-1369 by CCII with variable current transfer ratio’. IEEE International
Symposium on Circuits and Systems Proceedings, 1985, pp. 93-96
5 BRUTON, L.T.: ‘RC-Active Circuits’ (Prentice-Hall, New Jersey,
1980) 21 GO”, F.: ‘CMOS current conveyors’. MASc Thesis, University of
6 SMITH, K.C., and SEDRA, A.S.: ‘A new simple wide-band current- Toronto, Canada, 1988
measuring device’, IEEE Trans. 1969, IM-18, pp. 125-128 22 HUIJSING, J.H., and DE KORTE, J. : ‘Monolithic nullor-a univer-
7 BRENNAN, B.L., VISWANATHAN, T.R., and HANSON, J.V.: sal active network element’, IEEE J., 1977, SC-12, pp. 5 9 4 4
‘The CMOS negative impedance converter’, IEEE J . 1988, SC-U, 23 HASLETT, J.W., RAO, M.K.N., and BRUTON, L.T.: ‘High-
(9,pp. 1273-1275 freauencv active filter desinn - using- monolithic nullors’, IEEE J .
8 FABRE, A., and ROCHEGUDE, P.: ‘Ultra lowdistortion current- 1960, SC-15, pp. 955-962
conversion technique’, Ekctron. Lett. 1984,20, (17). pp. 674676 24 NAIRN, D.G., and SALAMA, C.A.T.: ‘High-resolution current-
9 TEMES, G.C., and KI, W.H.: ‘Fast CMOS current amplifier and mode A/D convertors using active current mirrors’, Electron. Lett.,
buffer stage’, Electron. Lett. 1987. U ,(13). pp. 696497 1988,24, (21), pp. 1331-1332
10 GRAY, R., and MEYER, R.G.: ‘Analysis and design of analog inte- 25 WILSON, B.: ‘Constant bandwidth voltage amplification using
grated circuits’(Wiley, New York, 1984,Znd edn.) current conveyors’, Int. J. Electronics, 1988,aS. pp. 983-988
11 SEDRA, A.S., and SMITH, K.C.: ‘A second-generationcurrent con- 26 ROBERTS, G.W., and SEDRA, A.S.: ‘All-current-mode frequency
veyor and its applications’, IEEE Trans., 1970, CT-17, pp. 132-134 selective circuits’, Electron. Lett. 1989, U, (12), pp. 759-761