6.

Binary Arithmetic & ALUs

o Objectives
This section is concerned with the algorithms for binary
arithmetic operations and the logical networks used to
implement these operations. It will:
n Review
u The binary number code and the algorithms for addition and
subtraction of binary numbers.
u The sign-magnitude and two's complement number codes used for
representing negative numbers.
u The operation of simple ripple carry adders and subtractors.
n Show how addition can be speeded up using carry
lookahead techniques.
n Show how Verilog can be used to model arithmetic circuits.

Elec 326 6.1 Binary Arithmetic & ALUs

o Reading Assignment
n Much of this material was introduced in Elec 220.
n This material is also covered in Chapter 5, Number
Representations and Arithmetic Circuits, in Brown &
Vranesic.
n Appendix A of Brown & Vranesic has additional
information on the Verilog features covered in this chapter.

Elec 326 6.2 Binary Arithmetic & ALUs

6.1. Binary Arithmetic
o The Binary Number Code
n Example: Binary-to-Decimal Translation
X = 101101 (Base 2)
X = 1•25 + 0•24 + 1•23 + 1•22 + 0•21 + 1•20
= 1•32 + 0•16 + 1•8 + 1•4 + 0•2 + 1•1
= 32 + 0 + 8 + 4 + 0 + 1
= 45 (Base 10)
n Example: Decimal-to-Binary Translation
N = 23 (Base 10)
N = Q1•2 + N0 = 11•2 + 1 N0 = 1
Q1 = 11 = Q2 • 2 + N1 = 5 • 2 + 1 N1 = 1
Q2 = 5 = Q3 • 2 + N2 = 2 • 2 + 1 N2 = 1
Q3 = 2 = Q4 • 2 + N3 = 1 • 2 + 0 N3 = 0
Q4 = 1 = Q5 • 2 + N4 = 0 • 2 + 1 N4 = 1
N = 10111 (Base 2)

Elec 326 6.3 Binary Arithmetic & ALUs

o Arithmetic Operations
n Binary Addition
1 1 1 1 0 0 0 0 CARRY
0 0 1 1 1 1 0 0 X
0 1 0 1 1 0 1 0 Y
0 1 0 0 1 0 1 1 0 SUM

1 1 1 0 0 0 0 0 CARRY
1 1 0 1 0 1 0 0 X
1 0 1 1 0 0 1 0 Y
1 1 0 0 0 0 1 1 0 SUM

Elec 326 6.4 Binary Arithmetic & ALUs

 n Binary Subtraction

0 0 0 1 1 1 1 0 BORROW
1 1 0 1 1 0 0 0 X
0 1 0 0 1 1 0 1 Y
1 0 0 0 1 0 1 1 DIFFERENCE

1 0 0 0 1 1 1 0 0 BORROW
0 1 0 1 0 0 0 1 X
1 1 0 0 1 0 1 0 Y
1 0 0 0 0 1 1 1 DIFFERENCE

Elec 326 6.5 Binary Arithmetic & ALUs

 n Modulo Arithmetic (no carries)
000 000 000
111 0 001 111 0 001 111 0 001
7 1 7 1 7 1
+6
110 6 2 010 110 6 2 010 110 6 2 010
+2 +5
5 3 5 3 5 3
101 4 011 101 4 011 101 4 011
100 100 100
100 + 010 = 110 100+110 = 010 011 + 101 = 000

000 000 000

111 0 001 111 0 001 111 0 001
7 1 7 1 7 1
-6
110 6 2 010 110 6 2 010 110 6 2 010
+7 -4
5 3 5 3 5 3
101 4 011 101 4 011 101 4 011
100 100 100
111 + 111 = 110 110 - 100 = 010 100 - 110 = 110

000 000
111 0 001 111 0 001
7 1 7 1

110 6 -4 2 010 110 6 -7 2 010

5 3 5 3
101 4 011 101 4 011
100 100
100 - 100 = 000 000 - 111 = 001

Elec 326 6.6 Binary Arithmetic & ALUs

 n Comments on transitions through zero
u An addition that causes a transition up to or through 0 is called an
overflow.
u A subtraction that causes a transition through 0 is called an
underflow.
u For positive integers, overflows and underflows are errors.

Elec 326 6.7 Binary Arithmetic & ALUs

o Negative Numbers
n Sign-Magnitude Representation
u Most significant bit is used as the sign bit (0 = plus, 1 = negative).
For example, +5 = 0101, -5 = 1101
u Two representations of zero (000...00 and 100...00)
u Addition involves several tests and is relatively difficult to
implement in hardware.
u Used in floating point

Elec 326 6.8 Binary Arithmetic & ALUs

 n Two's Complement Representation
u Divide binary numbers into two equal subsets and assign one to
represent positive integers and the other for negative numbers
0000
1111 0001
1110 -1 0 1 0010
-2 2
1101 -3 3 0011
1100 -4 + 4
0100
-5 - 5
1011 0101
-6 6
1010 -7 -8 7 0110
1001 0111
1000

u Note that there is only one representation of zero

u The most significant bit can be treated as a sign bit (although the
rest of the word is not the magnitude of negative numbers)
u Rotations around the circle works the same way as with positive
integers: Addition - clockwise, Subtraction - counter clockwise
u There are two ways to subtract a positive number y from another
number x of either sign:
l Move CCW y steps from x.
l Move CW 2n - y steps from x

Elec 326 6.9 Binary Arithmetic & ALUs

 n Two's Complement of an n-bit number
u Definition: If y is an n-bit binary number, then 2n - y is called the
two's complement of y and denoted y*.
l For example: n = 4, y = 0011, y* = 10000 - 0011 = 1101
l Note: y + y* = y + 2n - y = 2n = 0
l Hence y* represents -y.
u Forming the two's complement of a binary number
l 2n = 11...11 + 00...01, where both binary numbers are n bits.
l y* = 2n - y = (11...11 + 00...01) -y = (11...11 - y) + 00...01
l 11...11 - y = y', the bitwise complement of y
l y* = y' + 00...01
l To find the two's complement of y, flip all the bits of y and add 1
l Note that 0* = 0
u Sign Extensions: To convert an m bit number to an n-bit number
where m>n, pad on the left with the sign bit
l 0011 -- 00000011 +3
l 1011 -- 11111011 -5

Elec 326 6.10 Binary Arithmetic & ALUs

 n Two's Complement Addition
u Two's complement addition is just addition modulo 2n
+2 0010 +2 0010
+3 0011 -3 1101
+5 0101 -1 1111
1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010 1110 -1 0 1 0010
-2 2 -2 2
1101 0011 1101 0011
-3 3 -3 3
1100 -4 2+3 4 0100 1100 -4 4 0100
2-3
-5 5 -5 5
1011 -6 6 0101 1011 -6 6 0101
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000 1000

-2 1110 -2 1110
+6 0110 -5 1011
+4 0100 -7 1001
1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010 1110 -1 0 1 0010
-2 2 -2 2
1101 0011 1101 0011
-3 3 -3 3
-2+6
1100 -4 4 0100 1100 -4 -2-5 4 0100
-5 5 -5 5
1011 -6 6 0101 1011 -6 6 0101
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000 1000

Elec 326 6.11 Binary Arithmetic & ALUs

 u Note that in the third and fourth examples, the addition resulted in
movement through zero, but it did not produce an incorrect sum.
Thus movement through zero is not an error for two's complement
addition.
u However, it is possible to produce an error, either a sum that is too
big or too small to represent in the number of bits available.
u Overflow and Underflow:
l Adding two numbers with different signs can never produce an overflow or
underflow.
l Adding two positive numbers produces an overflow if the sign of the result is
negative.
l Adding two negative numbers produces an underflow if the sign of the result is
positive.
+7 0111 -7 1001
+6 0110 -4 1100
+13 1101 -11 0101
1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010 1110 -1 0 1 0010
-2 2 -2 2
1101 0011 1101 0011
-3 3 -3 3
1100 -4 4 0100 1100 -4 4 0100
+7+6 -7-4
-5 5 -5 5
1011 -6 6 0101 1011 -6 6 0101
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000 1000

l Note that in one case there is a carry out and in the other there is not
Elec 326 6.12 Binary Arithmetic & ALUs
 n Two's Complement Subtraction
u Add the two's complement of the subtrahend to the minuend.

+4 0100 0100 +3 0011 0011

-(+3) -0011 1101 -(+4) -0100 1100
+1 0001 -1 1111
1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010 1110
-2 2 -1 0 1 0010
1101 0011 -2 2
-3 3 1101 0011
-3 3
1100 -4 4 0100 1100 -4 4 0100
+4-(+3) +3-(+4)
-5 5 -5 5
1011 -6 6 0101 1011 0101
-7 -8 7 -6 6
1010 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000 1000

+3 0011 0011 -3 1101 1101

-(-4) -1100 0100 -(-4) -1100 0100
+7 0111 +1 0001
1111 0000 0001 1111 0000 0001
1110 1110 -1 0 1 0010
-1 0 1 0010
-2 2
-2 2 1101 0011
1101 0011 -3 3
-3 3 -3-(-4)
1100 -4 4 0100 1100 -4 4 0100
+3-(-4)
-5 5 -5 5
1011 0101 1011 -6 6 0101
-6 6
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000

Elec 326 6.13 Binary Arithmetic & ALUs

 u Overflow and Underflow:
l Subtracting two numbers with the same signs can never produce an overflow
or underflow.
l Subtracting a negative number from a positive number produces an overflow if
the sign of the result is negative.
l Subtracting a positive number from a negative number produces an underflow
if the sign of the result is positive.

+4 0100 0100 -4 1100 1100

-(-5) -1011 0101 -(+5) -0101 1011
+9 1001 -9 0111
1111 0000 0001 1111 0000 0001
1110 -1 0 1 0010 1110
-2 2 -1 0 1 0010
1101 0011 -2 2
-3 3 1101 0011
-3 3
1100 -4 4 0100 1100 -4 -4-(+5) 4 0100
+4-(-5)
-5 5 -5 5
1011 -6 6 0101 1011 0101
-6 6
1010 -7 -8 7 0110 1010 -7 -8 7 0110
1001 0111 1001 0111
1000 1000

Elec 326 6.14 Binary Arithmetic & ALUs

6.2. Arithmetic Operations in Verilog
o Numbers in Verilog
n Binary numbers can be represented by an expression of the
following form: <length>’<radix> <digits>, where
u <length> is the number of bits in the number; it is optional.
u <radix> denotes the radix of the representation.
l b - binary, o - octal, h - hex, d - decimal
u <digits> is a sequence of digits in the indicated radix.
n Examples:
u 12’b100010101001
u 12’o4251
u 12’h8A9
u 12d2217

Elec 326 6.15 Binary Arithmetic & ALUs

 n Negative numbers are written with a minus sign in the front.
u Verilog represents a negative number as the two’s complement of
the unsigned binary number.
l For example -4’b0110 = 4’b1010 and -8’d12 = -8’b00011000 = 8b11101000
n The length may exceed the number of bits needed to
represent the number.
u In this case the bits are padded on the left to get the specified length.
n The length may be less the the number of bits needed to
represent the number.
u In this case the high order bits are truncated.
n Underscore symbols may be used to improve readability.
u For example 8’b000110001100 = 8’b0001_1000_1100
n It is also possible to use the symbols x or z in addition to 0
and 1 in any bit position.

Elec 326 6.16 Binary Arithmetic & ALUs

o Vectors in Verilog
n A vector in Verilog is a finite, ordered list of bits. The
length of the vector is the number of bits it contains.
n Vectors are declared in Verilog in the following way:
input [3:0] W; //W is a 4-bit input signal, where bit 0 is the right-
!!!!!!!!!!!!!!!!!!!!!//most bit and bit 3 is the left-most bit
output [1:8] SUM; //SUM is an 8-bit output signal, where bit 1 is the
!!!!!!!!!!!!!!!!!!!!!!!!!!!!//left-most bit and bit 8 is the right-most bit
wire [3:1] A, B; //A and B are 3-bit internal signals (i.e., wires), with
!!!!!!!!!!!!!!!!!!!!!!!//bit 1 on the right and bit 3 on the left
n The range of the vector is specified as [Ra:Rb] where
u Ra and Rb are integers that specify the left and right indices of the
vector
u Ra can be > Rb, or Ra can be < Rb.
u Ra or Rb can be positive or negative

Elec 326 6.17 Binary Arithmetic & ALUs

 n Making smaller vectors from bigger vectors
u The i-th bit of a vector W may be specified as W[i].
l If i is not in the range of W, then W[i] has value x (undefined).
l The index i can be a variable (of type integer) or a constant.
u A sub-vector of a vector W can be specified as W[ra:rb], where ra
and rb specify a sub-range of the range of W.
l For example, if W is declared as “wire [1:8] W;” then W[3:6] is a 4-bit sub-
vector of W consisting of bits 3, 4, 5, and 6.
l The sub-range must be specified with two integer constants, not variables.
n Making bigger vectors from smaller vectors
u The concatenation operator { , } can be used to combine two or
more vectors.
l {W,Y} is a vector obtained by writing the bits of W followed by the bits of Y.
l For example if W = b1001 and Y = b011, then {W,Y} = b1001011
u The replication operator n{W} produced a vector consisting of n
concatenated copies of the vector W.

Elec 326 6.18 Binary Arithmetic & ALUs

 n Exercise
wire [3:0] W, Y;
wire [1:7] X;
Let W = 4’b1101, Y = 4’b0101 and X = 7’b1100101
u Evaluate the following:
W[2] = b1
Y[1] = b0
X[0] = bx
X[3: 5] = b001
{W,Y} = b11010101
{X[6:7], W[3:1] } = b01110
3{Y[1:0]} = b010101

Elec 326 6.19 Binary Arithmetic & ALUs

o Binary numbers in Verilog
n Vectors in Verilog may be used to represent binary
numbers in the obvious way.
u It is the position, not the index, of a bit that determines its
significance in the number. That is
l The left-most bit is the most significant bit of the number.
l The right-most bit is the least significant bit of the number.
n Arithmetic operations
u Addition and Subtraction of vectors
l Adds or subtracts the vectors as if they were unsigned binary numbers
l The length of the sum or difference is equal the length of the longest operand.
l If the lengths of the operands are not equal, the shorter one is padded on the left
with 0’s.
l Examples:
t If A = 1011b0, B = b0110 and C = b10001, then
t A + B = b11100
t A - C = b00101
t C - B = b01011
t B - C = b10101

Elec 326 6.20 Binary Arithmetic & ALUs

 n To obtain the carry out of an addition the operands must be
extended as follows:
u Let A and B be 8 bit vectors.
u Then {1’b0, A} + {1’b0, B} is a 9-bit sum of A and B where the
left-most bit is the carry out of the low order 8 bits.
n Adding negative binary numbers (in two’s complement
notation) of unequal length.
u The shorter number must be padded with the number’s sign bit
u If A = 8’b0100_1010, B = 4’0110, and C = 4’1001 where all are
supposed to represent two’s complement numbers, then B must be
padded with 0’s and C must be padded with 1’s if they are added to
A.
A + {4{B[3], B} = 8’b0100_1010 + 8’b0000_0110
A + {4{C[3], C} = 8’b0100_1010 + 8’b1111_1001

Elec 326 6.21 Binary Arithmetic & ALUs

 n Vector assignment statements.
wire [3:0] X, Y, S;
assign S = X + Y;
u The sizes of the vectors on the right side of the assignment are
adjusted (padded with 0 or truncated) to the size of the result
vector on the left side.
wire [3:0] X, Y;
wire [4:0] S;
assign S = X + Y; //same as S = {1’b0, X} + {1’b0, Y}
u Concatenation can also be used on the left side of the assignment
wire [3:0] X, Y, S;
wire carryout;
assign {carryout, S} = X + Y; //X and Y padded with one 0

Elec 326 6.22 Binary Arithmetic & ALUs

6.3. Arithmetic Circuits
o Full Adders CI B A S CO
S A
B A 0 0 0 0 0 0 1 0 1
0 0 1 1 0 CI 1 0 1 0
0 1 0 1 0 B
FA 0 1 1 0 1 CO
CO CI 1 0 0 1 0 A
1 0 1 0 1 0 0 1 0
1 1 0 0 1 CI 0 1 1 1
S 1 1 1 1 1 B

S = A'•B'•C + A•B'•CI' + A•B•CI + A'•B•CI'

A
= B'•(A'•CI + A•CI') + B•(A•CI + A'•CI') B S
= B'•(A⊕CI) + B•(A⊕CI)' CI

= B⊕(A⊕CI)
= A⊕B⊕CI CO
CO = A•CI + B•CI + A•B = MAJ(A, B, CI)

Elec 326 6.23 Binary Arithmetic & ALUs

 n Verilog representation of a full adder:
u A structural specification:
module fulladd(Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;

xor(s, x, y, Cin);
and(z1, x, y);
and(z2, x, Cin);
and(z3, y, Cin);
or(Cout, z1, z2, z3);
endmodule
l Altera software does not support xor gate module. How would you get around that
limitation?
u A behavioral specification:
module fulladd(Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule

Elec 326 6.24 Binary Arithmetic & ALUs

 u A simpler behavior specification

module fulladd (Cin, x, y, s, Cout);

input Cin, x, y;
output s, Cout;
reg s, Cout;

always @(x or y or Cin)

{Cout, s} = x + y + Cin;

endmodule

Elec 326 6.25 Binary Arithmetic & ALUs

o Ripple Carry Adders
B A
B3 A3 B2 A2 B1 A1 B0 A0
n n

CO ADDER CI
CO FA FA FA FA CI

n
S3 S2 S1 S0 S

n Worst case delay occurs when there is a carry that must

propagate from stage 0 to stage n-1 (or from CI to CO)
u Let tCICO be the delay from CI to CO on a single FA
u Then the worst case delay is given by

tADD = n¥tCICO

Elec 326 6.26 Binary Arithmetic & ALUs

 n Verilog representation of a 4-bit ripple carry adder
u A structural specification using the previous fulladd module
module adder4(carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;

fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);

fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage0 (C[3], X[3], Y[3], S[3], carryout);

endmodule

l Comment: the specification of fulladd can be included in the same file as the
adder4 or in a different one if its location is known

Elec 326 6.27 Binary Arithmetic & ALUs

 n Generic Specifications
u Allows the specification of module whose size can be specified by a
parameter (e.g., the number of bits in a ripple carry adder).
u Parameters are defined in Verilog statements of the following type:

parameter n = 4;

u Then vectors of length can be defined as follows:

wire [n-1:0] W

u An example of the use of generic specifications is the n-bit adder

given on the following page.
l n is determined by the parameter statement (32 in the example).
l k is an integer that is used as the index variable of a for loop, and it does not
correspond to a physical connection in the module.

Elec 326 6.28 Binary Arithmetic & ALUs

 module addern (carryin, X, Y, S, carryout);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout;
reg [n-1:0] S;
reg carryout;
reg [n:0] C;
integer k;

always @(X or Y or carryin)

begin
C[0] = carryin;
for (k=0; k<n; k=k+1)
begin
S[k]=X[k]^Y[k]^C[k];
C[k+1] = (X[k]&Y[k])|(X[k]&C[k])|(Y[k]&C[k]);
end
carryout = C[n];
end

endmodule

Elec 326 6.29 Binary Arithmetic & ALUs

 n A ripple carry adder with carry out and overflow:
module addern (carryin, X, Y, S, carryout, overflow);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output [n-1:0] S;
output carryout, overflow;
reg [n-1:0] S;
reg carryout, overflow;

always @(X or Y or carryin)

begin
{carryout, S} = X + Y + carryin;
overflow = (~X[n-1]&~Y[n-1]&S[n-1]) | (X[n-1]&Y[n-1]&~S[n-1]);
end
endmodule

Elec 326 6.30 Binary Arithmetic & ALUs

o Subtractors
n Convert an adder into a subtractor by inverting the
subtrahend and setting the CI to 1.
A

NOT n
B

...
n n
NOT

CO ADDER 1 n

n
D

n A combined adder/subtractor: Add if A/S =0, Sub if A/S =1

XOR
B
n n n

CO ADDER A/S XOR ...

n
n
S/D

Elec 326 6.31 Binary Arithmetic & ALUs

o Carry Look Ahead Techniques

FA
M
M

FA M
M

FA M
M

FA M
M

Carry Sum
Generation Generation

Elec 326 6.32 Binary Arithmetic & ALUs

 C0 = C 0

C1 = A0•B0+A0•C0+B0•C0
= A0•B0+(A0+B0)•C0
M

C2 = A 1•B1+A1•C1+B1•C1
= A1•B1+(A 1+B1)•(A0•B0+(A0+B0)•C0)
M = A1•B1+(A 1+B1)•A0•B0+(A1+B1)•(A0+B0)•C0

C3 = A2•B2+A2•C2+B2•C2
= A2•B2+(A 2+B2)•(A1•B1+(A1+B1)•A0•B0+(A1+B1)•(A0+B0)•C0)
M = A2•B2+(A2+B2)•A1•B1+(A2+B2)•(A1+B1)•A0•B0+
(A2+B2)•(A1+B1)•(A0+B0)•C0
Carry
Generation

Elec 326 6.33 Binary Arithmetic & ALUs

 n Carry Generate and Propagate
G i = Xi • Y i Pi = Xi + Yi Ci+1 = Gi + Pi•Ci

C1 = G0 + P0 • C0
C2 = G1 + P1 • C1 = G1 + P1 •(G0 + P0 • C0)
= G1 + P1 • G0 + P1 • P0 • C0
C3 = G2 + P2 • C2 = G2 + P2 •(G1 + P1 • G0 + P1 • P0 • C0)
= G2 + P2 • G1 + P2 • P1 • G0 + P2 • P1 • P0 • C0
C4 = G3 + P3 • C2
= G3 + P3 •(G2 + P2 • G1 + P2 • P1 • G0 + P2 • P1 • P0 • C0)
= G3 + P3 • G2 + P3 • P2 • G1 + P3 • P2 • P1 • G0 + P3 • P2 • P1 • P0 • C0
= G + P • C0
where G = G3 + P3 • G2 + P3 • P2 • G1 + P3 • P2 • P1 • G0
and P = P3 • P2 • P1 • P0

u Note that this expression has only three levels of delay for all i.
u Note also that the number of variables in the product term grows
with i.
u These equations are used to define carry look ahead logic as
illustrated in the following figures.

Elec 326 6.34 Binary Arithmetic & ALUs

 n Adder with carry look ahead
CI C
C
C0 A S
X0 A B
ADD1 S0 ADD1 S
Y0
B
P0 G0

C1 P G
P G
X1
ADD1 S1
Y1
Carry
P1 G1
Look
Ahead u The 74S182 is a commercial CLA chip
Logic C2
X2
ADD1 S2
u These carry look ahead networks can be
Y2
P2 G2
connected to extend the technique to
more than four bits in the following way.
C3
X3
ADD1 S3
Y3
P3 G3

P G

Elec 326 6.35 Binary Arithmetic & ALUs

 n Tree-Structured Carry Look Ahead Adder

CLA

CLA CLA CLA CLA

FA FA FA FA FA FA FA FA

Elec 326 6.36 Binary Arithmetic & ALUs

 6.4. Tips & Tricks
o Form the two's complement by inverting the bits and adding 1.
o Alternatively form the two’s complement by scanning the
number from right to left, skipping zero’s and the first 1, and
then toggling the remaining bits.
o Perform subtraction by adding the two's complement of the
subtrahend.

6.5. Pitfalls
o Viewing the carry out as an overflow/underflow for two's
complement addition/subtraction.

Elec 326 6.37 Binary Arithmetic & ALUs

6.6. Review
o The relationship between carry out and overflow
signals in two’s complement addition and subtraction.
o The relative advantages of sign magnitude vs. two’s
complement addition and subtraction.
o The limits on the time to perform addition and how to
achieve them
o Verilog features;
n Constant numbers
n Vectors & vector operations
n Arithmetic operations
u Vectors of different lengths
n Generic specifications

Elec 326 6.38 Binary Arithmetic & ALUs