3250
12, DECEMBER 2010
Comparative Study of FinFET Versus Quasi-Planar
HTI MOSFET for Ultimate Scalability
Reinaldo A. Vega, Member, IEEE, and Tsu-Jae King Liu, Fellow, IEEE
Abstract—The FinFET is compared against the quasi-planar
trigate bulk MOSFET with high-permittivity (high-k) dielectric
trench isolation (HTI MOSFET) for low-standby-power applica-
tions, at dimensions near the end-of-roadmap (11-nm half-pitch).
It is found that the optimal transistor structure depends on the
fin aspect ratio (AR) and the HTI dielectric constant εHTI : for
sufficiently high εHTI , the HTI MOSFET can provide comparable
or lower delay as the FinFET, for AR up to ∼2.5. Thus, the
development of high-k dielectric and/or high-AR fin formation
technologies will ultimately determine which transistor design is
more advantageous.
Index Terms—Band-to-band tunneling (BTBT), fin field-effect
transistor (FinFET), high permittivity (high-k), scalability.
I. I NTRODUCTION
A MOSFET scaling progresses, short-channel effects be-
come more significant so that it is increasingly difficult
to effectively turn the transistor off. This problem is exacer-
bated in the sub-10-nm gate length (LG ) regime, where direct
source-to-drain tunneling (DSDT) adds to thermal OFF-state
leakage current [1]–[4]. The challenge of achieving a low
OFF-state current IOFF while maintaining a required level of
ON -state performance is particularly difficult for low-standby-
power (LSTP) MOSFETs, because the IOFF specification is
only slightly higher than the leakage floor Imin , which is largely
defined by band-to-band tunneling (BTBT) current.
An optimally designed FinFET structure can have lower
BTBT current than the conventional planar bulk MOSFET
structure; its scalability down to below 5-nm LG has been
demonstrated via modeling and experiments [1]–[3], [5]–[7].
For a FinFET to have good electrostatic integrity, however, its
body thickness tbody —i.e., the fin width—generally must be
smaller than LG /1.4 [8]. In addition, fins with high aspect ratios
(ARs) are required to achieve good layout efficiency. These
requirements present significant manufacturing challenges, not
only for fin formation but also for gate-electrode and gate-
sidewall-spacer formation. In general, any nonplanar transistor
structure presents new manufacturing challenges. For example,
Manuscript received June 14, 2010; revised August 12, 2010; accepted
September 6, 2010. Date of publication October 4, 2010; date of current version
November 19, 2010. This work was supported in part by the Semiconductor Re-
search Corporation under Contract 2007-VJ-1631 and in part by an IBM/Global
Research Corporation Fellowship. The review of this paper was arranged by
Editor G. Jeong.
R. A. Vega was with the Department of Electrical Engineering and Computer
Science, University of California, Berkeley, CA 94720 USA. He is now with the
IBM Semiconductor Research and Development Center, Hopewell Junction,
NY 12533 USA (e-mail: rvega@us.ibm.com).
T.-J. King Liu is with the Department of Electrical Engineering and Com-
puter Science, University of California, Berkeley, CA 94720 USA.
Digital Object Identifier 10.1109/TED.2010.2077297
0018-9383/$26.00 © 2010 IEEE
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO.
the gate-all-around MOSFET [9] requires an undercut etch
to pattern the gate electrode around the entire nanowire/beam
channel region to minimize the parasitic gate-to-drain capac-
itance CGD , which can result in LG variation around the
channel region. Nanowire diameter control, pitch scaling, and
agglomeration are additional process integration issues [10].
The ideal MOSFET structure for aggressive scaling should
not only have electrostatic integrity comparable with the
FinFET (or any other multigate transistor structure) but also
retain the relative ease of manufacture of a conventional pla-
nar bulk MOSFET. Such a structure was proposed in [11],
wherein a low-AR (quasi-planar) trigate (TG) structure is com-
bined with high-permittivity (high-k) dielectric trench isolation
(HTI), and is henceforth referred to as the HTI MOSFET. The
HTI regions provide for strong gate coupling to the channel
region sidewalls, achieving the effect of a larger AR device,
such as a FinFET, without the manufacturing complications.
This also permits the elimination of the deep source/drain
regions and the use of a recessed retrograde well (RRW), which
together reduce Imin to an acceptable level for LSTP design
at scales much smaller than previously projected for planar
bulk technology [12]. A similar structure has also been recently
proposed, whereby the trenches are filled with a poly-Si gate
stack rather than a high-k dielectric [13]; although this achieves
a similar effect, it comes at the cost of very high CGD , since
the gate trench entirely overlaps the sidewalls of the active
region, including the source/drain regions. The HTI MOSFET
does not have this problem; in fact, it is shown herein that CGD
comprises a smaller fraction of the total gate capacitance CGG
in an HTI MOSFET than in a FinFET, which is a unique feature
of the HTI structure.
In this paper, an analysis of the HTI MOSFET is performed
in consideration of LSTP performance specifications for end-
of-roadmap transistor dimensions [12]. Its DC and AC perfor-
mance is compared against that of the FinFET via 3-D device
simulations using Sentaurus Device [14]. In Section II, the
device structures and modeling setup are defined. Section III
discusses the modeling results, and Section IV concludes this
paper.
II. M ODELING S ETUP
A. Device Structures
The HTI MOSFET and FinFET (both n-channel) structures
modeled in this paper are shown in Fig. 1(a) and (b), respec-
tively. Fig. 2 shows the across- and along-channel cross sections
for the HTI MOSFET. The gate pitch (GP) is constrained to
22 nm, within which the gate electrode, gate-sidewall spacers
VEGA AND KING LIU: COMPARATIVE STUDY OF FinFET VERSUS HTI MOSFET
Fig. 1. Three-dimensional view of the (a) bulk HTI MOSFET and (b) FinFET
structures modeled in this paper. The HTI regions, sidewall spacers, and silicide
contacts are translucent in both images, whereas the gate electrode is not shown
to allow the channel region to be seen.
Fig. 2. (a) Across-channel and (b) along-channel 2-D cross sections of the
HTI MOSFET.
(with length Lsp,total ), and source/drain regions (with length
LSD ) must fit. Thus, GP = LG + 2 ∗ (Lsp,total + LSD ). In
light of the results in [11] for optimal HTI width, the active
pitch (AP)—which is the sum of the active region width and
the lateral gate stack “height” on both sides of the device—is
constrained to be 20 nm.
For both structures, the gate dielectric is SiO2 (tox = 1 nm),
and dual-layer gate-sidewall spacers are utilized; the inner
spacer is high-k (εsp,hk = 23) with length Lsp,hk , and the
outer spacer is low-k (SiO2 , εsp,lk = 3.9) with length Lsp,lk .
This spacer design, as compared with a pure high-k spacer
design, was shown in [1] to provide for a more scalable double-
gate MOSFET structure: the high-k inner spacer beneficially
3251
increases gate-sidewall gating of the device, whereas the low-k
outer spacer reduces silicide gating of the source/drain exten-
sion (SDE) regions [1], [15].
Selective epitaxial growth to laterally and vertically increase
the thickness of the source/drain contact regions for reduced
series resistance is assumed. Silicidation is assumed to consume
a portion of the silicon in these raised-source/drain (RSD)
regions, so that the silicide/silicon interfaces end up being
coplanar with the top of the channel region. (If the RSD
regions were further silicided, then there would be increased
ambipolar leakage due to tunneling through the SDE regions
[16].) The silicide material has a workfunction φM = 4.7 eV.
The silicide-to-silicon contacts are assumed to have a specific
contact resistivity value of 1 × 10−9 Ω · cm2 in light of the
analysis performed in [17] and the possibility of achieving zero
or near-zero barrier contacts, as demonstrated in [18]. Since the
device dimensions are so small, it is assumed for simplicity that
the silicide and the contact are merged into a single structure
and that the silicide can be made arbitrarily narrow (i.e., grain
size limitations are ignored).
It should be noted that, for the HTI MOSFET, the height
of the HTI region, i.e., THTI , is large (40 nm) compared with
the width of the active region, i.e., Wstripe , so that the active
region has a high AR. In practice, the HTI would be shorter
(comparable with TSi ), and the bulk silicon substrate would
lie underneath it. The structure in Fig. 1(a) is modeled here to
improve simulation convergence (by eliminating corner effects
at the bottom of the HTI regions) while keeping the body
contact far enough from the drain-body depletion region to
prevent a drain-to-substrate short. This increases CGG ; thus, the
intrinsic delay is overestimated for the HTI MOSFET.
Both the HTI MOSFET and FinFET designs were optimized
through extensive technology computer-aided design (TCAD)
simulation. For the HTI MOSFET, LG = Wstripe , TRSD =
Hstripe , TSi = 9 nm, and Tgate = 15 nm. The default value
for the HTI dielectric constant εHTI is 23, corresponding to
HfO2 . The substrate doping is uniform at 4 × 1018 cm−3 for
depths below TSi and decays vertically toward the channel
surface with a Gaussian profile of decay length LRRW = 4 nm,
which corresponds to the distance over which the doping drops
by one decade. For the FinFET, the fin width Wfin is 3 nm,
and the default value of the fin height Hfin is 9 nm. The
p-type body is uniformly doped at 1 × 1015 cm−3 . The gate (of
thickness Tgate = 15 nm) wraps around the top and sidewall
surfaces of the fin to form a TG FinFET. For both structures,
the doping within the RSD regions is uniform at 1 × 1020 cm−3
and decays into the SDE regions as a Gaussian with decay
length LSDE = 2 nm. Cooptimization of the sidewall spacer
widths with LSDE yields Lsp,lk = 2 nm and Lsp,hk = 4 nm
(hence, Lsp,total = 6 nm). LG and LSD are varied together
(due to the GP constraint) to find the design that yields the
best drive current ION and intrinsic delay CGG ∗ VDD /ION for
supply voltage VDD = 0.7 V and IOFF = 29 pA/μm, following
LSTP specifications in the 2007 Edition of the International
Technology Roadmap for Semiconductors, at the 11-nm node.
Gate work function engineering is used for threshold voltage
adjustment. In the FinFET, LG is varied from 2 to 8 nm,
whereas in the HTI MOSFET, LG is varied from 3 to 8 nm.
3252 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010

(This is because LG = Wstripe for the HTI MOSFET, and the

lower limit for Wstripe is Wfin = 3 nm). For the p-channel
MOSFETs that will be modeled later in this paper to investigate
inverter switching delay, the device geometries and doping
profiles are the same as for the optimized n-channel MOSFETs,
except that opposite-type dopants are used.
It should be noted that the FinFET structure modeled in this
paper does not have a buried oxide (BOX) layer underneath it,
so that parasitic drain-to-substrate and gate-to-substrate capac-
itance, as well as the effect of drain-to-fin fringing electric field
through the BOX, are ignored. This means that the performance
of the FinFET is overestimated, so that any design space that
is shown to be advantageous for the HTI MOSFET herein is Fig. 3. Schematic cross section of the HTI MOSFET across the channel
region, zoomed in to show one side of the device only.
actually a conservative estimate.
neither one can be used to compare the HTI MOSFET with the
B. Physical Models and Assumptions FinFET, because the effective channel width Weff of an HTI
MOSFET is larger than Wstripe + 2 ∗ Hstripe due to capacitive
For the purpose of determining whether quasi-planar
coupling between the gate and the channel region sidewalls
MOSFETs can possibly achieve performance on par with
through the HTI. To calculate the effective additional channel
FinFETs at ultimately small scales, a basic set of physical
width due to gate fringing fields, the capacitance CHTI between
models is used in the device simulations. Carrier transport is
the gate and the channel region sidewalls through the HTI
modeled using drift–diffusion formulations with doping- and
is first calculated. Then, the ratio of CHTI to the gate-oxide
field-dependent mobility models, as in [15], and using a new
capacitance is multiplied by WHTI . (Note that WHTI is assumed
thin-film mobility model [14], which accounts for reduced
to be less than THTI , so that the gate coupling to the channel
mobility in ultrathin body regions. No strain-induced mobility
region sidewalls can be approximated to stop at a depth WHTI
enhancement (due to embedded source/drain stressors, contact
below the HTI surface.) Here, CHTI is approximated, since
etch stop liners, shallow trench isolation proximity effects,
inversion-layer quantization (and the nonuniformity thereof
etc.) is assumed. Velocity overshoot is ignored because of the
due to the nonuniform body doping profile)—which would
arguments put forth in [1] and also because the hydrodynamic
reduce CHTI —is not accounted for. Nevertheless, the derivation
transport model [14] would need to be calibrated against Monte
presented herein permits a much closer approximation of the
Carlo simulations—which can only be used for 2-D device
electrical channel width than the other normalization schemes
structures and, hence, cannot account for corner effects.
mentioned above, and any effect due to quantization can be
Carrier quantization is modeled in all structures using the
simplistically reflected in a lower value for εHTI .
modified local density approximation rather than the presum-
CHTI is composed of two components: 1) the capacitance
ably more accurate density gradient model (DGM) [14]. This is
along the HTI surface CA and 2) the capacitance at the gate-
because the DGM was found to give erroneous results for the
oxide-to-HTI junction, CB (Fig. 3). To determine CA , the
inversion carrier distribution along the channel region sidewalls
gate fringing field path through the HTI is assumed to follow
below the HTI surface, specifically with the peak carrier con-
a quarter-circle, as illustrated by the dark arrows within the
centration along the sidewalls as in a classical solution. (Tighter
HTI region in Fig. 3. This capacitance is integrated across the
meshing did not solve this problem.)
“width” of the capacitor, from tox to WHTI , i.e.,
Since the HTI MOSFET can achieve Imin < IOFF over a
wide design space [11] and the FinFET has a lightly doped HTI
W  
2εHTI dr 2εHTI WHTI
body region, BTBT is not modeled to minimize convergence CA = = ln . (1)
issues. The different gate geometries for the FinFET and the π r π tox
tox
HTI MOSFET may result in vastly different gate leakage. Since
the HTI structure relies in part upon fringing electric fields to To determine CB , some approximation is required because
gate the channel region, its gate leakage cannot be accurately the width of the capacitive plate along the channel region
modeled with current TCAD software, which can only model sidewall is equal to tox , but at the gate-oxide-to-HTI junction,
gate tunneling leakage along a 1-D noncurved path. Therefore, the width is effectively zero. The fringing field lines from this
gate leakage is assumed to be negligible herein, for the sake of corner region perpendicularly run to the gate-oxide interface
simplicity. and change to a quarter-circle path along the channel region
sidewall, so that the field strength nonlinearly drops along the
channel region sidewall. If tox is small, the fringing field lines
C. HTI MOSFET Current Normalization
can be approximated to be linear over the entire region, so
In [11], two current normalization schemes were proposed that the triangular approximation can be used to determine CB .
for the HTI MOSFET, whereby ION is normalized either to Assuming that the normalized capacitance C/CB is equal to 1
the stripe pitch or to Wstripe + 2 ∗ Hstripe . Either one can be for the shortest path length and 2/π for the longest path length,
used to compare different HTI MOSFET designs; however, CB is found using (2). Then, CHTI is found using (3), with Cox
VEGA AND KING LIU: COMPARATIVE STUDY OF FinFET VERSUS HTI MOSFET 3253

expressed in (4). Weff is found using (5) and is used henceforth

to normalize IDS for the HTI MOSFET. Although it is not
shown here, the value of Weff that is calculated using (5) closely
matches TCAD results for the total width of the inversion layer
with carrier concentration above 1 × 1019 cm−3 , for VGS =
1.5 V and VDS = 0 V (gate workfunction = 4.7 eV), over the
entire range of εHTI values used in this paper. This affirms
the validity of the approximations used herein, as shown in the
following equations:
   
εHTI tox 2 εHTI 2
CB = ∗ ∗ 1− = 1− (2)
tox 2 π 2 π
   
εHTI 2 2εHTI WHTI
CHTI = CA +CB = 1− + ln (3)
2 π π tox
εox
Cox = (Wstripe + 2 ∗ Hstripe ) (4)
tox
  
CHTI
Weff = Wstripe + 2 Hstripe + WHTI . (5)
Cox

III. M ODELING R ESULTS

A. Drive Current and Intrinsic Delay
Fig. 4(a) and (b) compares normalized and raw ION
versus LG , respectively, for the FinFET, HTI MOSFET,
HTI-DT MOSFET, (explained below), and also a quasi-planar
TG bulk MOSFET with conventional SiO2 dielectric isolation
(henceforth referred to as conventional TG (CTG) MOSFET).
Interestingly, ION /Weff is lower, although raw ION is higher
for the HTI MOSFET compared with the CTG MOSFET. This
is consistent with the smaller improvement in optimal intrinsic
delay (11%) shown in Fig. 5 compared with the improvement
in optimal ION (33%) shown in Fig. 4(b). In addition, ION Fig. 4. Comparison of (a) normalized drive current and (b) raw drive current
versus gate length for the FinFET, CTG, and HTI MOSFET structures.
more sharply drops with decreasing LG for the HTI MOSFET
than for the CTG MOSFET, due to drain-to-channel coupling
through the HTI: As LG shrinks, so does Wstripe , meaning so that it can benefit more from source/drain stressors [19]. The
WHTI and, therefore, drain fringing fields increase. As noted minimum intrinsic delay of the HTI-DT MOSFET is still larger
in [11], drain fringing fields through the HTI region can cause than for the FinFET, but this performance gap can be closed
ION to taper off and even drop with a large enough increase by increasing εHTI and εsp,hk to 50 [20] (Fig. 5). Increasing
in WHTI . εsp,hk to 50 for the FinFET increases its intrinsic delay unless
The drain-to-channel fringing capacitance Cf,DB through the LG is reduced (from 3 nm for εsp,hk = 23 to 2 nm for εsp,hk =
trench isolation regions can be reduced by using a high-k iso- 50)—which makes it more difficult to be fabricated compared
lation material only in the trench isolation regions underneath with the HTI-DT MOSFET, for which the optimal LG is
the gate electrode and high-k spacers, and a low-permittivity 3–4 nm with the same εsp,hk .
dielectric (SiO2 ) elsewhere in the trench isolation regions.
This dual-trench (DT) isolation structure can be fabricated in
B. Critical AR
a straightforward manner by etching away the high-k isolation
material surrounding the source/drain regions after forming Thus far, the comparative analysis has been performed as-
the high-k inner spacers, and then refilling the trenches by suming a fin height of 9 nm (i.e., AR = 3). It is difficult to
conformally depositing and anisotropically etching the low-k ascertain today whether this will be easy or difficult to manufac-
material—which also forms the low-k outer spacers. In addition ture in the future. Therefore, the impact of fin AR is examined
to reduced Cf,DB , it also provides for reduced gate-to-source in this section. The “critical AR” is defined to be the minimum
and gate-to-drain capacitances. As a result, both normalized fin AR for the FinFET to have lower intrinsic delay than the
and raw ION , as well as intrinsic delay, improve and are less HTI or HTI-DT MOSFET and is determined by comparing the
dependent on LG . Due to its reduced Cf,DB , the optimal LG for best-fit curves for FinFET delay versus Hfin and HTI or HTI-
minimizing intrinsic delay is smaller for the HTI-DT MOSFET DT MOSFET delay versus εHTI = εsp,hk . As shown in Fig. 6,
compared with the HTI MOSFET; this means that LSD is larger the critical AR is significantly larger for the HTI-DT MOSFET
3254
Fig. 5. Intrinsic delay versus LG for the FinFET, CTG, and HTI MOSFETs.
The dielectric constants in the legend refer to either the high-k spacer only
(FinFET) or both the high-k spacer and HTI regions (HTI-DT).
Fig. 6. Critical fin AR versus εHTI and εsp,hk for the HTI MOSFETs,
with εHTI = εsp,hk . For each value of dielectric constant, the HTI MOSFET
and FinFET designs were chosen based on the lowest CGG ∗ VDD /ION .
For the FinFET, this corresponds to LG = 3 nm (εsp,hk = 23) or 2 nm
(εsp,hk = 50). For the HTI and HTI-DT MOSFETs, this corresponds to LG =
7 and 4 nm, respectively.
compared with the HTI MOSFET. For the HTI MOSFET,
the critical AR peaks at 0.883 with εHTI = εsp,hk = 35 and
then slightly drops with increasing dielectric constant due to
increasing Cf,DB . For the HTI-DT MOSFET, the critical AR
exceeds 2.5 for εHTI = εsp,hk = 50 and drops to 2 if εsp,hk
in the FinFET is increased from 23 to 50. If the critical AR
was defined instead using ION rather than intrinsic delay, then
it would be larger, as shown in Fig. 7; thus, for heavily loaded
circuits (such that the load capacitance CL  CGG ), the HTI-
DT MOSFET has a larger window of competitive advantage
over the FinFET. Note that this analysis does not account for
the Miller effect, which requires inverter delay simulations and
is covered in the next section.
These results indicate that the HTI-DT MOSFET can be ad-
vantageous over the FinFET if εHTI is sufficiently high and/or
if the fin AR cannot be sufficiently large (in the range from 2
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 12, DECEMBER 2010
Fig. 7. Critical fin AR versus εHTI and εsp,hk for the HTI-DT devices in
Fig. 6, but here comparing ION and CGG ∗ VDD /ION as the metric for
defining the critical AR.
to 4, depending on the performance metric). In other words, a
high-AR channel region is necessary for a thin-body MOSFET
to be of value. Thus, nanowire MOSFETs that have AR ∼ 1
are easily trumped by the HTI-DT MOSFET (ignoring the
effects of quantum capacitance [21]). If lithography and etching
processes can achieve narrow (< LG ) fins with high AR and
tight pitch, then the FinFET will offer higher performance
than the HTI-DT MOSFET irrespective of εHTI . Therefore,
the transistor structure that is most scalable will depend on the
limits of high-k dielectric and fin patterning technologies.
C. Inverter Delay
In this section, only the HTI-DT MOSFET is compared
against the FinFET, because of its performance advantage
over the conventional HTI MOSFET. For each CMOS inverter
simulation, the PMOS device is virtually scaled in width to
achieve balanced pull-up and pull-down delays. The inverter
output is connected to a load capacitance CL = 2 ∗ CGG , which
approximates the next inverter stage of a ring oscillator. (CGG
is the total gate capacitance, i.e., the sum of gate-to-source,
gate-to-drain, and gate-to-channel capacitances). The gate work
functions are tuned in each case so that every device meets
the IOFF specification. For the FinFETs and the HTI-DT
MOSFETs, in all cases, the NMOS and PMOS gate work func-
tions are in the range ∼4.4–4.6 and ∼4.7–4.9 eV, respectively.
The input signal is ramped from ground to VDD in 5 ps and then
held at VDD to allow the output voltage overshoot (due to the
Miller effect) and the high-to-low propagation delay τp (taken
at 0.5 ∗ VDD ) to be ascertained. All inverter simulations are for
the same devices as in Fig. 7.
As shown in Fig. 8, the output voltage overshoot is lower for
the HTI-DT CMOS inverter for the same εHTI . This originates
from the relationship between channel width and drain width:
To increase ION (to reduce the overshoot) in the FinFET,
the fin height must be increased—but this also increases the
source/drain width and, therefore, CGD ; thus, CGD /CGG is
constant and is equal to 0.5 for VDS = 0 V, as shown in Fig. 9.
VEGA AND KING LIU: COMPARATIVE STUDY OF FinFET VERSUS HTI MOSFET
Fig. 8. Comparison of percent overshoot in output voltage versus εHTI
(which is equal to εsp,hk ) for the HTI-DT MOSFET and the FinFET.
Fig. 9. CGD /CGG versus VGS for the HTI-DT MOSFET and the FinFET.
In contrast, to increase ION in the HTI MOSFETs, the gate
fringing fields through the HTI regions can be increased by
increasing εHTI , without any corresponding increase in the
source/drain width; therefore, CGD /CGG < 0.5 (Fig. 9) so that
the resulting output voltage overshoot is lower. The fin AR
would have to exceed 3 for the FinFET inverter to have similar
or lower output voltage overshoot compared with the HTI-DT
inverter.
It was shown earlier that intrinsic delay defines a lower
limit (for device-limited circuits) for critical AR, whereas ION
defines an upper limit (for interconnect-limited circuits). How-
ever, this lower limit does not account for the Miller effect and
is thus an underestimation, given the output voltage overshoot
advantage of HTI-DT MOSFETs over FinFETs shown in Fig. 8.
Fig. 10 plots the critical AR based on inverter delay compared
with the critical AR based on intrinsic delay as the performance
metric. When the Miller effect is taken into account, the critical
AR increases, more so for higher εHTI due to the reduction in
output voltage overshoot (Fig. 8). Thus, for εHTI = εsp,hk =
50, the critical AR increases from 2.59 to 3.22 compared with
3255
Fig. 10. Critical fin AR versus εHTI = εsp,hk for the HTI-DT MOSFET.
the FinFET with εsp,hk = 23 and from 2.01 to 2.51 compared
with the FinFET with εsp,hk = 50. This is significant in con-
sideration of the fact that the optimized HTI-DT MOSFET
has AR = 1, which eases gate and sidewall-spacer patterning
compared with FinFETs. These findings indicate that the quasi-
planar bulk MOSFET may be the transistor structure that is
most scalable to end-of-roadmap dimensions.
IV. C ONCLUSION
An alternative to the FinFET, i.e., the HTI MOSFET, is
proposed for ultimate CMOS scaling without the process com-
plexities of FinFET fabrication. This structure is essentially the
same as a conventional quasi-planar bulk MOSFET, except that
the trench isolation (or trench liner) material is a high-k dielec-
tric that amplifies gate coupling to the channel region sidewalls
to improve ION at constant IOFF . By utilizing an HTI-DT
isolation structure, drain sidewall fringing field effects are
reduced for additional performance (delay) benefit. The Miller
effect is lower for the HTI-DT MOSFET than for the FinFET,
which increases the design space in which the HTI device
architecture has a performance advantage. The modeling results
in this paper conservatively suggest that the quasi-planar bulk
MOSFET will prove to be more scalable for LSTP applications
than the FinFET, unless fin ARs greater than ∼2.5 are used.
ACKNOWLEDGMENT
The authors would like to thank Dr. E. Nowak (IBM) for his
support and very stimulating discussions throughout the course
of this study and Synopsys, Inc., for support and providing their
most up-to-date simulation tools.
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Reinaldo A. Vega (S’04–M’10) received the B.S.
and M.S. degrees in microelectronic engineering
from the Rochester Institute of Technology (RIT),
Rochester, NY, in 2004 and 2006, respectively, and
the Ph.D. degree in electrical engineering from the
University of California, Berkeley, in 2010.
He joined Integrated Nano-Technologies during
the summer/fall of 2001 as a co-op student, develop-
ing a fabrication process for prototype DNA detec-
tors. During the summer/fall of 2002 and 2003, he
worked as a co-op student with IBM, East Fishkill,
NY, where he performed analysis of radio frequency microelectromechanical
systems and alternative power generation techniques, development of copper
thru-plated inductors, and SOI device characterization of thermal diodes,
MOSFETs, and electrically programmable fuses (eFUSE) at the 90-nm tech-
nology node. During the spring of 2004, he performed a National Science
Foundation (NSF) Research Experience for Undergraduates at RIT, working
on multivalued logic/memory with resonant interband tunnel diodes. From
the spring of 2005 to the spring of 2006, while at RIT, he also worked
with Biophan Technologies, Inc., Rochester, NY, characterizing nanoparticle
films for medical applications. In 2010, he joined IBM as a CMOS Device
Design Engineer. He is the holder of one U.S. patent, with one U.S. patent
pending, and was selected to appear in the 2007–2009 issues of Marquis Who’s
Who in America. His research interests include advanced source/drain and
contact design, quantum devices, multivalued logic/memory, and 3-D circuit
integration.
Dr. Vega has served as a Reviewer for the IEEE ELECTRON DEVICE
LETTERS, IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE
TRANSACTIONS ON NANOTECHNOLOGY, and IEEE TRANSACTIONS
ON E DUCATION . He was the recipient of the First Place Award at the
2004 RIT IEEE Student Design Contest for his earlier work on Schottky
barrier MOSFETs. He was also the recipient of the 2004 Professor I. Renan
Turkman Scholarship for Outstanding Achievements in Semiconductor Device
Engineering, the 2004 RIT Undergraduate Research Symposium Award
of Excellence, the 2005 RIT Intellectual Property Productivity Award, an
Honorable Mention for the 2005 NSF Graduate Research Fellowship Program
(GRFP), a 2006 IBM/Global Research Corporation Fellowship, and the Best in
Session at SRC TECHCON 2008 and 2009.
Tsu-Jae King Liu (SM’00–F’07) received the B.S.,
M.S., and Ph.D. degrees from Stanford University,
Stanford, CA, in 1984, 1986, and 1994, respectively,
all in electrical engineering.
In 1992, she joined the Xerox Palo Alto Research
Center as a Member of Research Staff, researching
and developing polycrystalline-silicon thin-film tran-
sistor technologies for high-performance flat-panel
display and imaging applications. In August 1996,
she joined the faculty of the University of California,
Berkeley, where she is currently a Professor with the
Department of Electrical Engineering and Computer Sciences and an Associate
Dean for Research with the College of Engineering. Her current research
activities are in nanoscale integrated-circuit devices and technology, as well
as materials, processes, and devices for integrated microsystems.
Dr. Liu has served on committees for many technical conferences, including
the IEEE International Electron Devices Meeting and the Symposium on VLSI
Technology. She was an Editor for the IEEE ELECTRON DEVICE LETTERS
from 1999 to 2004. She was the recipient of the Defense Advanced Research
Projects Agency Significant Technical Achievement Award in 2000 for the
development of the FinFET and the IEEE Kiyo Tomiyasu Award in 2010
for contributions to nanoscale metal–oxide–semiconductor transistors, memory
devices, and microelectromechanical system devices.