6/19/2014 E0-286 (2:1) � Testing and Verification for SoC Design (Jan 2008)

E0-286 (2:1) - Testing and Verification for SoC

Design

Semester: Jan - Apr 2008

Instructor: Virendra Singh

Class Timings: 1200 - 1300 Hrs (MWF) @202, SERC

Syllabus:

VLSI design flow, Introduction to electronic system testing and test

economics, Fault modeling (Stuck-at, Bridge, Delay, and Cross-talk fault
models), Fault simulation, Test generation for combinational circuits, ATPG
algorithms (D-Algorithm, PODEM, and FAN), Test generation complexity, Test
generation for sequential circuits, Time frame expansion model, Design for
test, Built-In Self Test (BIST), Memory test, Delay test, SoC test issues and
methodologies, test data compression and power conscious testing, fault
diagnosis and Synthesis for test.

High level design flow and verification issues, Simulation based verification,
Formal verification techniques: Model checking, equivalence checking, SAT
solvers, BDDs, Symbolic model checking with BDDs. Semi-formal Verification
techniques: Symbolic Simulation, Bounded Model Checking, Sequential ATPG
based Model Checking.

Reference:

1. M. L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for

Digital Memory and Mixed Signal VLSI Circuits, Springer, 2005
2. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985
3. M. Abramovici, M. Breuer, and A. Friedman, Digital System Testing and
Testable Design, IEEE Press, 1994
4. M. Huth and M. Ryan, Logic in Computer Science, Cambridge Univ.
Press, 2004
5. Current Literature
6. Class notes

Prerequisite: Knowledge of Digital System Design

Class Test Schedule:

Test1: March 3 (Mon) @ 1130 Hrs - R.N 309, SERC (Open Book)
Test2: April 07 (Mon) @ 1200 Hrs � R.N 202, SERC (Open Book)
Test3: April 11 (Fri) @ 1200 Hrs � R.N 202, SERC (Open Book)

Final Exam: April 22, 2008 (2:00 - 5:00 PM) @202, SERC (Close Book)

Class Schedule:

Jan 9 Course Introduction

Jan 14 Basics of testing
(By Prof. Erik Larsson)
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6/19/2014 E0-286 (2:1) � Testing and Verification for SoC Design (Jan 2008)

Jan 18 Introduction VLSI design flow, need of testing

Jan 21 Yield Analysis Yield Analysis and fault modeling
Jan 23 Fault modeling Fault Modeling, Fault collapsing
Jan 25 Fault Simulation Fault Simulation (Serial and parallel)
Jan 28 Fault Simulation Fault Simulation (Deductive,
concurrent, and fault sampling)
Jan 30 Test pattern Generation TPG basics, Boolean Difference
method
Feb 1 Test pattern Generation Boolean Difference and BDD based
TPG
Feb 4 Algorithmic TPG Basics, D-Algorithm
Feb 6 ATPG D-Algorithm
Feb 8 Formal Verification Need of formal verification, SoC
(By Dr. Subir Roy) verification
Feb 9 ATPG - II 9-Valued Logic TG, PODEM
Feb 13 Testability Analysis Testability analysis, SCOAP
Feb 13 Formal Verification - I Basics of formal verification,
(By Dr. Subir Roy) introduction to LTL
Feb 15 Testability Analysis Testability analysis
Feb 16 Formal Verification - II LTL
(By Dr. Subir Roy)
Feb 18 ATPG - III FAN Algorithm
Feb 20 Sequential Circuit test - I Test Compaction, Sequential ckt.
Testing, Time frame expansion model
Feb 20 Formal Verification - III LTL
(By Dr. Subir Roy)
Feb 22 Sequential Circuit test - Sequential ATPG
II
Feb 22 Formal Verification - IV Introduction to CTL
(By Dr. Subir Roy)
Feb 27 Sequential Circuit test - DfT (Scan Design)
III
Feb 29 Sequential Circuit test - Partial Scan,
IV
Feb 29 Formal Verification - V CTL*
(By Dr. Subir Roy)
Mar 3 Test 1 (Testing)
Mar 7 Random Access Scan Random Access Scan: Attack problem
in 3 way
Mar 7 Formal Verification - VI SMC Algorithms
(By Dr. Subir Roy)
Mar 12 Sequential Circuit Class of sequential circuits with
Classes combinational circuit TG complexity
Mar 14 Formal Verification - VII
(By Dr. Subir Roy)
Mar 17 Sequential Circuit Class of sequential circuits with
Classes combinational circuit TG complexity
Mar 17 Delay Fault Testing Delay Fault testing and classification
Mar 19 Formal Verification � Verification of LTL properties
VIII
(By Dr. Subir Roy)
Mar 24 Delay Fault Testing - II Path Delay fault testing,
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6/19/2014 E0-286 (2:1) � Testing and Verification for SoC Design (Jan 2008)

Mar 26 Delay Fault Testing - III DFTG, Enhanced Scan Design, Test
application
Mar 28 BIST - I Built-In Self-Test
Mar 29 BIST-II BIST - TPG, LFSR
Mar 31 BIST - III BIST - RA
Apr 02 Memory Test Memory fault model, March tests
Apr 02 Formal Verification - IX
(By Dr. Subir Roy)
Apr 08 SoC Test Methodology - I
Apr 09 Semi-Formal Verification
(By Dr. Subir Roy)

Selected Readings (Papers):

1. D. Baik, K. K. Saluja and S. Kajihara, "Random Access Scan: a solution to test power,
test data volume and test time," International Conference on VLSI Design, Jan. 2004
2. H. Fujiwara, �A new class of sequential circuits with combinational test generation
complexity�, IEEE Trans. on Computers, Vol. 49, No. 5, Sep 2000, pp. 895-905
3. S. Ohtake, T. Masuzawa, and H. Fujiwara, �A non-scan DfT method for controllers to
achieve complete fault efficiency�, Proc. of the IEEE Asian Test Symposium (ATS)
1998, pp. 204-211.
4. T. Iwagaki, S. Ohtake, and H. Fujiwara, �A design methodology to realize delay
testable controllers using state transition information�, Proc. of the IEEE European
Test Symposium (ETS) 2004, pp. 168-173.
5. Y. Bonhomme et al., �Power driven chaining of flip-flops in scan architecture�,
Proc. of the IEEE International Test Conference (ITC) 2002, pp. 796-803.

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