Logic Built-In Self-Test

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0 What are the problems in today’s
semiconductor testing?
• Traditional test techniques become quite
expensive
• No longer provide sufficiently high fault coverage
0 Why do we need built-in self-test (BIST)?
• For mission-critical applications
• Detect un-modeled faults
• Provide remote diagnosis
 go
0 Online BIST
• Concurrent online BIST
• Non Concurrent online BIST
0 Offline BIST
• Functional offline BIST
• Structural offline BIST
 BIST

Offline Online
[Abramovici 1994]
Non-
Functional Structural Concurrent concurrent

Logic BIST Techniques

 System
Test Pattern Generator
(TPG)

Logic
BIST Circuit Under Test
Controller (CUT)

Output Response Analyzer

(ORA)

Structural off-line BIST

 u
Logic BIST requires much more stringent design restrictions when
compared to conventional scan. Therefore, when designing a logic BIST
system, it is essential that the circuit under test meet all scan design rules
and BIST specific design rules, called BIST design rules.
 Pattern G n on
0 Test pattern generators (TPGs) constructed
from linear feedback shift registers (LFSRs)
0 TPG
• Exhaustive testing
• Pseudo-random testing
• Pseudo-exhaustive testing
Standard LFSR
0 Consistsof n D flip-flops and a
selected number of exclusive-OR
(XOR) gates

hn-1 hn-2 h2 h1
[Golomb 1982]
Si0 Si1 Sin-2 Sin-1

An n-stage (external-XOR) standard LFSR

Modular LFSR
0 EachXOR gate placed between two
adjacent D flip-flops

h1 h2 hn-2 hn-1

[Golomb 1982]
Si0 Si1 Sin-2 Sin-1

An n-stage (internal-XOR) modular LFSR

 op
0 The internal structure of the n-stage
LFSR can be described by a
characteristic polynomial of degree n,
f(x).

hi is either 1 or 0,depending on the feedback path

 op
0 LetSi represent the contents of the n-
stage LFSR after ithshifts of the initial
contents,S0,of the LFSR, and Si(x) be
the polynomial representation of Si

If T is the smallest positive integer such that f(x) divides 1 xT ,then
the integer T is called the period of the LFSR.
g standard and

• 4-stage Standard LFSR

f(x)=1+x2+x4

1  2
 4
• 4-stage Modular LFSR
f  x 1 x  x 4
Primitive polynomials list
Primitive polynomials of degree n up to 100
 ng
0 Exhaustive Testing
• Applying 2 n exhaustive patterns to an n-input
 o n
0 Exhaustive Testing guarantees all
detectable, combinational faults will be
detected.
0 Test time maybe be prohibitively long if
input number is large than 20.
 Response An

0 Ones count testing

0 Transition count testing
0 Signature analysis
Ones ng
Assume the CUT has one output and the output contains a
stream of L bits. Let the fault-free output response be

Ones count testing will need a counter to count the number of 1s

in the bit stream.

Aliasing probability [Savir 1985]

One ng

T Signature
CUT
Counter

CLK

One counter as ORA

 ng
Transition count testing is similar to that for ones count testing,
except the signature is defined as the number of 1-to-0 and
0-to-1 transitions.
[Hayes 1976]

Aliasing probability
ng
 n
Signature analysis is the most popular compaction technique
used today, based on cyclic redundancy checking.

Two signature analysis schemes

• Serial signature analysis
• Parallel signature analysis
 n
An n-stage single-input signature register

h1 h2 hn-2 hn-1

M r0 r1 rn-2 rn-1

Define L-bit output sequence M

Let the polynomial of the modular be f(x)

F
 p

A 4-stage SISR
Aliasing probability
 n
Multiple-input signature register (MISR)

h1 h2 hn-2 hn-1

r0 r1 rn-2 rn-1

M0 M1 M2 Mn-2 Mn-1

An n-input MISR can be remodeled as a single-input SISR with

effective input sequence M(x) and effective error polynomial E(x)
 g

M0 1 0 0 1 0
M1 0 1 0 1 0
M2 1 1 0 0 0
M3
M3 1 0 0 1 1
M0 M1 M2
M 1 0 0 1 1 0 1 1

A 4-stage MISR An equivalent M sequence

Aliasing probability
Four Types of BIST Architectures:
0 No special structure to the CUT
0 Make use of scan chains in the CUT
0 Configure the scan chains for test pattern
generation and output response analysis
0 Use concurrent checking circuitry of the
design
 u n Observer

 Combined functionality of D flip-flop, pattern

generator, response analyzer, and scan chainReset
all FFs to 0 by scanning in zeros

The architecture applies to circuits that can be partitioned into

independent modules (logic blocks). Each module is assumed to have
its own input and output registers (storage elements), or such registers
are added to the circuit where necessary. The registers are redesigned
so that for test purposes they act as PRPGs or MISRs.

[Konemann 1980]
BIST implementation
u n Observer

Y0 Y1 Y2
B2
B1

0
D Q D Q D Q
1

Scan-In SCK X0 X1 Scan-Out/X2

A 3-stage BILBO
 Summary
 LFSR pattern generator and SISR response analyzer – preferred BIST
methods

 BIST has overheads: test controller, extra circuit delay, primary input MUX,
pattern generator, response compacter, DFT to initialize circuit and test the test
hardware

 BIST benefits:
 At-speed testing for delay and stuck-at faults
 Drastic ATE cost reduction
 Field test capability
 Faster diagnosis during system test
 Less effort to design testing process
 Shorter test application times