USN 1 S I 1LSP04

Siddaganga Institute of Technology, Tumkur – 572 103

(An Autonomous Institution affiliated to Visvesvaraya Technological University, Belgaum, Approved by AICTE, New Delhi, Accredited by NBA, New Delhi,
An ISO9001:2008 Certified)

First Semester M.Tech.- Signal Processing Examinations Jan. 2016

Advanced Digital Signal Processing
Time: 3 Hours Max. Marks: 100
Not : 1. Answer any 5 full questions
e

1 a) Discuss the special features of programmable digital signal processors to achieve high speed
program execution. 8
b) Find the Q.7 and Q.15 representation for the following decimal numbers:
i. 0.435.
ii. -0.725. 4
c) Derive an expression for signal to quantization noise ratio for a sine wave input with the
peak-to-peak voltage, VFS. Assume N-bit analog to digital converter. 4
d) Differentiate between rounding and truncation. Highlight on the range of these two errors. 4

2 a) A 16-bit fixed-point processor has an instruction cycle of 10 ns. A set of DSP libraries has
been written for some commonly used DSP algorithms. One of these functions is the FIR
filtering routine, which can perform sample-by-sample and block processing for an L-tap FIR
filter. The number of instruction cycles required to perform this function in given as
38 +N (4+L), where N = 1 for sample –by-sample processing and where 32 is the number of
samples used per block for block processing. Determine the maximum length of the filter that
can be implemented for stream and block processing methods. Assume sampling rate is
44.1 KHz. 8
b) Compute 8 –point DFT of x(n) = (-1)n, where n = 0 to 7. Use DIT-FFT algorithm. 6
c) Discuss in place computation and constant geometry in FFT algorithms. 6

3 a) Write a pseudo code to implement, butterfly structure used in DIT-FFT algorithm. Also draw
the butterfly structure and write related equations. 8
b) Find the order of low-pass digital filter to be used in A/D – H(z)-D/A structure that will have
a – 3 dB cutoff of 30 rad / sec and an attenuation of 50 dB at 45  rad/sec. the filter is
required to have linear phase and the system uses a sampling rate of 100 samples / sec. 4
c) Given, the transfer function of an IIR filter
 0.1329225  0.1805232 z 1  0.05834  0.50842 z 1
H ( z)    0.2499
1  0.028994 z 1  0.0445416 z  2 1  0.0484899 z 1  0.0179511z  2
Realize the filter in parallel form. Also write a pseudo code for implementation of the same
on a digital signal processor. 8

4 a) Sketch the frequency spectrum of the sinusoidal signal, x(n) = 5cos(0.2 n). Also sketch the
frequency spectrum of the signal obtained.
i. After up sampling x(n) by a factor 2.
ii. After down sampling x(n) by a factor of 2. 10
b) Define and prove noble identities. 6
c) Determine the poly phase decompositions for the following FIR filter.
H ( z )  2  3 z 1  2 z 2  4 z 3  5 z 4  2 z 5  6 z 6 . Assume D = 2. 4

-1- Please Turn Over

-2- 1LSP04
5 a) A signal x(n) at a sampling frequency of 6 KHz is to be decimated to yield a signal at a
sampling rate of 60 Hz. the signal band of interest extends from 0 to 25 Hz. The anti-aliasing
digital filter should satisfy the following specifications:
Stop band attenuation - 50dB.
Pass band - 0 to 25 Hz
Stop band - 30 to 60 Hz.
i. Design a single stage decimator. Compute the total number of operations per
second.
ii. Design a three stage decimator with decimation factors 10, 5 and 2. Compute the total
number of operations per second. 12
b) i. Draw a block diagram to realize a decimator with a sixth order low pass filter and down
sampling factor of 4.
ii. Draw a more efficient realization and write a flow chart for software implementation of the
efficient realization of the same. 8

6 a) Explain a DFT filter bank. How filter bank differs from trans-multiplexer? 8
b) Compare Fourier transform, Short-Time Fourier Transform (STFT) and Gabor transform. 6
c) What is concept of wavelet transform? How it is advantageous compared to STFT? 6
________