Module 5- CMOS Testing

Lecture 6 & 7 – CMOS Testing

Prepared By,
M.Rajmohan
AP(SG), ECE, HITS
 Course Outcome (CO1)
Students will be able to Summarize the test techniques at
the chip level and system level

Learning Outcome
Students will be able to articulate the Design strategies for
test

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 DESIGN STRATEGIES FOR TEST
Design for testability:
 The key to designing circuits that are testable are the two
concepts that introduced called controllability and
observability.
Controllability is the ability to set (to 1) and reset (to 0)
every node internal to the circuit.
Observability is the ability to observe either directly or
indirectly the state of any node in the circuit.

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 DESIGN STRATEGIES FOR TEST
Design for testability:
The three main approaches to what is commonly called
design for testability.
These may be categorized as:
 Ad-hoc testing
 Scan-based approaches
 Self-test and built-in testing

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 Scan-Based Test Techniques
A collection of approaches have evolved for testing that
lead to a structured approach to testability.
The approaches stem from the basic tenets of controllability
and observability.
They are effective for circuit partitioning
† They provide controllability and observability of
internal state variables for testing
† They turn the sequential test problem into a
combinational one

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 Scan Design Approaches
Four major approaches:
„ Shift-register modification
„ Scan path
„ Level-sensitive scan design (LSSD)
„ Random access

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 Scan Design Approaches

To make elements of state vector controllable and observable we add , we

add
„ A TEST mode pin (T)
„ A SCAN-IN pin (SI)
„ A SCAN-OUT pin (SO)
„ A MUX (switch) in front of each FF (M)

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 Scan Design Rules
Use only clocked D-type of flip-flops for all state variables
‰ At least one PI pin available for test; more pins, if
available, can be used
‰ All clocks controlled from PIs
‰ Clocks must not feed data inputs of flipflops

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 Scan Variations
There have been many variations of scan as listed below,
few of these are discussed here.
ƒ MUXed Scan
ƒ Scan path
ƒ Scan-Hold Flip-Flop
ƒ Serial scan
ƒ Level-Sensitive Scan Design (LSSD)
ƒ Scan set
ƒ Random access scan

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Scan Flip-Flops

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Shift Register Modification Approach

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 Scan path
 In this approach multiplexing is done by two different clocks instead of a MUX

Each FF consists of two latches operating in a master-slave

fashion, and has two clocks (C1 and C2) to control the scan
input (SI) and the normal data input (DI) separately.
The two-port raceless D-FF is controlled in the following
way:
For normal mode operation C2 = 1 to block SI and C1 = 0
→ 1 to load DI.
For shift register test mode C1 = 1 to block DI and C2 = 0
→ 1 to load SI.

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Scan path

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 Scan Design Rules
Use only clocked D-type of flip-flops for all state variables
‰ At least one PI pin available for test; more pins, if
available, can be used
‰ All clocks controlled from PIs
‰ Clocks must not feed data inputs of flipflops

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 Multiple Scan Registers
Possibility of distributing scan flip-flops among any number
of shift registers, each having a separate scanin and scanout
pin
‰ Test sequence length determined by the longest scan
shift register
‰ Just one test control (TC) pin essential

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 Partial Scan
 Subset of flip-flops is scanned:
‰ Objectives:
 Minimizing area overhead and scan sequence length, while
achieving required fault coverage
Excluding selected flip-flops from scan:
Improvement of performance
Allowing on limited scan design rule violations
Allow automation:
In scan flip-flop selection
In test generation
Shorter scan sequences

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 Partial Scan Architecture


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Flip Flop Partial Scan

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 Partial Scan
Generalized scan method; scan varying from 0 to 100%
‰ Partial-scan has lower overheads (area and delay) and
reduced test length
‰ Partial-scan allows limited violations of scan design
rules, e.g., a flip-flop on a critical path may not be scanned

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Clocked Scan Flip Flop

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Clocked Scan Flip Flop

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Clocked Scan Architecture

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Clocked Scan Architeture

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 Scan Hold Flip Flop
Special type of scan flip-flop with an additional latch designed for
low power testing application.
The control input HOLD keeps the output steady at previous state of
flip-flop.
ƒ For HOLD = 0, the latch holds its state and for HOLD = 1, the
hold latch becomes transparent.
ƒ For normal mode operation, TC = HOLD =1 and for scan mode,
TC = 1 and Hold = 0.
ƒ Hardware overhead increases by about 30% due to extra
hardware the hold latch.
ƒ This approach reduces power dissipation and isolate
asynchronous part during scan.

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Scan Hold Flip Flop

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 Level-Sensitive Scan Design
Latch-based design used at IBM
† Race- & hazard-free operation and testing
„ Insensitive to rise time, fall time, delay, etc.
† Faster than shift register (SR) modification;
low hardware complexity
† More complicated design rules
† Uses 2 latches
„ One for normal operation and one for scan

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 Level-Sensitive Scan Design
A logic circuit is level sensitive if the steady state response
to any allowed input change is independent of the delays
within the circuit.

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Polarity-Hold Latch

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Polarity-Hold Shift Register Latch

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Shift Register Latch (SRL)

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Double Latch-based Design (w/o LSSD)

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Double Latch-based Design (w/o LSSD)

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Shift Mode

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Double Latch based design (w/LSSD)

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Test Mode Operation

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Polarity-Hold Shift Register Latch

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LSSD

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Random Access Scan

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 Random Access Scan
It uses an address decoder. By using address decoder we can
select a particular FF and either set it to any desired value or
read out its value.


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Thank you

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