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Design for Testability in VLSI

The document discusses design for testability, which has three main categories: functionality testing/logic verification, silicon debug, and manufacturing test. It introduces faults that can occur due to dust or imperfections, and discusses ad hoc testing techniques like partitioning, adding test points and multiplexers, and state reset capabilities. Finally, it describes scan design which provides observability and controllability at each register using either serial or parallel scan and utilizes a normal mode and scan mode where registers are connected as a shift register.

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jasmine reena
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217 views10 pages

Design for Testability in VLSI

The document discusses design for testability, which has three main categories: functionality testing/logic verification, silicon debug, and manufacturing test. It introduces faults that can occur due to dust or imperfections, and discusses ad hoc testing techniques like partitioning, adding test points and multiplexers, and state reset capabilities. Finally, it describes scan design which provides observability and controllability at each register using either serial or parallel scan and utilizes a normal mode and scan mode where registers are connected as a shift register.

Uploaded by

jasmine reena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

EC 3552 VLSI AND CHIP DESIGN

UNIT V
DESIGN FOR TESTABILITY
DESIGN FOR TESTABILITY

THREE MAIN CATEGORIES:

 FUNCTIONALITY TEST/LOGIC
VERIFICATION

 SILICON DEBUG

 MANUFACTURING TEST
FAULT

 Dust Particles and small imperfections in


starting material or photo masking can result
in bridged connections or missing features.

 These imperfections result in term named as


FAULT
DESIGN FOR TESTABILITY
AD HOC TESTING

 Collection of ideas aimed at reducing the


combinational explosion of testing
 Useful for designs where scan,ATPG and
BIST are not available.
 Common techniques for adhoc testing:
 Partitioning large sequential circuits
 Adding test points
 Adding multiplexers
 Providing for easy state reset
AD HOC TESTING

 Avoids the overhead of systematic approach


testing
 Used only for simple design.
 System complexity is more.Hence structural
approach testing is needed.
SCAN DESIGN

 To provide observability and controllability at


each register
 Two types
(i) serial scan
(ii) parallel scan
 Two Modes
(i)Normal mode
(ii) Scan mode(scan chain spanning-gaint shift
register)
SCAN DESIGN

 Modern scan is based on use of scan registers


 It consists D FF preceeded by MUX
 Scan signal deasserted(=0)
register-conventional register
stores data on D input
 Scan signal asserted,
Data loaded from SI pin
connected in shift register to previous Q
register output
SCAN DESIGN

DESIGN FOR TESTABILITY EC 3552 VLSI AND CHIP DESIGN UNIT V
DESIGN FOR TESTABILITY THREE MAIN CATEGORIES: FUNCTIONALITY TEST/LOGIC VERIFICATION SILICON DEBUG MANUFACTURING TEST
FAULT Dust Particles and small imperfections in starting material or photo masking can result in bridged connections or
DESIGN FOR TESTABILITY
AD HOC TESTING Collection of ideas aimed at reducing the combinational explosion of testing  Useful for designs where sc
AD HOC TESTING Avoids the overhead of systematic approach testing Used only for simple design. System complexity is mor
SCAN DESIGN To provide observability and controllability at each register Two types (i) serial scan
SCAN DESIGN Modern scan is based on use of scan registers It consists D FF preceeded by MUX Scan signal deasserted(=0)
SCAN DESIGN

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