SCAN TEST DESIGN METHODOLOGY AND PRACTICAL RESULTS

Joe Canning

Content
This work is associated with providing good test coverage on digital designs. The concept of using scan test cir-
cuitry in synchronous digital designs as a solution is introduced. There is a description of the methodology when
using “Synopsys Test Compiler”. Finally, some results of the experience of the author on some of Analog De-
vices’ video encoder products are outlined.

Background

More and more of Analog Devices’ new products have large portions of digital circuitry. On some designs the
work-hours required to provide sufficient test coverage on digital circuitry has comprised -20% of the design
effort. This is the case, because many of the techniques used previously relied heavily on manual or semi-auto-
matic iterative generation of test patterns. Also the engineer generating the patterns required a thorough knowl-
edge of all the modes of operation of the part. With these techniques, because the time required for pattern
generation is so long, it is usually deferred until after silicon tape-out. By then, it is too late to remove struc-
tures which are untestable or which lead to low test coverage. On synchronous designs scan test methodology
can circumvent a lot of these problems albeit with an overhead of sorne additional die area (circa 10%).

Theory

As an introduction to the concept of scan test we will use the circuit in Figure 1 (next page). There are 2 flip-
flops (A and B) feeding combinational circuity - an inverter and an AIND gate. The AND gate feeds into a third
flip-flop C. All 3 flip-flops update on the rising edge of the same clock (CLK). Therefore, at each rising CLK
edge the data stored in A and B which has propagated through the inverter and the AND gate is latched into
flip-flop C. In the example shown a logic 1 in A and a 0 in B causes ai 1 to be latched into C.

Now let us imagine that a “stuck at 0” fault exists at the inverter output i.e. that output of the inverter remains at
logic low regardless of its input stimulus. This causes a 0 to be presented at the D input of flip-flop C. At the ris-
ing edge of CLK a 0 is latched into C instead of a 1 as expected.

In this scenario, it is quite easy to observe the effect of stuck at 0 fault at the inveirter output i.e. by reading the
contents of flip-flop C after the rising edge of CLK. It is also easy to 4controlthe conditions which expose the
fault. That is to set the contents of flip-flops A and B so that the inverber should drive a 1 and so that the inverter
output should be gated through the AND gate to flip-flop C.

However, consider the situation where the circuit shown is not directly accessible. That is, the circuit may be
buried deep within a synchronous design. To control the contents of fiip-flops A and B may involve applying a
long and complicated set of signals to the accessible (primary) inputs of the device. Similarly, observing the

Joe Canning is with Analog Devices, Limerick

18/1
 Figure 1: Sample circuit
A

output of flip-flop C may not be trivial. If may only feed deep internal nodes which are not directly accessible
by primary outputs. In summary, controlling and observing the fault is not easy.

By changing the flip-flops to scannable ones and adding a scan chain we can allow controllability and observ-
ability of the flip-flops. To make a flip-flop scannable a multiplexer is added (this scan style is called multi-
iexed flip-flop) see figure 2 (below). The inputs to the multiplexer are the nonnal data input of the flip-flop and

Figure 2: Scannable flip-flop

Normal Input
Norma
Scan Out
Input
Scan Input

C k Scan Enable 2 Clk

Non Scan flip-flop Scannable flip-flop
the scan-input signal. The active input of the multiplexer is controlled by the scan-enable signal. One of the
a>
data outputs of the flip-flop (Q or is used as the scan output signal. The scan out signal is connected to the
scan in signal of another scan cell to form a serial scan (shift) capability.

Let us examine how adding scan capability effects the circuit in figure 1. Figure 3 (next page) shows the circuit
with scan capability added. Imagine that scan enable (SEN) signal is high - then the scan path as shown by the
thick lines is active. The scan in has come from a primary input through many scannable flip-flops to flip-flop
B. The scan path continues through flip-flop A and out to other flip-flops in the design. Flip-flop C is also on the
scan path. By scanning in the correct data on the primary scan input and clocking it the required number of
times, the data arrives at flip-flops A and B as shown. Therefore, we have managed to control the fault (we have
set up the conditions to expose it).

1812
 Fimre 3: Scan Mode (SEN := 1)
v

N
II “.Y

I
scan in Scan Out

We now want to latch the output of the AND gate into flip-flop C to capture the fault. Currently, flip-flop C only
sees its scan in input as scan mode is enabled. Therefore we must lea.ve scan mode before the next rising CLK
edge. We leave scan mode by setting scan enable low (SEN=O). The active part of the circuit is now shown by
the thick line in figure 4 (next page).

At the rising edge of CLK the output from the AND gate is captured i n flip-flop C. This is a 0 or 1 depending on
whether the fault was present or not. We need to observe the contents of flip-flop C. To do this we re-enter scan
mode by setting scan enable high. The flip-flops become linked in 1 ljong shift register again. By clocking CLK
the required number of times, the data in flip-flop C will propagate out through the other flip-flops on its scan
chain to the primary scan output pin. When it appears at this primary output pin, the data can be checked for
correctness.

By applying this theory across the flip-flops in a synchronous design, most of the nodes should become control-
lable and observable for stuck at faults. There is software available to implement the scan capability. There is
also software available to automatically generate the test patterns which use the scan capability to check for
faults. In the authors case, “Synopsys Test Compiler” was used for the scan insertion and for the automatic test
pattern generation(ATPG).

Implementation

This describes the “Synopsys” implementation which we used. The test methodology was chosen early in the
design phase. It was easy for designers to check their modules for testability as they proceeded. The Synopsys
software can check a module for some of the more common scan test problems - for example flip-flops which
are driven by different clock domains. Resolving these issues during the early part of the design effort mini-
mizes the problems when all the modules are finally knitted together..

1813
 Figure 4: Normal Functional Mode (SEN = 0)

I
---------*I

Scan in Scan Out

At the end of the core design a “test scan insertion” takes place (Figure 5). This means that some or all flip-

Figure 5: Implementation Flow /------,

Core Design

c
L
Scan Insertion

Pattern Generation
r
I 1 Vector Formatting

flops in the design are changed to scannable flip-flops which are linked in one or more scan chains. As
described earlier in the theory section, this allows the internal state of the device to be easily controlled. There-
fore, the circuit conditions to detect most “stuck-at” faults can be set up using the scan chains. This scan inser-
tion phase adds to the die area due to the extra multiplexer on the flip-flops and the scan chain routing.

1814
This test methodology views the design from a structural rather than a functional point of view. Thus the engi-
neer generating the test patterns does not need to have a thorough understanding of all modes of operation of
the part.

Using the “Synopsys Test Compiler”, test patterns to detect faults wcre automatically generated. Once the test
insertion had been successful, it was usually feasible to generate test patterns which give stuck-at fault coverage
of >95% in a matter of hours. This allowed proven fault coverage before tape-out. This was a real benefit as
prior to this, it was not uncommon for testability issues to arise during electronic test solution development
after the silicon had arrived.

For figure 5 the steps from core design to pattern generation have already been mentioned. After this, it is vital
to perform some simulations on the design with the patterns which have been generated. This can highlight
some potential issues (e.g. timing problems). We used “Verilog” for this simulation. The test patterns were for-
matted as a Verilog “test bench”. This test bench was simulated witfithe Verilog net list of the design and with
back annotated timing information. To fix problems which arise here, one may have to return to the core design
and make edits before entering the scan insertion phase again.

Once over the simulation hurdle, the vectors are translated to load on automatic test equipment. The vectors can
be ready for use as soon as real silicon arrives.

Results

The author was involved in using scan testing on some video encoder chip designs (e.g ADV7175N6A and
ADV717011). These designs had digital cores of around 200,000 gates. The fault coverage was >95%. The
work-hours required to provide sufficient test coverage on digital circuitry comprised ~ 1 0 %
of the design
effort.

There were some problems encountered. The most critical of these was concerned with clock skew between
adjacent flip-flops on the scan chain. As an example of this, consider figure 6. There 2 flip-flops cascaded. The

Figure 6: Data Slippage due to Clock Skew

D
A

Q
-- D
B

Q ...110...
...110... Scan in Sc:min
1 Scan en 1 ’ Scanen

-a--

data at the scan in input of flip-flop A should appear at the Q output of flip-flop B after 2 rising clock edges.
However, the clock arrives later at B than at A. Therefore, the data latched into flip-flop A is presented at the
scan in input of flip-flop B before the rising clock edge arrives at B. ‘Thus the data in flip-flop A “slips” through
into flip-flop B when the delayed clock edge arrives at B. In fact, the 2 flip-flops above behave effectively like a
single flip-flop. A situation like this on a scan chain can cause severe difficulties with the test strategy. This is
why it is so important to observe the implementation phase which in,volves simulations on the design with the
pattems generated and with back annotated timing information.

1815
Conclusion

The methodology described certainly has advantages with regard to resources and time-to-market. Any scan
implementation will incur extra die area but because of time and resources saved this may be worthwhile. The
“Synopsys” implementation can work but it needs careful thought and thorough simulation to avoid potential
problems.

18/6