VLSI TESTING

 CMOS Testing
 Need for testing
 Test Principles
 Design Strategies for test
 Design for testability
 Practical design for test guidelines
 Chip level Test Techniques
 System-level Test Techniques
 Built-In-Self-Test(BIST)
 Design for testability (DFT)
• DFT is a set of design rules or guidelines which, if
obeyed will facilitate test
• Any failure occurring during testing is due to either
poorly controlled fabrication process or because of
design defect
• The aspect of testability is based on two key
concepts
• (i) Controllability
• (ii) Observability
 Design for testability (DFT)
• DFT covers three important approaches (Chip level)
• (i) Ad-hoc testing (Collections of ideas)
– Adding test points
– Adding multiplexers
– Dividing large counters
• (ii) Scan based approaches – structured approach
– Scan path
– Full scan
– Partial scan
• (iii) Built-in self test (BIST) – structured approach
– Pseudo random pattern generator
– Signature analyzer
 Ad-hoc Testing techniques /
practical DFT guidelines
• Practical guidelines for DFT
– Improve Controllability and Observability
– Adding multiplexers
– Partition large circuits
– Divide long counters
– Initialize sequential logic
– Bypassing techniques
– Avoid logical redundancy
– Avoid delay dependent logic
– Separate analog and digital circuits
 Scan Path
A scan path is a DFT technique which involves
specialized flip-flop or latch allowing data to be scanned
in for control and then out for observation
It is activated in scan mode for test purposes.

A scan path consists of placing a multiplexer just ahead

of each flip-flop as shown in figure.

1 0
0 – Normal
1 – Test
 Scan Path
A scan path is tested by shifting a special pattern
through the scan path before the testing process begin

The test pattern consists of 1s and 0s that test the ability

of the scan path to shift all possible transitions
SCAN based TESTING
 Scan shift operation

Test mode (1) Test mode (1)

Normal mode (0) / Test mode (1) control signal

 Advantages of Scan Path
• 1. Test vector can be generated by automatic
test pattern generator (ATPG)
• 2. During design phase, problems like
observability and controllability need not be
considered
• 3. No need of complex test vector generator
for all inputs except scan in and scan out
 Disadvantages of Scan Path

• 1. Scan path results in hardware overhead as

additional multiplexers are required
• 2. Speed degradation may be observed due to
additional multiplexers in signal path
Full scan and Partial Scan
Full scan
 Partial Scan
• In partial scan mode, all the flip-flops are not into
the scan path
• The gate overhead is significantly low for partial
scan
• Also it improves the fault coverage to adequately
high level
• The combinational ATPG is used for full scan
• The sequential ATPG is used for partial scan
 Scannable Flip-flops

Scan Flip-flop
Using Master slave
arrangement Scan Flip-flop

Using Master slave arrangement Scan Flip-flop

Scan shift operation
 Built-in Self test (BIST)
 As the complexity of individual VLSI circuits and as
overall system complexity increase, test generation and
application using external testers becomes an expensive,
and not always very effective means of testing.
Further, there are also very difficult problems associated
with the high speeds at which many VLSI systems are
designed to operate.
 Such problems require the use of very sophisticated,
but not always affordable, test equipments.
 BIST Objectives
BIST objectives are:

1. To reduce test pattern generation costs;

2. To reduce the volume of test data
3. To reduce test time
4. BIST techniques aim to effectively integrate an
automatic test system into the chip design.
 Built-in Self Test
• With the increasing complexity of VLSI systems, test
generation and test application becomes expensive
and may not be effective
• At speed testing is also not supported by external
testers
• These aspects can be handled by incorporating BIST
which also reduces:
• (i) The volume of test data
• (ii) Cost involved in test pattern generation
• (iii) Test time
 Built-in Self Test
• It incorporates one or many of the following
structures
• (i) Linear Feedback shift register (LFSR) – PRSG
• (ii) Signature analyser
• (iii) Built-in logic block observer (BILBO)
 BIST : Test pattern Generation
 LFSR techniques can be applied in a number of ways,
including
 random number generation
 polynomial division for signature analysis
 h-bit counting
 LFSR can be either series or parallel
 The differences being in the operating speed and in
the area of silicon occupied
 Parallel LFSR being faster but larger then serial LFSR
 3 – bit LFSR

0 1 2 3

Characteristic Polynomial : X3 + X1 + X0
Assume any initial value: Except 000
Check the sequence for 2n - 1
 BIST : LFSR
• An n-bit LFSR will cycle through 2n - 1 states before repeating
the sequence
• Act as Pseudo Random Pattern Generation (PRPG) and as a
Test Response Analyzer (TRA) to observe the output signals

D Y D Y D Y D Y D Y D Y D Y D Y
x0 x1 x2 x3 x4 x5 D_FF
x6 x7 x8
D_FF D_FF D_FF D_FF D_FF D_FF D_FF

Clk

Characteristic Polynomial : X8 + X6 + X5 + X1 + X0
Tapping points for Selected LFSRs
The feedback connections or tapping points in an LFSR are
represented by a polynomial function called characteristic polynomial.
The feedback connections decide the number of possible binary
combinations in the flip-flops, called length of the sequence

Bit Size Tapping points in XOR Tapping points for XNOR

3 3, 1, 0 3, 2
4 4, 1, 0 4, 3
8 8, 6, 5, 1, 0 8, 6, 5, 4
16 16, 5, 3, 2, 0 16, 15, 13, 4
32 32, 28, 27, 1, 0 32, 22, 2, 1
64 64, 4, 3, 1, 0 64, 63, 61, 60
 BIST : Signature Analysis
 Data compression techniques are currently used in BIST
systems
 It consist of making comparisons on compacted test
responses instead of on the entire test data, which can
be huge in some case.
 The test compacting scheme currently used most is
called signature analysis.
 The signature from the DUT is compared with the
expected signature to determine if the DUT is fault-free.
 BIST : Signature Analysis
 Signature analysis performs polynomial division, that is
to say division of the data out of the device under test
(DUT).
 This data is represented as a polynomial P(x) which is
divided by a characteristic polynomial C(x) to give the
signature R(x), so that R(x)=P(x)/C(x)

Test Pattern Generator

Design Under test Compaction
TPG Analysis
(DUT) Signature
(E.g., Digital Tester)

Figure: Built-in-self-test: Signature analysis

 Multiple input Signature Register
A signature analyzer receives successive outputs of
a combinational logic block and produces a
syndrome that is a function of these outputs.
 BIST : Signature Analysis
The difference between the faulty signature and a good
signature may also be used to indicate the nature of the
fault.
Signature analysis has been proved to be a reliable and
attractive alternative to full un compacted testing.
 Data Compression: 1’s counting, 0’s counting
Another technique of data compression - transition
counting - has been in use for some considerable time.
This consists of counting transitions of a specified
direction (0 to 1 or 1 to 0) and then comparing this count
with the count obtained from the simulation model.
 Built-in Logic Block Observer
 BILBO is a built-in test generation scheme which uses
signature analysis in conjunction with a scan path.
It is aimed at integrated modular and bus-oriented
systems, such as microprocessor and similar circuits.
 The major component of a BILBO is an LFSR with a few
gates. Here BILBO is controlled by two signals, B1 and B2
which define the modes.

B1

B2
0
Scan in 1

Feedback
 BILBO
Table 4 Operation modes of BILBO

B1 B2 Operation Modes
0 0 Scan
0 1 Reset
1 0 PSRG / MISR
1 1 Normal Register
Example BILBO usage
 Built-in Logic Block Observer
In the Test 1 (Scan) mode, B1=B2=0 and the storage
elements are configured as a scan path
 All storage elements being connected as a serial shift
register (Figure (b)).
Test vectors are then applied to the scan-in input and
responses shifted out at the scan path output.
The analysis of data is then similar to that for a simple
scan-path test.
 Built-in Logic Block Observer

Scan 0
in

Figure (b): Scan Mode (00)

 Built-in Logic Block Observer
 Reset mode, B1=0,B2=1, as in figure (d),

Figure (b): BILBO Reset Mode (01)

 Built-in Logic Block Observer
 Test mode, B1=1,B2=0 , as in figure (d),
 The circuit is configured in a LFSR mode and can be
used either as a polynomial divider to compact data or as
a random test pattern generator

Figure (b): BILBO TPG / MISR Mode (10)

 Built-in Logic Block Observer
 Test mode, B1=1,B2=0 , as in figure (d),
 The circuit is configured in a LFSR mode and can be
used either as a polynomial divider to compact data or
as a random test pattern generator

• If the D inputs are taken from the output of the CUT,

then the LFSR acts as Multiple input signature
register (MISR) and hence it produces the signature
 Built-in Logic Block Observer
Normal (Register) mode, B1=1,B2=1, as in figure 10.48
 Advantages of BIST
• (i) Low cost
• (ii) High quality testing
• (iii) Faster fault detection
• (iv) Ease of diagnostics
• (v) Reduced maintenance and repair costs
Summary
Doubts Clarifications
Polynomial Division
Sequential LFSR as MISR
Manufacturing Defects
 References
• “VLSI Test Principles and Architectures : Design for
Testability” By Laung-Terng Wang, Cheng-Wen Wu,
Xiaoqing Wen
• “CMOS Digital integrated circuit analysis and design”
by Sung Mo kang, Yusuf Leblebici
• http://book.huihoo.com/design-of-vlsi-systems/
ch08/ch08.html
• http://www.eet.bme.hu/~benedek/Vlsi_Design/Lect
ures/Design_for_Test.pdf