Microsystem Technologies (2018) 24:3341–3348

https://doi.org/10.1007/s00542-017-3691-3
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TECHNICAL PAPER

Performance evaluation of domino logic circuits for wide fan-in gates

with FinFET
Ajay Kumar Dadoria1 • Kavita Khare1 • Uday Panwar2 • Anita Jain3

Received: 21 December 2017 / Accepted: 22 December 2017 / Published online: 3 January 2018
 Springer-Verlag GmbH Germany, part of Springer Nature 2018

Abstract
Power dissipation, propagation delay and noise are major issues in digital circuit design. In this paper, a new leakage-
tolerant domino circuit is presented which has lower power consumption and higher noise immunity without significant
delay increment for 8 and 16 input OR gates are designed and simulated using existing and proposed techniques in FinFET
technology. In this paper utilize the property of FinFET on domino circuit in order to improve the overall performance of
the circuit. Here all the circuit is simulated at 32 nm process technology by using HSPICE simulation at supply voltage of
0.9 V in MOS, short gate (SG) and low power (LP) mode at 10 MHz frequency. Comparison is done on the basis of power
dissipation, propagation delay and unity noise gain. FinFET technology in SG mode reduces propagation delay while LP
mode reduces power dissipation. Maximum power saved by ultra low power stacked (ULP-ST) domino logic for 8 and 16
input OR at 15.5, 18.39% in SFLD, 32.91, 28.22% in HSD, 40.60, 44.67% in CKD in SG mode and for LP mode 18.26,
21.68% in SFLD, 28.84, 27.94% in HSD, 55.45, 44.59% in CKD, respectively.

1 Introduction scaled down in order to reduce power consumption (Tawfik

and Kursun 2009; Hisamoto et al. 2000). Due to technol-
Dynamic logic gates have lesser area and high speed as ogy scaling, the thickness of gate oxide is also scaled down
compared to static dynamic gates. So wide fan-in dynamic due to which there is exponential increase in gate leakage
gates are used in SRAM, DRAM and high speed micro- current. The precharge node of domino logic may be dis-
processors (Wong et al. 1999; Nowak et al. 2004). If a large charged due to excessive leakage. Also, less threshold
fan in gate is designed using static CMOS logic, the voltage makes the dynamic logic more susceptible to cross
number of transistors to be connected in series will be very talk and input noise. So reduced switching point, leakage
large. However, due to large number of inputs, the per- current and noise sources affects the robustness of domino
formance of dynamic gates is largely affected by sub- logic.
threshold leakage current and noise. Now with the scaling Power consumed by a logic gate is given by:
of technology, supply voltage and threshold voltage is also Pgate ¼ Psw þ Psc þ Pleak ð1Þ
where Psc is the power due to short circuit of supply and
& Ajay Kumar Dadoria
ajaymanit0@gmail.com ground, Psw is power due to circuit capacitances charging
and discharging and Pleak is the power due to leakage
Kavita Khare
kavita_khare1@yahoo.co.in current (Rasouli et al. 2010; Mahmoodi and Roy 2004;
Gong et al. 2008). To over from this problem a new type of
Uday Panwar
panwaruday1@gmail.com multigate device come into the existence which reduces the
shorter channel effect, improve ION/IOFF of the transistor
Anita Jain
anitajainone@gmail.com without sacrificing the performance of other parameters
like delay, capacitance etc.
1
Department of Electronics and Communication Engineering, The paper is arranged as follows: literature review is
MANIT, Bhopal 462003, India
given in Sect. 2 in which various design techniques are
2
Department of Electronics and Communication Engineering, discussed using CMOS logic. In Sect. 3, proposed logic is
SIRT, Bhopal 462003, India
design using FinFET technology. In Sect. 4, results and
3
Cummins College of Engineering for Women, Pune, India

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3342
discussion of proposed circuit using FinFET technology.
conclusion is given in Sect. 5.
2 Literature review
The basic dynamic logic is standard footless domino logic
(SFLD) circuit as shown in Fig. 2. In domino logic the
evaluation phase major concern is reduction of leakage
currents through PDN, even all inputs are at low logic
level. This leakage current is due to band-to-band tunneling
(BTBT) current, gate tunneling current and subthreshold
leakage current. In standard domino P-CNT keeper tran-
sistor prevent from undesirable discharge of the dynamic
node due to leakage current and charge sharing from PDN
during evaluation phase. In this way noise immunity of
circuit improve.
The keeper ratio K is defined as


lP WL Keepertransistor
K¼
: ð2Þ
ln WL evaluationnetwork
where W and L are the transistor size, and ln and lp are the
mobility of electron and hole, respectively. Nowadays
traditional keeper is less effective in ultra-deep submicron
regime of CMOS technology, to improve noise immunity
of dynamic logic by upsizing of the keeper, that increase
contention current between keeper transistor and the eval-
uation network or PDN i.e. wide OR logic gate.
2.1 FinFET
A FinFET is a three dimensional transistor in which the
channel is designed above the insulator In FinFET tech-
nology, there is a thin layer (vertical) called Fin on a silicon
substrate. This thin layer acts as source and drain for the
transistor. The thin layer is covered by gate from three
sides. This gives a good control of channel from three
sides. Due to this fin shape, many gates can be operated on
one transistor. FinFETs are less affected by short channel
effects as compared to CMOS technology (Jeyasingh and
Bhat 2008; Allah et al. 2000).
FinFET has four terminals—source, drain and a double
gate (back gate and front gate). This double gate can be
used in three two modes as shown in Fig. 1.
In short gate (SG) modes, the two gates of FinFET are
shorted together so that gate covers the channel from three
sides and provides good control over channel. In this case,
power dissipation increases but delay of the circuit
decreases.
In insulated gate (IG) mode, the two gates of FinFET
may be driven by different signals due to which no. of
FinFETs can be reduced in the circuit.
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Microsystem Technologies (2018) 24:3341–3348
High bias
Low bias
SG LP IG
Fig. 1 Mode of operation of FinFET. (1) Short gate mode (SG), (2)
insulated gate mode, (3) low power mode
In low power (LP) mode, high voltage is applied at back
gate of P-FinFET and low voltage to back gate of N-Fin-
FET. Due to this, the threshold voltage of P and N devices
will vary reducing the power consumption but increasing
the delay.
2.2 Domino circuits
Thus in the SFLD circuit, power and delay increases, this
makes critical problem in wide fan-in dynamic gate due to
large number of N-FinFET transistor are connected at
dynamic node (Hisamoto et al. 2000; Frustaci et al. 2008).
So there is trade-off between noise immunity and perfor-
mance due to limitation in pull-down legs. Numerous
techniques are proposed to address this issue. These are
divided into two groups, in the first group circuit tech-
niques changes the controlling circuit of the gate voltage of
keeper such as conditional-keeper domino (CKD) (Liao
et al. 2014), high-speed domino (HSD) (Peiravi and Asyaei
2012), leakage current replica (LCR) keeper domino
(Dadoria et al. 2016a), and controlled keeper by current-
comparison domino (CKCCD) (Dadoria et al. 2017a), DFD
circuit is used to obtain low leakage current and increase
noise immunity of circuit. In this circuit, M1 is employed
in diode configuration in series with evaluation network to
reduce leakage current by using stacking effect. Figure 2
shows that if we increase the width of the evaluation
transistor there is increment of delay take place this happen
because evaluation delay of the circuit increases because
increment in the resistance in the path to discharge the
dynamic node of the circuit through evaluation network.
Due to the leakage current of evaluation network, there
is some voltage stablish across footer diode M1 in the
evaluation phase. The addition of keeper transistor
improves robustness of the circuit but increases propaga-
tion delay and power consumption as shown in Fig. 3. As
keeper size goes on increasing, delay and power also
increases. So for faster applications, smaller keeper is used
and for robust design, keeper size is increased. Figure 3
shows the effect of keeper upsizing on power dissipation
for a 16 input OR gate using FLDL logic. A footer NMOS
is connected between evaluation logic and ground to
Microsystem Technologies (2018) 24:3341–3348 3343

160 Width of footer N1 = 200 nm Vdd Vdd

Keeper
140 Transistor
Clock

120
Out
100 Dynamic Node
Delay(pS)

80
Input <0-15> Evaluation
60 Network

40
Clock
20

0
32 64 96 128 160 GND
Width of Evaluaon Transistor(nm) Fig. 4 Footed domino logic circuit
Fig. 2 Effect of evaluation transistor width on delay
noise in the circuit. Also due to fast switching of inverter
buffer, the power consumption will be high due to con-
Vdd Vdd
Keeper tinuous shorting of VDD and GND. These pulses at the
Transistor output can be avoided if NMOS transistor in the inverter is
Clock turned off at the time of precharge.
In proposed technique as shown in Fig. 5, transistors
MN2 and MN3 are added in the basic footed domino logic
Out for leakage reduction and noise improvement and provide
Dynamic Node
the proper stacking to the transistor in order to reduce the
contention current of the circuit. Transistor MN2 is driven
Input <0-15> Evaluation by the dynamic node N of footer transistor. Transistor MN1
Network is NMOS transistor of output inverter of the circuit which
reduces leakage power consumption during precharge
phase by stacking effect, which is not discharge though
GND but it provide the input to the MN2 transistor for
GND improvement of unity noise gain (UNG) of the circuit.
Fig. 3 Footless domino logic circuit Whenever there is a small voltage drop across MN4 due to
noise pulses, transistor MN3 provides stacking effect by
reduce the leakage current as shown in Fig. 3. This tech- making gate to source voltage of MN2 smaller. The delay
nique is called footed domino logic (FDL) (Nowak et al. element is inserted in between clock and MN4 transistor so
2004). In this technique, speed decreases as footer tran- as to reduce the overall delay of the signal. This will reduce
sistor introduces delay in the circuit. Robustness of footed the leakage power of MN2 and makes MN3 conduct less,
domino logic decreases for large fan-in gates (Dadoria hence over all power of the circuit is improved.
et al. 2016b, 2017b, c; Chun and Roger Chen 2010). During precharge phase, voltage at dynamic node is
high. Now if any of the inputs to pull down network is
high, then voltage of node N at footer will be nearly equal
3 Proposed work to voltage at dynamic node because N1 is off in precharge
mode. At this time N2 turns ON while N3 remains off due
In standard FDL as shown in Fig. 4, during precharge to low voltage at output. So leakage power consumption of
phase, the output must remain high. But when clock fre- circuit reduces and noise performance improves. By pro-
quency is very high (50–500 MHz), the voltage at the viding proper stacking with the help of ULP-ST which help
dynamic node of circuit also changes very frequently. So in improving the UNG of the circuit, reduces the power
pulses are present at the dynamic node and these pulses are consumption and enhance the speed by using FinFET
transferred at the output. So output remains high for very technology in different mode. The transistors MN3, MP4
less time during precharge phase. These pulses produce and MN2 are arrange as stack transistors and provides a

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MP1 MP2 4 Simulations results and comparisons

Clock MP3
All the simulation is performed at 32 nm technology at
temperature, i.e. 27 C. The supply voltage used in the
Out simulations is 0.9 V. The wide fan-in (2, 4, 8, 16, input)
MN1 OR gate circuit is operated at 10 MHz clock frequency. In
IN1 IN2 IN3 INn
worst case and heavy load due to the high fan-out, the
Delay Element
output capacitance load is set at 1fF. Some previous
MN2
technique are simulated with proposed technique for
comparison and analysis. And also measure the noise
immunity of the circuits quantitatively and account other
Clock MN4 MN3
circuit factors i.e. noise metric and figure of a merit.

4.1 Noise immunity metric

Few metrics have been proposed by FinFET and CMOS in

Fig. 5 ULP-ST domino logic
stacked effect in pull down network reducing the leakage
current simultaneously a proper logic level is achieved
Different domino topologies discussed in Sect. 2 along
with the proposed domino circuit are simulated on PTM
32 nm process using H-spice simulation tool. The simula-
tion is performed for 2, 4, 8 and 16 input OR gates.
In this paper, to compare various topologies, parameters
used are power consumption, propagation delay and UNG.
Figure 6 provide the proper logic achieve by the proposed
ULP-ST circuit for all input vector combination so as to
improve overall performance of the circuit.
the literature survey to compare and analyzed the noise
immunity of the dynamic gates (Tawfik and Kursun 2008)
and well-known noise-margin metric is the unity noise gain
(UNG) that is use in this paper (Peiravi and Asyaei 2013;
Lih et al. 2007). It is equal to the amplitude of input noise
that causes the equal amplitude to appear at the output.
This metric is define by
UNG ¼ fVin : Vnoise ¼ Voutput g
In this technique, a pulse noise matches cross-talk noise
at the input. The input noise can be raised by increasing the
noise pulse duration or the noise amplitude. In this paper
mainly the input noise amplitude is changed in the worst
case DC noise conditions to compare DC robustness of the
various techniques.

4.2 2 transistor sizing

The FDL, FLDL, CKD, HSD and LCR techniques are

Fig. 6 Transient characteristics of 2-input proposed domino OR gate
using HSPICE at 10 MHz
simulated to compare the results with proposed foot driven
stack transistor domino logic (FDSTDL). The width of
footer transistor N1 is set to 4 Lmin in the proposed circuit
to reduce the delay while it is set to 2 Lmin for existing
circuits where Lmin = 32 nm (channel length). The width
of identical NMOS transistors in evaluation block is taken
to be 2 Lmin. The aspect ratio (Wp/Wn) of the static
inverter is taken as 2 to compensate the mobility difference
of electrons and holes. The width of precharge transistor
and keeper transistor is set to 4 Lmin and 2 Lmin,
respectively.
OR gates are more suitable for calculating leakage
currents because in OR gates, N channel transistors are
connected in parallel in the evaluation logic while in AND
gate, the N channel transistors are connected in series
(stacked one over the other) so number of interconnects
between dynamic node and foot will be more in case of
AND gate. Leakage current and noise performance is

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Microsystem Technologies (2018) 24:3341–3348 3345

affected by a number of interconnects at the node. So in
this paper, domino OR gates are simulated in FinFET.
Tables 1, 2, 3, 4, 5 and 6 shows the overall comparison
of Average power, delay and UNG of 2, 4, 8 and 16 input
OR Gate in CMOS, SG and LP mode of FinFET technol-
ogy. From the simulation results it is observe that Tables 2,
4 and 5 for 8 and 16 inputs OR gate shows the comparison
of different parameters like average power, delay and UNG
of the domino circuits by using FinFET technology. Pro-
posed ULP-ST circuit shows maximum saving of Average
power 22.15, 23.39% in FLD, 28.36, 27.34% in HSD,
42.37, 44.84% in CKD for 8 input OR gate in SG and LP
modes of FinFET technology. Saving of delay 28.42,
18.37% in FLD, 56.83, 43.47% in FDL, 28.47, 21.37% in
HSD, 36.31, 34.19% in CKD for 8 input OR gate in SG and
LP mode of FinFET technology, respectively. Maximum
Saving of the average power by ULP-ST is up to 35.35% in
DFD and 34.39% in LCR for 8 input OR gate. For 16 input
OR gate ULP-ST circuit saves power 24.81% for DFD and
28.28% in LCR. unity noise gains (UNG) of different
existing domino logic circuits are compared with proposed
domino logic. Higher value of UNG shows better noise
immunity. For calculating UNG, noise pulse of varying
amplitude and constant width is applied at the input. The
result shows that proposed technique has higher noise
immunity as compared to existing domino techniques as
well as FinFET SG and LP mode.
The simulation results of the proposed ULP-ST domino
circuit for power dissipation and delay at the different
keeper ratios is shown in Figs. 7 and 8, respectively. The
power dissipation is significantly reduced up to 68% (16-
input OR with KPR = 1.5) with the proposed FinFET
technique when compared to the proposed MOS technique,
as shown in Fig. 7. Similarly, the delay is significantly
reduced by up to 58% (16-input OR with KPR = 1.5) for
the proposed FinFET technique with respect to the pro-
posed MOS technique, as shown in Fig. 8. The power
reduction and speed enhancement with the proposed Fin-
FET and MOS techniques are more pronounced as the
contention current increases with a large keeper transistor.
The ratio of the contention current in the proposed FinFET
circuit is more compared with the proposed MOS circuit. In
Table 7, different domino techniques are compared based
on standby power consumption for 16 input OR gate.
Standby power is calculated by applying zero input to all
the transistors in evaluation logic. It is shown in the
table that proposed technique (FULP-ST) has least stand-
by power consumption due to low transistor count.
Comparison of the average power between domino logic
style made from MOS and FinFET is done because scaling
of the technology is the prime thrust for the development of
the MOS but as the SCE came into existence the FinFET
has excellent control over the silicon fin and mitigates this
effect. From the results it is observed that the FinFET
based ULP-CCMF domino circuit shows the saving of an
average power of 16.67, 29.11% SFLD, 42.58, 44.91%
HSD, 51.22, 52.65% CKD, 21.34, 32.73% LCR, 30.56,
43.13% DFD and in the MOS based proposed domino
circuit a saving of an average power of 10.66, 20.22%
SFLD, 36.77, 36.49% HSD, 95.11, 93.33% CKD, 16.59,
23.93% LCR, 12.21, 14.44% DFD is shown for the 8 and
16 input OR gates, respectively. From the results it is
observed that the FinFET based ULP-CCMF domino cir-
cuit shows a saving of standby power of 18.79, 29.36%
SFD, 46.15, 42.11% HSD, 63.3, 61.46% CKD, 71.71,
32.11% LCR, 49.08, 29.18% DFD and in the MOS based
domino circuit proposed shows the saving of standby
power 3.42, 3.13% SFD, 43.51, 40.62% HSD, 98.3,
98.09% CKD, 14.34, 3.05% LCR, 14.08, 12.6% DFD for
the 8 and 16 input OR gates, respectively. The maximum
average power saving is observed in the CKD compared
with the proposed circuit (both MOS and FinFET based)
because the number of transistors used in the ULP-CCMF
circuit is less compared with the CKD and is due to the
stacking effect with the mirror transistor in the pull down
network.
A maximum penalty of delay of 34.7% in the MOS,
34.05% in FinFET and evaluation delay of 28.61% in the
MOS, and 18.05% in FinFET was seen compared with the
HSD for the 8 input OR gate. The delay is increased

Table 1 Comparison of domino

Topology 2 input OR gate 4 input OR gate
circuits in terms of power, delay
and UNG for 2 and 4 input OR Avg. power (lW) Delay (pS) UNG Avg. power (lW) Delay (pS) UNG
gates by using MOS technology
FDL 1.511 16.99 0.361 1.811 20.32 0.341
FLDL 1.494 10.91 0.312 1.570 11.93 0.312
CKD 1.751 23.45 0.668 2.055 30.49 0.616
HSD 1.585 9.494 0.382 1.812 13.55 0.343
LCR 1.8925 12.99 0.388 2.073 15.39 0.345
DFD 1.812 19.13 0.383 2.009 24.65 0.342
CKCCD 1.932 9.025 0.384 2.167 13.71 0.342
Proposed 1.540 12.94 0.477 1.732 15.21 0.165

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Table 2 Comparison of domino

Topology 8 input OR gate 16 input OR gate
circuits in terms of power, delay
and UNG for 8 and 16 input OR Avg. power (lW) Delay (pS) UNG Avg. power (lW) Delay (pS) UNG
gates by using CMOS
technology FDL 1.3135 32.21 0.242 1.3765 36.41 0.217
FLDL 1.3335 31.524 0.124 1.3388 32.49 0.101
CKD 1.4815 159 0.426 1.5601 174.31 0.395
HSD 1.4286 38.15 0.238 1.4705 41.75 0.213
LCR 1.5948 50.83 0.241 1.6209 52.61 0.212
DFD 1.4484 38.11 0.246 1.4823 41.76 0.219
CKCCD 1.5454 45.154 0.236 11.604 52.02 0.211
Proposed 1.3113 38.83 0.191 1.3635 452.5 0.165

Table 3 Comparison of domino

Topology 2 input OR gate 4 input OR gate
circuits in terms of power, delay
and UNG for 2 and 4 input OR Avg. power (lW) Delay (pS) UNG Avg. power (lW) Delay (pS) UNG
gates by using FiFET
technology in SG mode FDL 0.401 13.18 0.313 0.452 14.20 0.273
FLDL 0.356 10.23 0.281 0.390 10.36 0.253
CKD 0.588 20.52 0.331 0.622 20.61 0.302
HSD 0.440 8.178 0.306 0.492 7.936 0.268
LCR 0.762 11.50 0.311 0.805 11.95 0.271
DFD 0.705 15.66 0.327 0.755 16.33 0.297
CKCCD 0.662 12.97 0.354 0.822 11.93 0.317
Proposed 0.365 10.43 0.401 0.448 11.78 0.352

Table 4 Comparison of domino

Topology 8 input OR gate 16 input OR gate
circuits in terms of power, delay
and UNG for 8 and 16 input OR Avg. power (lW) Delay (pS) UNG Avg. power (lW) Delay (pS) UNG
gates by using FiFET
technology in SG mode FDL 0.561 16.99 0.242 0.811 20.32 0.217
FLDL 0.469 10.91 0.124 0.570 11.91 0.101
CKD 0.754 23.45 0.426 1.052 30.49 0.395
HSD 0.585 9.492 0.238 0.812 12.55 0.213
LCR 0.882 12.99 0.241 1.073 15.39 0.212
DFD 0.812 19.13 0.246 1.009 24.65 0.219
CKCCD 0.932 9.025 0.236 1.137 16.71 0.211
Proposed 0.530 12.94 0.281 0.632 15.21 0.265

Table 5 Comparison of domino

Topology 2 input OR gate 4 input OR gate
circuits in terms of power, delay
and UNG for 2 and 4 input OR Avg. power (lW) Delay (pS) UNG Avg. power (lW) Delay (pS) UNG
gates by using FiFET
technology in LP mode FDL 0.287 22.93 0.427 0.3178 24.45 0.401
FLDL 0.269 19.65 0.309 0.2856 19.87 0.276
CKD 0.400 40.80 0.351 0.4138 40.51 0.335
HSD 0.369 9.77 0.413 0.1839 10.56 0.404
LCR 0.305 22.97 0.397 0.3137 23.06 0.382
DFD 0.403 26.16 0.408 0.4203 27.64 0.391
CKCCD 0.269 24.49 0.425 0.2990 25.51 0.409
Proposed 0.279 21.15 0.434 0.3253 22.05 0.421

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Table 6 Comparison of domino

Topology 8 input OR gate 16 input OR gate
circuits in terms of power, delay
and UNG for 8 and 16 input OR Avg. power (lW) Delay (pS) UNG Avg. power (lW) Delay (pS) UNG
gates by using FiFET
technology in LP mode FDL 0.377 28.37 0.371 0.5012 36.32 0.343
FLDL 0.308 20.98 0.256 0.3460 20.38 0.224
CKD 0.481 44.88 0.305 0.6304 55.84 0.273
HSD 0.338 12.57 0.361 0.3604 17.91 0.329
LCR 0.344 22.03 0.322 0.4328 23.99 0.273
DFD 0.459 30.78 0.331 0.5577 27.96 0.302
CKCCD 0.344 22.08 0.379 0.4603 23.79 0.323
Proposed 0.323 21.13 0.381 0.3520 22.83 0.356

Fig. 7 Comparison of power MOS FinFET

0.3500
dissipation in MOS and FinFET
of ULP-ST circuit with different 0.3000
Power (µW)

KPR (NMOS and FinFET: 0.2500

W/L = 1, PMOS and FinFET: 0.2000
W/L = 2) 0.1500
0.1000
0.0500
0.0000
0.25 0.50 1.00 1.50 0.25 0.50 1.00 1.50 0.25 0.50 1.00 1.50 0.25 0.50 1.00 1.50

2 Input AND Gate 4 Input OR Gate 8 Input OR Gate 16 Input OR Gate

KPR

Fig. 8 Comparison of delay in MOS FinFET

MOS and FinFET of ULP-ST 40.000
circuit with different KPR 35.000
(NMOS and FinFET: W/L = 1, 30.000
PMOS and FinFET: W/L = 2) 25.000
Dely

20.000
15.000
10.000
5.000
0.000
0.25 0.50 1.00 1.50 0.25 0.50 1.00 1.50 0.25 0.50 1.00 1.50 0.25 0.50 1.00 1.50

2 Input AND Gate 4Input OR Gate 8 Input OR Gate 16 Input OR Gate

KPR

because of the increase in the resistance due to the stack
transistor in the pull down network. The average power
saving, delay and PDP between the MOS and FinFET in
the same, existing and proposed domino circuits.
According the above-mentioned discussions, the pro-
posed circuit has some advantages over the previous works
in some details as follows.
• In the proposed circuit, the difference between voltages
across the pull down network is used to provide output
voltage. Thus, the performance is improved without
robustness degradation.
• The pull-down network is disconnected from the output
inverter to decrease the propagation delay due to lower
capacitance on the dynamic node. Also, a small keeper
is sufficient to have a desired robustness.
• Voltage swing on the pull-down network is reduced
which results in lower power consumption especially in
wide fan-in gates.
• The switching threshold voltage of the proposed
domino will be approximately twice of the threshold
voltage of NMOS transistors. Therefore, noise immu-
nity of the new circuit is significantly improved,
especially as fan-in is increased.

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FinFET technology electronics design
Chun JW, Roger Chen CY (2010) A novel leakage power reduction
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pp 119–122
MOS SG mode LP mode
Dadoria AK, Khare K, Gupta TK, Singh RP (2016a) Ultra low power
FDL 0.3777 0.01528 0.01486 high speed domino logic circuit by using FiNFET technology.
Adv Electr Electron Eng 14(1):66–74
FLDL 0.3081 0.01625 0.01798 Dadoria AK, Khare K, Singh RP (2016b) Sleepy lector: a novel
CKD 0.4815 0.05726 0.0508 approach for leakage reduction in DSM technology. In:
HSD 0.2284 0.03251 0.02472 Proceedings of IEEE confluence 2016. Amity University, Noida,
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LCR 0.3445 0.03596 0.03307
Dadoria AK, Khare K, Gupta TK, Singh RP (2017a) Ultra-low power
DFD 0.4599 0.02831 0.03159 FinFET-based domino circuits. Int J Electron 104:952–967
CKCCD 0.3446 0.03751 0.03752 Dadoria AK, Khare K, Gupta TK, Khare N (2017b) Integrating sleep
Proposed ULP-ST 0.3832 0.01343 0.01537 and pass transistor logic for leakage power reduction in FinFET
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