NuMicro

Introduction to Cortex-M0
A Leading MCU Platform Provider
ARM Architecture Roadmap

2
Reference from ARM
Cortex-M0 Function Block
• Cortex-M0 processor includes
- Cortex-M0 processor core
- Nested Vectored Interrupt Controller (NVIC)
Nuvoton provider
- System Timer (SysTick)
Nested AHB-Lite
Vectored Cortex-M0 interface
Interrupts Interrupt Processor
Controller core ROM
(NVIC)
RAM

Peripherals
System Timer
(SysTick)
Cortex-M0
6
Cortex-M0 Architecture Overview
• ARMv6-M (which is a subset of ARMv7-M, upward
compatible)
• It supports only the Thumb instruction set. No Interworking code is
required.
• Total are 56 instructions. 6 are 32-bit length, the others are 16-bit
length
 32-bit instructions : BL, DMB, DSB, ISB, MRS, MSR

• Supports byte (8-bit), halfword (16-bit) and word (32-bit)

data types, each must be accessed with natural alignment.

7
Cortex-M0 Architecture Overview – cont.
• Processor modes are Thread and Handler.
• Always in privilege
• Supports hardware key context state saving and restoring (Need not
Assembly coding for ISR).
• Built-in timer and interrupt controller
• NVIC, Systick
• Memory mapped I/O
• Use same instructions to access memory and registers
• Ex : LDR, STR
8
Memory Model
• 32-bit address space
• Virtual memory is not supported in ARMv6-M.
• Instruction fetches are always halfword-aligned
• Data accesses are always naturally aligned
• Ex : word at address A : A, A+1, A+2 and A+3.

9
System Memory Map
0xE000_EFFF
0xE000_E000
Cortex M0 System Register System
Reserved
0x501F_FFFF
AHB peripherals
0x5000_0000
Reserved Peripheral
0x401F_FFFF
APB peripherals
0x4000_0000
Reserved
0x2000_3FFF
0x2000_0000
16KB RAM SRAM
Reserved
0x0010_1FFF
ISP Loader Program Memory (8KB LDROM)
0x0010_0000
Reserved Code
0x0001_FFFF
Application Program Memory (128KB APROM)
0x0000_0000
10
Memory Setting in Keil

Code region

SRAM region

Program entry point

11
System Timer - SysTick
• SysTick provides a simple, 24-bit clear-on-write,
decrementing, wrap-on-zero counter.
• When enabled, the timer will count down. When the
counter transitions to zero, the COUNTFLAG status bit is set.
• The reference clock can be the core clock or an external
clock source.
SysTick request
CPU clock Reference when counter
clock 24-bit reaches 0
down count counter
external clock

Reload counter
15
Exception Model – cont.
• Exceptions defined in Cortex-M0
Exception
Exception Priority level
number
1 Reset -3
2 NMI -2
Cortex M0 Core 3 HardFault -1
Exception
11 SVCall configured by register SHPR2
14 PendSV configured by register SHPR3
15 SysTick configured by register SHPR3
External Interrupt
16 configured by register NVIC_IPRx
(0)
IP Exception … … …
External Interrupt
47 configured by register NVIC_IPRx
(31)

19
Exception Model – cont.
• Exception priorities and pre-emption
• Lower numbers (0-3) take higher precedence
• If multiple exceptions have the same priority number, the pending
exception with the lowest exception number takes precedence.
• Only exceptions with a higher priority (lower priority number) can pre-
empt an active exception.

20
Context Saving and Restoring
• Key context saving and restoring
• Using full-descending stack format (decremented immediately before
storing, incremented after reading)
• xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0
SP’ H
xPSR
ReturnAddress Loaded into PC on exception return
LR
r12
r3
r2
r1
SP r0
L
21
Nested Vectored Interrupt Controller (NVIC)
• Supports up to 32 (IRQ[31:0]) discrete interrupts which can
be either level-sensitive or pulse-sensitive.
• NVIC interrupts can be enabled/disabled, pended/un-
pended and prioritized by setting NVIC control registers

Interrupt Exception Exception 1

interrupt 0 number number Exception 2
: NVIC Cortex-M0
Interrupt 31

Exception 47

System Vector Table

interrupts

22
Summary
• Cortex-M0 is always in privileged mode and supports Thumb
instruction only.
• Supports key context saving and restoring
• xPSR, return address, r14, r12, r3, r2, r1, r0
• System address map is defined in advance.
• Code, SRAM, Peripheral, System
• Contains SysTick and NVIC

29
 NuMicro
Cortex-M0 NUC029 Series
A Leading MCU Platform Provider
 NuMicro® M0 Microcontroller introduction 5V MCU
New
Platform
Ultra Low Power
512 KB
M031 NUC029 M251 Series
1.8V Series 5V Series M252 Series
256 KB

128 KB
Nano130
M0564 NUC126 NUC240 Nano120
M0518 NUC125 NUC220 Nano110
NUC140 Nano130
M0516 NUC121 NUC140 Nano100
64 KB
NUC130 Nano110
M058 NUC123
NUC131 NUC240
M054 NUC120
M052 NUC230 Nano103
32 KB

Mini57 USB Crystal-less CAN x 1 CAN x 2

Mini55 Nano112 Nano102
16KB Mini51

General Purpose Ultra Low Power

Entry Level Standby current < 1uA
Base Advance 31
USB CAN LCD Ultra-Low Power
Advanced Line - M051 Series Portfolio
Flash All Operating temp. : -40 ~ 85/105 °C
256 KB
M0564LG4AE M0564SG4AE M0564VG4AE • HIRC 48MHz
128 KB • PWM up to 144MHz
• Hardware Divider
M0564LE4AE M0564SE4AE
• VAI interface
64 KB
M0518LD2AE M0518SD2AE • 8K SRAM
• Up to 6 UARTs
M0516ZDN/DE M0516LDN/DE • 24 channels PWM
32 KB
M0518LC2AE M0518SC2AE
M058SZAN M058SLAN M058SSAN • Low Pin Count
Package TSSOP20
M058ZDN/DE M058LDN/DE
16 KB
M054ZDN/DE M054LDN/DE
8 KB
M052ZDN/DE M052LDN/DE

QFN33 LQFP48 LQFP64 LQFP100 32

 5V - NUC029 Series Portfolio
Flash
USB2.0 FS device
• CPU speed 72Mhz
256 KB/20K • Vbat pin
New NUC029LGE NUC029SGE • Hard Divider

128 KB/16K Products • CPU speed 72Mhz

NUC029LEE NUC029SEE • RTC
• ADC 1MSPS
• Up to 9-ch PDMA
68 KB/8K NUC029LDE NUC029SDE
• Up to 12-ch PWM
• 4-ch 32bit Timer
NUC029NAN • Up to 4-ch UART
64 KB/4K
NUC029ZAN NUC029LAN • Up to 3-ch ACMP
• Up to 8-ch ADC
• Up to 4K SRAM
32 KB/4K NUC029TAN

16 KB/2K NUC029FAE • Up to 5-ch PWM

QFN33(4x4) QFN48
TSSOP20 LQFP64(7x7)
QFN33(5x5) LQFP48(7x7) 33
NUC029 Series Features
System
• Arm® Cortex® -M0, CPU speed up to 72 MHz
• 16 ~ 256 KB Flash / 2 ~ 20 KB SRAM
• Supply voltage 2.5 ~ 5.5V
• Operating temperature -40 ~ 105 °C
Peripherals
• UART, SPI, I2C, LIN interface
• USCI support to configure as UART, SPI, I2C
• Up to 12-channels 144MHz resolution PWM,
with programmable dead-zone
• 16/8 bit EBI
Analog
• Up to 15-channels high performance 12bit ADC
• Up to 1MSPS 12bit ADC
• Build-in analog comparator x2
• Support BOD/LVR function
Others
• Support crystal-less USB 2.0 FS device
• HID, MSD, VCOM
• Support Hardware Divider
34
NUC029FAE/ZAN/TAN/NAN/LAN Feature
The NuMicro NUC029FAE/ZAN/TAN/NAN/LAN is embedded with the Cortex™-M0 core
running up to 50 MHz (NUC029FAE: 24MHz) and features 64K/32K/16K bytes flash, 4K bytes SRAM, and
4 Kbytes loader ROM for the ISP. It is also equipped many system level peripheral functions, such as
Timers, Watchdog Timer (WDT), Window Watchdog Timer (WWDT), UART, SPI, I2C, PWM, GPIO, 800
kSPS high speed 12-bit ADC, Low Voltage Reset Controller and Brown-out Detector.

• Core • Power Management and Robustness

• Arm® Cortex®-M0 MCU • 2.5V to 5.5V wide operating voltage
• Frequency up to 50 MHz • -40℃ ~ +105 ℃ Industrial Temperature

• Memories
• Flash/SRAM Optional • Differentiated Features
16/32/64 KB Flash & SRAM 2/4 KB • Analog Comparator

NUC029
• Communication Interfaces
• Up to 8-ch PWM • Analog Features
• Up to UARTx4, SPI/I2Cx2 • 8-channel 12-bit ADC, up to 800 KSPS.
• 16/8 bit EBI interface
35
NUC029FAE/ZAN/TAN/NAN/LAN Function Blocks

36
NUC029LDE/SDE Feature
The NuMicro NUC029LDE/SDE is embedded with the Cortex™-M0 core running up to 50 MHz
and features 68 Kbytes flash, 8K bytes SRAM, and 4 Kbytes loader ROM for the ISP. It is also equipped with
plenty of peripheral devices, such as Timers, Watchdog Timer (WDT), Window Watchdog Timer (WWDT),
UART, SPI, I2C, PWM, GPIO, LIN, 1000 kSPS high speed 12-bit ADC, Low Voltage Reset Controller and
Brown-out Detector.
• Core
• Arm® Cortex®-M0 MCU
• Power Management and Robustness
• Frequency up to 50 MHz
• 2.5V to 5.5V wide operating voltage
• -40℃ ~ +105 ℃ Industrial Temperature
• Memories
• Flash 68 KB/SRAM 8 KB

• Communication Interfaces • Analog Features

• Up to 12-ch PWM NUC029LEE/SEE • 8-channel 12-bit ADC, up to 1MSPS.
• Up to UARTx4, SPIx1, I2Cx2
• Built-in LINx3
• Up to GPIOx56
37
NUC029LDE/SDE Function Blocks

38
NUC029LEE/SEE Feature
NUC029LEE/SEE which is a 32-bit Microcontroller based on Arm® Cortex® M0 Core can operate
at 72 MHz with wide supply voltage from 2.5V to 5.5V as well as -40oC to 105oC temperature range. It
integrates 12-channels 12-bit ADC that up to 1000K SPS conversion rate, a 16/8 bit EBI interface to
support display, and support USB 2.0 full-speed device function.

• Core
• Arm® Cortex®-M0 MCU
• Power Management and Robustness
• Frequency up to 72MHz
• 2.5V to 5.5V wide operating voltage
• -40℃ ~ +105 ℃ Industrial Temperature
• Memories
• Flash 128 KB/SRAM 16 KB

• Differentiated Features
• Independent power supply for RTC
• Communication Interfaces
• Up to 6-ch PWM NUC029
• Up to UARTx3, SPI/I2Cx2 • Analog Features
• 16/8 bit EBI interface • 12-channel 12-bit ADC, up to 1MSPS.
• USB 2.0 full-speed device
39
NUC029LEE/SEE Function Blocks

40
 NUC029LGE/SGE Feature
 NUC029LGE/SGE which is a 32-bit Microcontroller based on Arm® Cortex® M0 Core can operate at 72 MHz with
wide supply voltage from 2.5V to 5.5V as well as -40oC to 105oC temperature range. It integrates 15-channels
12-bit ADC that up to 800KSPS conversion rate, a 16/8 bit EBI interface to support display, have voltage
adjustable interface (up to 6 IOs) with supply VDDIO from 1.8V to 5.5V, and support USB 2.0 full-speed device
function (Crystal-less).

• Core
• Power Management and Robustness
• Arm® Cortex®-M0
MCU
• 2.5V to 5.5V wide operating voltage
• Frequency up to 72MHz
• -40℃ ~ +105 ℃ Industrial Temperature

• Memories
• Flash 256 KB/SRAM 20 KB • Differentiated Features
• Independent power supply for RTC
• Communication Interfaces • VAI (Voltage Adjustable Interface)
• USCIx3 (UART, I2C, SPI)
NUC029
• Up to 12-ch PWM • Analog Features
• Up to UARTx3, SPI/I2Cx2/I2Sx2 • Up to 15-channel 12-bit ADC, up to
• 16/8 bit EBI interface 800KSPS.
• USB 2.0 full-speed device
41
(Crystal-less)
NUC029LGE/SGE Function Blocks
Memory Speed Up RTC / PWM / Timer Analog Interface

APROM LDROM RTC (VBAT)

PDMA 5-ch 12-bit ADC 15-ch
256 KB 4 KB
ARM Watchdog Timer
®
Cortex -M0
DataFlash SRAM Hardware Divider
72 MHz
Configurable 20 KB
Timer/PWM x 4
Analog
SPROM CRC Comparator x 2
PWM 12-ch
2 KB

AHB Bus Bridge APB Bus

Power Control Clock Control Connectivity I/O Ports

High Speed Low Speed UART x 3

LDO 1.8V Oscillator(HIRC) Oscillator(LIRC) General Purpose I/O
22.1184 MHz 10 kHz
SPI/I²S x 2
High Speed Low Speed
POR LVR BOR Crystal Osc.(HXT) Crystal Osc.(LXT) I²C x 2 External Interrupt
4 ~ 24 MHz 32.768 kHz

High Speed USCI x 3

VREF External Bus
(2.048V/2.56V/ Oscillator(HIRC48) PLL
48 MHz USB 2.0 FS Interface
3.072V/4.96V)
(Crystal-less)
42
NUC029 Selection Guide

ISP ROM (KB)

Connectivity

ADC(12-Bit)
SRAM (KB)
Flash (KB)

Package
Divider
PDMA

ACMP
Timer

PWM
Part

CPU

CRC

RTC
LXT
PLL
I/O

EBI
USB FS
USCI*

UART
Number

LIN
SPI

I2C
I2S
NUC029FAE 16 2 24 2 17 2 3 - - 1 1 1 - - - - - - √ - 2 - 4 (10-bit) TSSOP20

NUC029TAN 32 4 50 4 24 4 5 - - 2 1 2 - - - - - √ - - 3 √ 5 QFN33*

NUC029ZAN 64 4 50 4 24 4 5 - - 2 1 2 - - - - - √ - - 3 √ 5 QFN33

NUC029NAN 64 4 50 4 40 4 8 - - 2 2 2 - - - √ - √ - - 4 √ 8 QFN48

NUC029LAN 64 4 50 4 40 4 8 - - 2 2 2 - - - √ - √ - - 4 √ 8 LQFP48

NUC029LDE 68 8 50 4 42 4 12 - - 4 1 2 - 3 - - - √ - - - - 8 LQFP48

NUC029SDE 68 8 50 4 56 4 12 - - 4 1 2 - 3 - - - √ - - - - 8 LQFP64*

NUC029LEE 128 16 72 8 31 4 4 9 - 2 1 2 - 2 1 - √ √ √ √ - - 10 LQFP48

NUC029SEE 128 16 72 8 45 4 6 9 - 3 2 2 - 3 1 √ √ √ √ √ - - 12 LQFP64*

NUC029LGE 256 20 72 4 35 4 10 5 3 3 2 2 2 - 1 √ √ √ √ √ 2 V 9 LQFP48

NUC029SGE 256 20 72 4 49 4 12 5 3 3 2 2 2 - 1 √ √ √ √ √ 2 V 15 LQFP64*

43
NUC029 Series Naming Rule

NUC 029 T D E
Temperature
N - 40℃ ~ +85℃
E - 40℃ ~ +105℃

Package
F TSSOP20 4.4x6.5 (mm)
Flash Size
T QFN33 4x4 (mm)
A < 68K
Z QFN33 5x5 (mm)
D 68K
N QFN48 7x7 (mm)
E 128K
L LQFP48 7x7 (mm)
G 256K
S LQFP64 7x7 (mm)
44
ARM Cortex-M0 Function Block Diagram
4 Break Point
2 Watchpoint

Cortex-M0 components
Cortex-M0 processor Debug
Interrupts Nested
Cortex-M0 Breakpoint
Vectored
and
Interrupt Processor Watchpoint
Controller core unit
(NVIC)

Wakeup
Interrupt Debug
Controller Bus matrix Debugger
Access Port
(WIC) interface
(DAP)

AHB-Lite interface Serial Wire or

JTAG debug port

45
System Memory Map
0xE000_EFFF
0xE000_E000
Cortex M0 System Register System
Reserved
0x501F_FFFF
AHB peripherals
0x5000_0000
Reserved Peripheral
0x401F_FFFF
APB peripherals
0x4000_0000
Reserved
0x2000_3FFF
0x2000_0000
16KB RAM SRAM
Reserved
0x0010_1FFF
ISP Loader Program Memory (8KB LDROM)
0x0010_0000
Reserved Code
0x0001_FFFF
Application Program Memory (128KB APROM)
0x0000_0000
46
 Power Management (1/2)

• Normal Run Mode

• Flexible system clock source selection
• All peripherals clock can be turned off individually.
• Sleep Mode (IDLE Mode)
• CPU halt, peripheral is probably under running which depends on your
application
• Deep Sleep Mode (Power Down Mode)
• CPU & peripheral are all halt
47
Power Management (2/2)

• Idle mode
SYS_UnlockReg();
CLK_Idle();

• PowerDown mode
SYS_UnlockReg();
PowerDownFunction();

48
 System Reset
• Hardware Reset
• The Power-On Reset
• nRESET pin Reset
• Watchdog Time Out Reset
• Low Voltage Detected Reset
• Brown-Out-Detected Reset
• Software Reset
• CPU_RST
“RSTSRC” register identify chip’s reset source from last operation
 Just only reset CPU & flash controller
 SYS_UnlockReg(); SYS_ResetCPU();
• CHIP_RST
 To reset the whole chip like “Power-on reset”
 SYS_UnlockReg(); SYS_ResetChip();
• MCU_RST
 To reset the whole chip
49
 SYS_UnlockReg(); NVIC_SystemReset();
RSTSRC (System Reset Source Register)
Register Address R/W Description Reset Value

RSTSRC 0x5000_0004 R/W System Reset Source Register 0x0000_00xx

These bits are cleared by writing 1 to itself

7 6 5 4 3 2 1 0

RSTS_CPU Reserved RSTS_SYS RSTS_BOD RSTS_LVR RSTS_WDT RSTS_RESET RSTS_POR

RSTS_CPU Power-on reset

“Reset Signal” from the /RESET Pin Reset

Cortex® -M0 kernel
Watchdog Reset

Brown Out Reset Low Voltage Reset

50
Peripheral IP Reset

• Every peripheral has corresponded reset register

• “SYS_IPRST0”, “IPRSTC1” & “PRSTC2”register had defined the
corresponded peripheral asynchronous reset signal

52
IPRSTC2(Peripheral Reset Control Register 1 )
Register Offset R/W Description Reset Value

IPRSTC2 GCR_BA+0x08 R/W Peripheral Reset Control Register 2 0x0000_0000

31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

Reserved EBI_RST PDMA_RST CPU_RST CHIP_RST

53
IPRSTC2(Peripheral Reset Control Register 2 )
Register Offset R/W Description Reset Value

IPRSTC2 GCR_BA+0x0C R/W Peripheral Reset Control Register 2 0x0000_0000

31 30 29 28 27 26 25 24

USBD_RST Reserved
Reserved ADC_RST

23 22 21 20 19 18 17 16

Reserved PWM45_RST PWM03_RST Reserved UART2RST UART1RST UART0RST

15 14 13 12 11 10 9 8

Reserved SPI1RST SPI0RST Reserved I2C1_RST I2C0_RST

7 6 5 4 3 2 1 0

Reserved TMR3RST TMR2RST TMR1RST TMR0RST GPIORST Reserved

•Set these bit “1” will generate asynchronous reset signal to the correspond IP.
•User need to set bit to “0” to release IP from the reset state
54
 Clock Control

• Clock Sources Control

• PWRCON: Enable/Disable LIRC, HIRC, LXT and HXT output.
• PLLCON: Enable/Disable PLL output.
• CLKSTATUS : Reports clock status.
• IP Clock Control
• AHBCLK, APBCLK(0~1) : Enable/Disable individual IP clock.
• CLKSEL(0~3) : Select IP clock source.
• CLKDIV0(0~1) : Set IP clock divider.
55
Clock System

56
Clock Control

57
IRC TRIM (SYS_IRCTCTL)
• SYS_IRCTCTL : IRC Trim Control Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
CLKERR_
Reserved
STOP_EN
7 6 5 4 3 2 1 0
TRIM_RETRY_CNT TRIM_LOOP Reserved TRIM_SEL

• [1:0] TRIM_SEL : Trim Frequency Selection

This field indicates the target frequency of internal 22.1184 MHz
high speed oscillator will trim to precise 22.1184MHz or 24MHz
automatically.
00 = HIRC auto trim function Disabled.
01 = HIRC auto trim function Enabled and HIRC trimmed to
22.1184 MHz.
58
10 = HIRC autotrim function Enabled and HIRC trimmed to 24 MHz.
HIRC TRIM (SYS_HIRCTCTL)
• SYS_HIRCTCTL : HIRC Trim Control Register
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved Boundary
15 14 13 12 11 10 9 8

Reserved BOUNDEN CESTOPEN

7 6 5 4 3 2 1
RETRYCNT LOOPSEL Reserved FREQSEL

• [1:0] FREQSEL : Trim Frequency Selection

This field indicates the target frequency of 48 MHz internal
high speed RC oscillator (HIRC) auto trim.
00 = Disable HIRC auto trim function.
01 = Enable HIRC auto trim function and trim HIRC to 48
59
MHz.
 NuMicro NVIC

• NVIC (Nested Vectored Interrupt Controller)

• An integrated part of the Cortex-M0 processor
• It supports 32 peripheral interrupts input
• it supports NMI( Nonmaskable Interrupt) input
• It supports “Tail Chaining” & “Late Arrival”
• Interrupt handler follows the CMSIS coding rule

60
C ISR Function Call Name

61
 General Purpose I/O Controller
• GPIO type
• Quasi-bidirectional
• Push-Pull output
• Open-Drain output
• Input only with high impendence
• Configurable default I/O mode of all pins after reset by Config0[10] setting
• 0 : all GPIO pins in input tri-state mode after chip reset
• 1 : all GPIO pins in Quasi-bidirectional mode after chip reset
• Support GPIO interrupt for each I/O PIN
• Level trigger or Edge trigger
 Input Mode

• Just input mode

• Output is tri-state ( high impedance) without drive capability
Push-Pull Output

CMOS Output
VDD

Port Pin

Port Latch N
Data

Input Data
Open-Drain Output

• Only NMOS sink current capability

Port Pin

Port Latch N
Data

Input Data
 Quasi-bidirectional

• Supports digital output and input at the same time

VDD

2 CPU
P P Very P
Clock Delay Strong
Weak
Weak

Port Pin

Port Latch N
Data

Input Data
PWRCON Register (Bit Field Definition)
31 30 29 28 27 26 25 24

Reserved

23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8

Reserved OSC48M_EN PD_WAIT_CPU

Reserved

7 6 5 4 3 2 1 0

PWR_DOWN_EN PD_WU_STS PD_WU_INT_EN PD_WU_DLY OSC10K_EN OSC22M_EN XTL32K_EN XTL12M_EN

/********************* CLK PWRCON Bit Field Definitions **********************/

#define CLK_PWRCON_PD_WAIT_CPU_Msk
#define CLK_PWRCON_PWR_DOWN_EN_Msk
#define CLK_PWRCON_PD_WU_STS_Msk
#define CLK_PWRCON_PD_WU_INT_EN_Msk
#define CLK_PWRCON_PD_WU_DLY_Msk
#define CLK_PWRCON_OSC10K_EN_Msk
#define CLK_PWRCON_OSC22M_EN_Msk
#define CLK_PWRCON_IRC22M_EN_Msk
#define CLK_PWRCON_XTL32K_EN_Msk
#define CLK_PWRCON_XTL12M_EN_Msk
(1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) /*!< CLK PWRCON:
(1ul << CLK_PWRCON_PWR_DOWN_EN_Pos)
(1ul << CLK_PWRCON_PD_WU_STS_Pos)
(1ul << CLK_PWRCON_PD_WU_INT_EN_Pos)
(1ul << CLK_PWRCON_PD_WU_DLY_Pos)
(1ul << CLK_PWRCON_OSC10K_EN_Pos
(1ul << CLK_PWRCON_OSC22M_EN_Pos)
(1ul << CLK_PWRCON_IRC22M_EN_Pos
(1ul << CLK_PWRCON_XTL32K_EN_Pos
(1ul << CLK_PWRCON_XTL12M_EN_Pos
Group Registers for fixed CLK_BA
BaseAddr (CLK_T Data Type)
Register Offset

typedef struct { PWRCON CLK_BA+0x00

__IO uint32_t PWRCON; AHBCLK CLK_BA+0x04

__IO uint32_t AHBCLK; APBCLK CLK_BA+0x08
__IO uint32_t APBCLK; CLKSTATUS CLK_BA+0x0C
__IO uint32_t CLKSTATUS;
CLKSEL0 CLK_BA+0x10
__IO uint32_t CLKSEL0;
CLKSEL1 CLK_BA+0x14
__IO uint32_t CLKSEL1;
__IO uint32_t CLKDIV; CLKSEL2 CLK_BA+0x1C

__IO uint32_t CLKSEL2; CLKDIV CLK_BA+0x18

__IO uint32_t PLLCON; PLLCON CLK_BA+0x20
__IO uint32_t FRQDIV; FRQDIV CLK_BA+0x24
__IO uint32_t APBCLK1;
__IO uint32_t CLKSEL3;
__IO uint32_t CLKDIV1;
} CLK_T;
76
 To Control Register
#define AHB_BASE ((uint32_t)0x50000000)
#define CLK_BASE (AHB_BASE + 0x00200)
#define CLK ((CLK_T *) CLK_BASE)

AHB Modules Space (0x5000_0000 – 0x501F_FFFF)

0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers

0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers

0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers

0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers

0x5000_8000 – 0x5000_BFFF PDMA_BA SRAM_APB DMA Control Registers

0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers

/* Enable Internal RC 22.1184MHz clock */

CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
77
 Cortex-M0 Core Registers Access
(core_cm0.h)
Function Definition Core Register Description

void __enable_irq (void) PRIMASK = 0 Global Interrupt enable (using the instruction CPSIE i)

void __disable_irq (void) PRIMASK = 1 Global Interrupt disable (using the instruction CPSID i)

void __set_PRIMASK
PRIMASK = value Assign value to Priority Mask Register (using the instruction MSR)
(uint32_t value)

uint32_t __get_PRIMASK
return PRIMASK Return Priority Mask Register (using the instruction MRS)
(void)

void __set_CONTROL
CONTROL = value Set CONTROL register value (using the instruction MSR)
(uint32_t value)

uint32_t __get_CONTROL
return CONTROL Return Control Register Value (using the instruction MRS)
(void)

void __set_PSP (uint32_t PSP =

Set Process Stack Pointer value (using the instruction MSR)
TopOfProcStack) TopOfProcStack

uint32_t __get_PSP (void) return PSP Return Process Stack Pointer (using the instruction MRS)

void __set_MSP (uint32_t MSP =

Set Main Stack Pointer (using the instruction MSR)
TopOfMainStack) TopOfMainStack

uint32_t __get_MSP (void) return MSP Return Main Stack Pointer (using the instruction MRS)
78
Cortex-M0 Instruction Access
Function Name CPU Instruction Description

void __WFI (void) WFI Wait for Interrupt

void __WFE (void) WFE Wait for Event

void __SEV (void) SEV Set Event

void __ISB (void) ISB Instruction Synchronization Barrier

void __DSB (void) DSB Data Synchronization Barrier

void __DMB (void) DMB Data Memory Barrier

uint32_t __REV (uint32_t value) REV Reverse byte order in integer value.

Reverse byte order in unsigned short

uint32_t __REV16 (uint16_t value) REV16
value.
Reverse byte order in signed short
sint32_t __REVSH (sint16_t value) REVSH
value with sign extension to integer.

79
NVIC Setup Function Call
Function Name Parameter Description
void NVIC_SetPriorityGrouping (uint32_t Set the Priority Grouping (Groups .
Priority Grouping Value
PriorityGroup) Subgroups)
void NVIC_EnableIRQ (IRQn_Type IRQn) IRQ Number Enable IRQn
void NVIC_DisableIRQ (IRQn_Type IRQn) IRQ Number Disable IRQn
uint32_t NVIC_GetPendingIRQ (IRQn_Type
IRQ Number Return 1 if IRQn is pending else 0
IRQn)
void NVIC_SetPendingIRQ (IRQn_Type IRQn) IRQ Number Set IRQn Pending
void NVIC_ClearPendingIRQ (IRQn_Type IRQn) IRQ Number Clear IRQn Pending Status
void NVIC_SetPriority (IRQn_Type IRQn,
IRQ Number, Priority Set Priority for IRQn
uint32_t priority)
uint32_t NVIC_GetPriority (IRQn_Type IRQn) IRQ Number Get Priority for IRQn
uint32_t NVIC_EncodePriority (uint32_t IRQ Number, Priority Group,
Encode priority for given group,
PriorityGroup, uint32_t PreemptPriority, Preemptive Priority, Sub
preemptive and sub priority
uint32_t SubPriority) Priority
IRQ Number, Priority,
NVIC_DecodePriority (uint32_t Priority, uint32_t pointer to Priority Group,
Decode given priority to group,
PriorityGroup, uint32_t* pPreemptPriority, pointer to Preemptive
preemptive and sub priority
uint32_t* pSubPriority) Priority, pointer to Sub
Priority
void NVIC_SystemReset (void) (void) Resets the System

80
 NuMicro
NUC029 SDK
A Leading MCU Platform Provider
Disc Content Introduction

82
Software Installation

Double Click “autorun.exe”

83
Step 1. Install the Keil uVision4

1. Keil RVMDK EV Version

2. Install Keil RVMDK EV Version
The Keil uVision4 evaluation version (FREE) can be downloaded
from Keil website www.keil.com
84
Step 2. Install Nu-Link Keil Driver

The “Nu-Link Driver” can be

Note : Please close the Keil application downloaded from nuvoTon website
program when installing Nu-Link Keil driver. www.nuvoton.com
85
Step 3. Copy NUC029 Series BSP

1. BSP Software Library

2. NUC029xEE_Series_BSP_CMSIS
_V3.00.001
Note : Please use the default destination folder.
C:\Nuvoton\BSP Library\
86
Virtual COM Port Function Switch

Switch Pin Disable VCOM Enable VCOM

Number Mode Mode
1 Off On
2 Off On
3 Off On
4 Off On

88
 Resource
• BSP (Board Support Package):
- https://www.nuvoton.com/opencms/system/modules/com.thesys.opencms.nuvoton/pages/download/download.jsp?file=http://www.nuv
oton.com/hq/resource-download.jsp?tp_GUID=SW0120180713155423&version=V3.00.001

• TRM (Technical Reference Manual):

- http://www.nuvoton.com/resource-files/TRM_NUC029xEE_EN_Rev1.01.pdf

• Data Sheet:
- http://www.nuvoton.com/resource-files/DS_NUC029xEE_EN_Rev1.00.pdf

• NuTiny-SDK_NUC029SEE_V1.01:
- Schematic:
 https://www.nuvoton.com/opencms/system/modules/com.thesys.opencms.nuvoton/pages/download/download.jsp?file=http://w
ww.nuvoton.com/hq/resource-download.jsp?tp_GUID=HL0320181017105843&version=1.01

• DVD Content:
- http://www.nuvoton.com/NuMicroDVD/
89
Thank you!