Microcontroller system architecture

SYS3041
Part 2

F. CRISON
V2.0
 Introduction to ARM processors

2
ARM processor
⚫ ARM: development and IP licensing
⚫ 32-bit and 64-bit RISC architecture
⚫ ARM: Advanced RISC Machines
⚫ ARM families
– Cortex-A: high performance to support OS
– Cortex-R: real-time (deterministic behavior)
– Cortex-M: microcontroller (low power requirement)

3
4
5
ARM Cortex-M0+
⚫ ISA (instruction set architecture)
– Thumb/Thumb-2 subset
– Small instruction set (56 instructions)
– Most are 16-bit (6 are 32-bit)
⚫ Pipeline: 2-stage
– Fetch and pre-decode
– Main decode and execute
 Lower consumption

⚫ Ultra low-power sleep modes (+ active mode)

6
 Cortex-M0+ functional block diagram

7
Source: ARM
 STM32L0x3
32-bit ultra-low-power MCU

8
 STM32L0x3 architecture
9
Source: STMicroelectronics
⚫ Glossary
– ADC: analog to digital converter
– AHB: advanced high-performance bus
– APB: advanced peripheral bus
– CRC: cyclic redundancy check
– DAC: digital to analog converter
– DMA: direct memory access
– GPIO: general purpose input/output
– I2C: inter-integrated circuit
– MIF: memory interface
– NVM: non-volatile memory
– RTC: real time clock
– SPI: serial peripheral interface
– SRAM: static read only memory
– USART: universal synchronous/asynchronous receiver transmitter

10
 STM32L0x3 electrical characteristics

STM32L0x3 power supply scheme

11
12
13
 Reset
⚫ Source: hardware or software

Recommended NRST
pin protection

⚫ On reset
– SP loaded with the value from address 0x00000000
– PC loaded with the value from address 0x00000004
14
 Clocks
⚫ Four primary sources
– HSI16 (high-speed internal) oscillator clock
⚫ Internal 16 MHz RC oscillator
⚫ + Clock source at low cost (no external components)
⚫ - Less accurate than an external crystal oscillator
– HSE (high-speed external) oscillator clock
– PLL clock
– MSI (multispeed internal) oscillator clock (RC oscillator)
⚫ Two secondary clock sources
– 37 kHz low speed internal RC (LSI RC)
– 32.768 kHz low speed external crystal (LSE crystal)

15
16
 GPIO
⚫ Output: push-pull or open drain + pull-up/down
⚫ Input: floating, pull-up/down, analog

17
 GPIO

18
 STM32 Nucleo-64 board

19
Source: STMicroelectronics (UM1724 STM32 Nucleo-64 board)
 Programming ARM Cortex-M0+
⚫ Core registers

20
⚫ R0-R12
– General-purpose registers
⚫ Stack Pointer
– MSP
⚫ Main Stack Pointer
⚫ Active “SP” if CONTROL.B[1]=0
 Thread mode in a multitasking OS

– PSP
⚫ Process Stack Pointer
⚫ Active “SP” if CONTROL.B[1]=1
 Handler mode in a multitasking OS

⚫ LR (=R14)
– Link Register
– Return addr. for subroutines, functions and exceptions.
21
 ⚫ PC
– Program Counter
– Loaded with value from address 0x00000004 on reset
⚫ PSR
– Program Status Register: APSR, IPSR or IPSR
– APSR
⚫ Application Program Status Register
Bits Name Function
[31] N Negative flag Set to 1 when the result of the operation was negative, cleared to 0 otherwise
[30] Z Zero flag Set to 1 when the result of the operation was zero, cleared to 0 otherwise
[29] C Carry or borrow flag Set to 1 when the operation resulted in a carry, cleared to 0 otherwise
Addition is greater than or equal to 232, subtraction is positive or zero, result of a shift or rotate instruction
[28] V Overflow flag Set to 1 when the operation caused overflow, cleared to 0 otherwise
Sign of the result, in bit[31], does not match the sign of the result had the operation been performed
Ex: adding two negative values results in a positive value
[27:0] - Reserved

22
 – IPSR
⚫ Interrupt Program Status Register
Bits Name Function
[31:6] -
[5:0] Exception number 0 = Thread mode.
1 = Reserved.
2 = NMI (NonMaskable Interrupt)
3 = HardFault (hardware or software error, ex:undefined instruction,bus error,…)
4-10 = Reserved.
11 = SVCall (Supervisor Call, in OS, applications can use SVC instruction to access OS kernel functions and drivers)
12, 13 = Reserved.
14 = PendSV (In an OS environment, use PendSV for context switching when no other exception is active)
15 = SysTick (system timer, SysTick is a 24-bit count-down timer, exception generated when it reaches zero.)
16 = IRQ0 (Interrupt request)
… (exception signaled by a peripheral, or generated by a software request)
47 = IRQ31.
48-63 = Reserved

– EPSR
⚫ Execution Program Status Register
Bits Name Function
[31:25] - Reserved
[24] T Thumb state bit
Normally set to 1 (Cortex-M0 processors only support Thumb state)
If cleared, a HardFault exception will be generated in the next instruction execution
[23:0] - Reserved

23
⚫ PRIMASK
– Priority Mask Register
Bits Name Function
[31:1] - Reserved
[0] PM Prioritizable interrupt mask:
0 = No effect
1 = Prevents the activation of all exceptions with configurable priority

⚫ CONTROL
– Control register
Bits Name Function
[31:2] - Reserved
[1] SPSEL Defines the current stack:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer
In Handler mode this bit reads as zero and ignores writes
[0] nPRIV Defines the Thread mode privilege level:
0 = Privileged
1 = Unprivileged

24
 Little-endian format

STM32L0x3 memory map

25
Source: STMicroelectronics (DM00105960: STM32L053 datasheet)
⚫ Exception, interrupt and vector address

Priority level is programmable from 0 to 192

Exception event handlers for interrupt = ISR (interrupt service routine)

26
 Writing Arm assembly code

Source: ARM (https://developer.arm.com/documentation/102438/0100)

27
 ARM Cortex-M0+ instructions
⚫ 16-bit instruction set

⚫ 32-bit instruction set

28
⚫ Four main groups of instructions
– Memory access instructions
– General data processing instructions
⚫ Arithmetic operations
⚫ Logic operations
⚫ Shift and rotate operations
⚫ …
– Branch and control instructions
– Miscellaneous instructions
⚫ No operation
⚫ Wait for operation
⚫ …
Complete documentation reference:
1) PM0223 STM32L0 Series Cortex®-M0+ programming manual
2) ARM® v6-M Architecture Reference Manual

29
 Encoding

30 Source: ARM (ARMv6-M Architecture Reference Manual)

 Memory access instructions
PUSH {R0,R2-R4}
 push R0,R2,R3,R4 on the stack
POP {PC}
 pop PC from the stack and branch to PC address

31
 Memory access instructions
LDR R0,[PC,#0x20]
 R0=value in address[PC+0x20]

LDR R0,label
 R0=value in address[PC relative / label]

32
 Memory access instructions
LDR R0,=label (pseudo-instruction placing the address of label in memory)
 R0= address of label

33
 Memory access instructions
STR R0,[R1]
 Value in address[R1] = R0
STR R0,[R1,#0x20]
 Value in address[R1+0x20] = R0
STR R0,[R1,R2]
 Value in address[R1+R2] = R0

34
 General data processing instructions
MOV r0,r1
 r0=r1 move register to register
MOV r0,#0x20
 r0=0x20 move immediate data (8-bit)

ADD R0,R1,R2
 r0=r1+r2 add two registers without updating APSR
ADDS R0,R1,R2
 r0=r1+r2 add two registers, update APSR
ADCS R0,R1,R2
 r0=r1+r2+carry add two registers + carry, update APSR

35
 ANDS R0,R1,R2
 r0=r1&r2 perform bitwise AND on two registers
EORS R0,R1,R2
 r0=r1^r2 perform bitwise exclusive OR
ASR R0,R1,#3
 r0= 3-bit arithmetic shift right on r1

LSR R0,R1,#3
 r0= 3-bit logical shift right on r1

36
 Branch and control instructions
⚫ Condition code suffixes

37
 B label
 Branch to the address indicated by label (PC-relative)
Address of next instruction is save in R14 (link register/LR)
BX r0
 Branch to the address indicated by r0
Address of next instruction is save in R14 (link register/LR)
BEQ label
 Branch to the address indicated by label if Z flag is set
Address of next instruction is save in R14 (link register/LR)

38
 Example: string copying

39
 Miscellaneous instructions
WFI
 Suspends execution until an interrupt, an exception or a
debug request (for power saving)
NOP
 No operation
…

40