Part II: MPC555 Internal I/O Modules, Hardware interconnects, Interrupt Controller, External Interrupt ESR

External Interrupt ESR

Two major aspects:

Exception processing: Interrupt and resume programming execution Interrupt processing: Read interrupt registers, find and call ISR

External Interrupt ESR

General procedures:
1. 2. 3.

4.
5. 6. 7.

Save machine contexts Re-enable interrupts Save user-level registers Read interrupt vector code Calculate ISR address and jump to ISR Restore machine contexts and user-level registers Return to program execution

External Interrupt Exception Prologue

; STEP 1: SAVE "MACHINE CONTEXT" Create stack frame, saving r3, SRR0, SRR1 stwu sp, -40 (sp) Must use r3 or some other GPR because stw r3, 24 (sp) SRR0:1 cannot be saved directly mfsrr0 r3 MSR[EE] and MSR[RI] are cleared, i.e., stw r3, 12 (sp) Interrupt disabled and execution not recoverable mfsrr1 r3 stw r3, 16 (sp)

; STEP 2: make execution recoverable and enable ; external interrupt Set MSR[EE] and MSR[RI] bits; others: mtspr EIE, r3 EIE: set MSR[EE] and MSR[RI]
EID: set MSR[RI] only
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External Interrupt Exception Prologue (Continue) ; STEP 3: SAVE OTHER APPROPRIATE CONTEXT
mflr r3 stw r3, 8 (sp) mfcr r3 stw r3, 20 (sp)
Save LR and CR LR will be changed when calling ISR ISR will have branches that change CR r3 is used because CR and LR cannot be saved into memory directly

stw r4, 28 (sp) stw r5, 32 (sp) stw r6, 36 (sp)

Save other registers assume that any ISR uses only r3-r6 must save more if ISR is written in C

MPC555 Interrupt Controller

Features:
Support sixteen priority levels Interrupt masking: To help enable and disable interrupts

selectively Interrupt vector code: To help generate ISR address Interrupt prioritization: To help select the interrupt with the highest priority

MPC555 Interrupt Controller

U-BUS 8 8
4
1

IRQ[0:7] external
3 IRQ Reset Timer

USIU

1
1

Eight interrupt levels assigned to internal devices Eight IRQ pins reserved for extern devices
Hard drive, video card, IRQ[0]: connect to reset
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MPC555 Interrupt Controller

Programming interface SIPEND: Interrupt pending register, recording all pending interrupt signals SIMASK: Interrupt mask register, storing the mask bits SIVEC: Interrupt vector code, storing the vector code for the interrupt of the highest priority

MPC555 Interrupt Controller

SIPEND: Eight internal interrupt sources, eight external interrupt sources; interleaved together UIPEND is located From at UIMB IMB3 peripherals
L0 L1 L2 L3 L4 L5 L6 L7 for 7-31
UIPEND

External IRQ[0:7]
SIPEND
I0 I1 I2 I3 I4 I5 I6 I7 16 31

I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7

reserved
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MPC555 Interrupt Controller

SIPEND

SIMASK: 16 effective bits, one for each interrupt source

16 31

I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7
SIMASK
16

reserved
31

I0 L0 I1 L1 I2 L2 I3 L3 I4 L4 I5 L5 I6 L6 I7 L7

reserved

Masked Interrupt Signals 0-15

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MPC555 Interrupt Controller

SIVEC: Vector codeInterrupt for the most0-15 urgent interrupt Masked Signals
Priority Arbiter Hardware SIVEC 0 0 X X X X 0 0

Priority: 0 Highest

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MPC555 Exceptions and Interrupts device 1 device 2 device n

External Interrupts Interrupt controller External interrupt exception CPU SIVEC SIMASK SIPEND

Other ESR

External Interrupt ESR ISR 1 ISR 2

Other ESR

ISR n
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External Interrupt Exception ; STEP 4: DETERMINE INTERRUPT SOURCE Prologue (Continue)

lis r3, SIVEC@ha lbz r3, SIVEC@l (r3)
Load 8-bit SIVEC into r3 SIVEC here is a 32-bit constant 0x2FC01C Set up jump inst address in a jump lis r4, IRQ_table@h table ori r4, r4, IRQ_table@l use lis and ori to load IRQ table add r4, r3, r4 base mtlr r4 add offset to get the ISR address move jump inst address to LR

; STEP 5: BRANCH TO INTERRUPT HANDLER blrl blrl: branch to address in LR and save PC+4 in LR
basically this is a function call using function pointer at target address: b kth_isr_addr
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Set Up ISR Addresses

Use Jump table:
IRQ_jump_table: b irq0_handler ; interrupt pin 0 b level0_handler ; interrupt level 0 b irq1_handler ; interrupt pin 1 b level1_handler ; interrupt level b irq7_handler ; interrupt pin 7 b level7_handler ; interrupt level 7 irq0_hanlder: ; IRQ0 ISR put here
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Set Up ISR Addresses

Use address table
InterruptTable: .long irq0_handler .long level0_handler .long irq1_handler .long level1_handler .long irq7_handler .long level7_handler irq0_hanlder: ; ; ; ; ; ; ; interrupt interrupt interrupt interrupt pin 0 level 0 pin 1 level 1

interrupt pin 7 interrupt level 7

; IRQ0 ISR put here

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External Interrupt Exception Epilogue ; STEP 6: RESTORE CONTEXT

lwz r4, 28 (sp) lwz r5, 32 (sp) lwz r6, 36 (sp)
Restore r4, r5, r6, which were saved in prologue

lwz r3, 8 (sp) mtcrf 0xff, r3 lwz r3, 20 (sp) mtlr r3

Restore CR and LR again use r3 as a bridge CR and LR (and any other SPR) cannot be loaded directly with data from memory

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External Interrupt Exception Epilogue (Continue) Clear MSR[RI] and MSR[EE]

; STEP 6: RESTORE CONTEXT

mtspr NRI, r3 lwz r3, 12 (sp) mtsrr0 r3 lwz r3, 16 (sp) mtsrr1 r3 lwz r3, 24 (sp) addi sp, sp, 40

cannot be interrupted from now on; NRI: SPR for fast clearing MSR[EE] and MSR[RI]
Restore SRR0, SRR1 and r3 again use r3 as a bridge in restoring SRR0 and SRR1 r3 is the first to be saved and the last one to be restored

; STEP 7: RETURN TO PROGRAM rfi ; End of Interrupt rfi (return from interrupt):
restores MSR bits saved in SRR1 restores next-PC saved in SRR0
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External Interrupt ESR

General Setup

Set up SIMASK Set up ISR table Set up device interrupt level

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MPC555 On-Chip I/O

2

4 5

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MPC555 On-Chip I/O

TPU3 TPU3 MIOS1 QADC64 QADC64 TouCAN TouCAN QSMCM

IMB3 Bus

TPU3: Time Processor Units, 3rd version; versatile

functions, e.g. counting pulses MIOS1: Modular I/O System; QADC64: Queued Analog-to-digital converter TouCAN: Control Area Network, two-wire, up to 1Mbps and 40m; e.g. network inside vehicle QSMCM: Queued Serial Multi-channel Module IMB3 bus: Inter-Module Bus
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UIMB: U-bus to IMB Interface

IMB3 Bus
32

addr/data

UIPEND
8

UMCR[IRQUX]

U-Bus Other bus Interrupt controller

UIMB: U-bus to IMB interface

UIPEND: Interrupt pending reg.

U-bus: Unified bus, connecting multiple internal buses UMCR[IRQUX]: Enable level 7-31
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UIMB: U-bus to IMB Interface

The interface converts 32 interrupt levels on IMB3 Bus to 8 interrupt levels on U-Bus
Level 0-6 to U-Bus level 0-6 Level 7-31 to U-Bus level 7 Interrupt handler reads full UIPEND through memory-

mapped I/O

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Unified System Interface Unit

The USIU controls system start-up, system initialization and operation, system protection, and the external system bus.
MPC555 USIU functions: System configuration and protection Internal I/O Interrupt controller System reset monitoring and generation Clock synthesizer Processor USIU Power management Core External bus interface (EBI) control Memory controller Debug support
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Unified System Interface Unit

Internal I/O through U-bus External IRQ
4

USIU
Timebase Clock SIPEND SIMASK SIVEC

PIT
PLL
SW watchdog Decrementer

IREQ NMI control reset Decr timer

Note: External IRQ is controlled by SIEL triggered by falling edge or low level
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USIU Internal Interrupt Sources

MPC 555 has a crystal of 4MHz or 20MHz Time base: timer interrupt based on the clock; cannot be reset Real-time clock: timer interrupt based on real-time clock (like a watch); cannot be reset PIT: Periodic interrupt timer goes off every n cycles PLL change of lock: Phase lock loop, used to provide higher clock frequency; generate interrupt in abnormal situation, e.g. lost the lock of the clock Software watch dog: Used to monitor help avoid software deadlock Decrementer: Another timer interrupt, but is processed by a special handler (less overhead)
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Connecting To PowerPC Core

5

Finally!

IREQ 1

MSR[EE]

Vector table

&
NMI 2 Decrementer 3

n+0x100 n+0x500 n+0x900

SRR0 SRR1

inst addr to mem

Inst buffer

inst

Three interrupt lines to processor core: IREQ, NMI, and Decrementer MSR[EE]: Enable external interrupt IREQ: External interrupt NMI: Non-maskable interrupt (e.g. reset button is pushed) Decrementer: fast timer interrupt
Other processor components not shown
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Connecting To PowerPC Core

Refers to three handlers for
1. 2. 3.

Maskable Interrupt Non-maskable interrupt Decrementer (low-overhead timer)

When an interrupt happens, hardware:

Waits for current inst to complete Saves PC to SRR0 Saves MSR[EE] to SRR1, Clear MSR[EE] Transfer control to n+0x100, n+0x500, or n+0x900, respectively The rest is left to software handler

All I/O interrupts share the same interrupt handler

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