Exceptions and Interrupts Architecture: Microprocessor Systems

Cortex-M Exceptions & Interrupts Interrupt Configuration Interrupt Handling Interrupt Tail Chaining Interrupt Nesting
Microprocessor Systems
Exceptions and Interrupts

Architecture
University of Engineering and Technology Lahore

Contents
1 Cortex-M Exceptions & Interrupts
2 Interrupt Configuration
3 Interrupt Handling
4 Interrupt Tail Chaining
5 Interrupt Nesting
2/47
Introduction
Interrupt
An interrupt causes deviation to the normal program execution
flow. Both hardware (e.g., external inputs or peripherals) as well as
software events can generate interrupts
Interrupt Service Routine

The response from the processor is implemented as a function call
called interrupt service routine (ISR)
3/47
Procedure following occurrence of Interrupt
The sequence of operations involved from the occurrence of the

exception/interrupt to the resumption of normal program
execution again often involves the following key steps.
1. Interrupt request Generation
2. Suspension of currently executing task
3. Execution of an interrupt service routine
4. Resuming the suspended task
4/47
The Cortex-M Exceptions and Interrupts
• Exceptions 1 to 15 → (System) Exceptions

• Exceptions 16 to 255 → (Peripheral) Interrupts
5/47
Nested Vectored Interrupt Controller
• All Cortex-M processors include a Nested Vectored Interrupt

Controller (NVIC).
• NVIC can be configured for the desired functionality using its
memory-mapped control registers.
• Most of interrupt status and control registers can only be
accessed in the privileged mode.
• The NVIC also contains a timing module called SYSTICK
timer and its associated control registers.
• The actual number of interrupts that are supported by the
microcontroller is determined by the hardware manufacturers.
6/47
Different Sources of Interrupts Interfaced with NVIC

Cortex-M based Microcontroller
Cortex-M Microprocessor
SysTick
Reset
Processor Core
NVIC
NMI System Exceptions &
...
Software Interrupts
...
{
Integrated
Peripherals ...
{
Interrupt
Configurable I/Os
7/47
Exception and Interrupt Priority
• The NVIC allows multiple interrupt priority levels.

• In Cortex-M architecture, a higher-priority corresponds to a
smaller number assigned for priority level.
• The Cortex-M3/M4 based microcontrollers support three fixed
highest-priority levels and up to 256 programmable priorities.
• The maximum number of priority preemption levels is 128.
• The minimum number of priority levels is 8 corresponding to
3-bit priority configuration, while using an 8-bit priority
configuration, we can have 256 priority levels and is the
maximum number of priority levels available with Cortex-M
architecture.
8/47
System Exceptions and Interrupts with Associated

Priorities
Exception No. Label Priority
1 Reset -3
2 NMI -2
3 Hard fault -1
4 Memory management fault Programmable (Range 0-255)
6 Usage fault Programmable (Range 0-255)
7-10 Reserved Programmable (Range 0-255)
11 SVC Programmable (Range 0-255)
12 Debug Monitor Programmable (Range 0-255)
13 Reserved Programmable (Range 0-255)
14 PendSV Programmable (Range 0-255)
15 Systick Programmable (Range 0-255)
16 Interrupt 0 Programmable (Range 0-255)
.. .. ..
. . .
9/47
Priority Levels
Priority Bits Unused Bits
7 6 5 4 3 2 1 0
• To reduce the number of

priority levels, fewer bits of -3 (Reset)
Fixed Priority
-2 (NMI)
the priority configuration -1 (Hardfault)
Levels
registers are used by ignoring 0x00

0x20
the least significant bits. 0x40
• Using most significant bits 0x60
Programmable
of the priority configuration 0x80 Priority Levels
0xA0
registers makes it simpler to 0xC0
reuse the existing software 0xE0
for another device.

Figure: Bit allocation in the priority
configuration register for configuring
3-bit priority.
Priority Bits Unused Bits
10/47
Interrupt States
The execution of an ISR corresponding to a low priority interrupt
might be suspended due to the occurrence of a high priority
interrupt. This leads to different possible operating states.
• Active: The interrupt is in active state when it is being
serviced by the processor
• Inactive: No interrupt condition has been generated from the
corresponding interrupt source.
• Pending: The interrupt is waiting to be serviced by the
processor.
• Active and pending: An interrupt is being serviced by the
processor and there is a pending interrupt from the same
source.
11/47
Interrupt Configuration
Interrupt configuration process has multiple components.

• Global interrupt configuration is applicable to all the interrupts
• Local interrupt configuration is specific to that particular
source of interrupt.
• Interrupt vector table is used at the time of occurrence of an
interrupt to determine where the corresponding service routine
is located in the instruction memory.
12/47
Basic Interrupt Configuration
There are two aspects related to interrupt configuration.

1. Global configuration for the desired interrupt processing
behavior
2. Device or peripheral specific interrupt configuration of the
source of interrupt
13/47
Global Configuration
The following configurations are normally involved in setting up

the interrupt behavior globally.
• Interrupt/exception masking registers configuration
• Setting up interrupt vector table
• Configuring interrupt priority groups
14/47
Peripheral Specific Interrupt Configuration
Some of the important local device specific configurations, based

on the functionality, are listed below.
• Enabling and disabling of interrupts locally
• Interrupt pending control and status
• Priority level configuration
• Active status indication
15/47
Interrupt Masking
There are three different interrupt/exception masking special
registers in a Cortex-M processor:
1. Priority masking register (PRIMASK)
2. Fault mask register (FAULTMASK)
3. Base priority masking register (BASEPRI)
– These registers can only be accessed when the processor is
operating at privileged access level.
– On reset these registers are cleared to zero resulting in no
interrupt masking.
– These interrupt masking registers are accessed through special
register access instructions i.e. MSR and MRS.
16/47
PRIMASK Register
• The PRIMASK interrupt masking register is a 1-bit register.

• When it is set, all the exceptions/interrupts are blocked
except the Reset Interrupt, the Non-Maskable Interrupt
(NMI), and the HardFault exception.
• Setting PRIMASK to 1 is equivalent to raising the priority
level to 0.
• PRIMASK can be used to disable all of the interrupts when
executing a critical code section that should not be
interrupted once its execution starts.
17/47
FAULTMASK Register
• It is a 1-bit register
• Setting FAULTMASK to 1 only allows reset and NMI but
masks the HardFault exception.
• It is effectively equivalent to setting the priority level of
current exception to -1.
• FAULTMASK can be used to suppress any bus faults.
• FAULTMASK is cleared automatically when returning from an
exception.
18/47
BASEPRI Register
• 3 to 8 bits can be used by the BASEPRI register.

• When BASEPRI is set to a non-zero value, it blocks all the
interrupts of either the same or lower priority.
• The BASEPRI and the PRIMASK system registers can be
used for disabling interrupts temporarily when dealing with
time critical applications.
19/47
Registers used for interrupt masking. For the BASEPRI

register, two extreme scenarios corresponding to 3-bit and
8-bit implementation are shown
31 1 0
PRIMASK Reserved
FAULTMASK Reserved
31 7 5 0
Reserved
BASEPRI ...
31 7 0
Reserved
20/47
Setting Up Interrupt Vector Table

• The starting addresses of the interrupt service routines are
stored in the memory in the form of an interrupt vector table.
• In Cortex-M processor architecture, the vector table starts at
memory address 0 by default.
• For 32-bit address bus the starting address of an arbitrary
interrupt service routine can be stored in 4 bytes.
• The order as well as the assigned location to the entries in the
vector table is fixed and they cannot be rearranged.
• The vector table is usually provided as part of the startup code
made available by the microcontroller chip manufacturers.
• Since the vector table is located in non-volatile permanent
memory region, it cannot be modified or updated at runtime.
• Cortex-M processor architecture supports vector table
relocation capability. 21/47
Interrupt vector table at the default location. Observe that

some of the unused entries are also included to maintain
the location of each entry in the vector table
Memory Address Memory Contents
0x00000048 Interrupt #2 handler

0x0000003C Systick handler
0x00000038 PendSV handler
0x00000034 Reserved
0x00000030 Debug Monitor handler
0x0000002C SVC handler
0x00000028 Reserved
0x00000024 Reserved
0x00000020 Reserved
0x0000001C Reserved
0x00000018 Usage Fault handler
0x00000014 Bus Fault handler
0x00000010 MemManage handler
0x0000000C Hard Fault handler
0x00000008 NMI handler
0x00000004 Reset handler
0x00000000 MSP initial value
22/47
Configuring an Interrupt
For simple applications,

– The program is stored in flash memory or EEPROM.
– There is no need to change the exception handlers at run time.
– We can have the interrupt vector table located at the
beginning of the code memory region.
When dealing with interrupts, allocating enough size of the stack
memory is quite important. Since the exception handlers always
use the main stack pointer, it is the size of the main stack memory
that should have enough space.
23/47
Setting Up Interrupts
The sequence of steps required for setting up the interrupts is

listed below.
1. It involves configuring PRIMASK, FAULTMASK, and
BASEPRI masking registers. The default value is zero for all
of these interrupt masking registers.
2. Priority setting may require two configurations, one for priority
level and second for priority group. On reset, the priority
configuration register is 0
3. Each potential interrupt source should be configured to enable
the specific interrupt.
24/47
Handling of Exceptions or Interrupts

When an exception or an interrupt occurs, the processor uses either
handlers for exceptions or service routines for interrupts.
• Interrupt Service Routines: The external or peripheral
interrupts (i.e., exceptions 16 to 255) are handled by interrupt
service routines.
• Fault Handlers: These handlers are used for HardFault,
MemManage fault, UsageFault, and BusFault.
• System Handlers: NMI, PendSV, SVCall SysTick as well as
the above-mentioned fault exceptions are all considered
system exceptions. These exceptions are handled by system
handlers.
– Usually these handlers are implemented as part of the
operating system.
25/47
Exception Handling
When an exception takes place, a sequence of operations is

performed for proper handling of the exception.
1. Execution of the current instruction is either completed or its
execution is terminated without completing, depending on the
value of interrupt continuable instruction (ICI) field in the
xPSR register.
2. The current status is preserved by pushing registers R0-R3,
R12, LR, PC, and PSR to the stack.
3. The processor reads the exception number field from the
updated value of xPSR register and performs vector fetch by
reading the exception handler starting address from the
interrupt vector table.
26/47
Exception Handling Cont’d
4. Before the execution of the interrupt service routine begins,

the processor updates the stack pointer, link register (LR),
and program counter (PC).
5. Specific interrupt service routine corresponding to the
interrupt source is performed.
6. Return from the interrupt service routine, which also involves
popping the registers from the stack.
27/47
Register Stacking in Response to Interrupt Occurrence
• If the process stack pointer is being used by the application

program at the time of occurrence of interrupt or exception,
then the process stack will be used for storing the current
status.
• If the application program was using the main stack pointer,
then the registers are stacked to the main stack.
• For nested interrupts, where a higher priority interrupt occurs
during the execution of a lower priority ISR, the main stack
will be used during the execution of both ISRs.
28/47
Register Stacking in Response to Interrupt Occurrence

Cont’d
• The set of eight registers pushed to the stack is commonly

termed stack frame.
• Once the interrupt source has been identified and PC register
stacked, the processor fetches the ISR, by updating the PC, in
parallel to stacking of other registers.
• The processor automatically stacks its state before entering
the interrupt service routine and unstacks the system state
while exiting from the ISR.
29/47
Stacking of the registers in case of interrupts. The order in

which eight registers are stacked in memory and time
sequence of stacking the registers.
SP before
0x12345678
interrupt
xPSR
PC
LR
R12 Stacked
R3 registers
R2
R1
SP after
R0
interrupt
Stack empty
region
PC xPSR R0 R1 R2 R3 R12 LR
time
30/47
C/C++ procedure call standard for the ARM architecture

According to the C/C++ procedure call standard for the ARM
architecture,
• The registers R0-R3, R12, LR, PC, and xPSR are caller saved
registers and are required to be stacked when making a
function call.
• This arrangement allows the interrupt handler to be a normal
C function.
• Any other general purpose register that can be modified by the
exception handler should be saved on the stack by the user.
• The general registers (R0-R3 and R12) are located at the end
of the stacked region, allowing an easier access to these
registers using SP relative addressing. In addition, these
general purpose registers allow simpler parameter passing in
case of software interrupts.
31/47
Updating Registers
• SP: The stack pointer (either the MSP or the PSP) will be updated
to a new value during register stacking.
• xPSR: The least significant nine bits of xPSR (corresponding to the
interrupt program status register, IPSR) will be updated to the new
exception number.
• PC: The program counter will be updated to the exception handler
and starts fetching the service routine instructions from the location
of the exception handler.
• LR: The LR will be updated to a special value called EXC RETURN.
The least significant 4 bits (5 bits in case of Cortex-M4F processors)
of LR are used to provide exception return information.
• Some other NVIC related registers are also updated to active or
pending depending on the process of interrupt handling.
32/47
Description of bit fields on LR register for exception return
Bits Value Description

31-4 0xFFFFFFF No effect on exception return behavior.
0 Return to handler mode.
3
1 Return to thread mode.
0 Use main stack on exception return.
2
1 Use process stack on exception return.
1 0 This bit is reserved and must be zero.
0 Processor returns to ARM mode of op-
0
eration.
1 Processor returns to Thumb mode of
operation.
33/47
Possible exception returns based on LR register
LR value Description
0xFFFFFFF1 Return from exception handler to handler mode.
0xFFFFFFF9 Return from exception handler to thread mode
and use main stack on return.
0xFFFFFFFD Return from exception handler to thread mode
and use process stack on return.
Due to the special EXC RETURN value format, one cannot

perform an interrupt return to a memory address in the range
0xFFFFFFF0-0xFFFFFFFF. However, this requirement does not
lead to any restrictions, since this address does not fall in the code
memory region.
34/47
LR is set to 0xFFFFFFF9 on the occurrence of low priority

interrupt and is updated to 0xFFFFFFF1 on the higher
priority interrupt. Main stack is used in thread mode
Low Priority High Priority
Interrupt Interrupt
t1 t2 Time
Register Register
Stacking Unstacking
LR= LR= t3 t4
0xFFFFFFF9 0xFFFFFFF1
Main Stack, Main Stack, Main Stack,

Thread Mode Handler Mode Thread Mode
35/47
LR is set to 0xFFFFFFFD on the occurrence of low priority

interrupt and is updated to 0xFFFFFFF1 on higher priority
interrupt. In this case, process stack is used in thread mode
Low Priority High Priority
Interrupt Interrupt
t1 t2
Time
Register Register
Stacking Unstacking
LR= LR= t3 t4
0xFFFFFFFD 0xFFFFFFF1
Process Stack, Main Stack, Process Stack,

Thread Mode Handler Mode Thread Mode
36/47
Exception Exit or Return
After completing the execution of exception or interrupt handler,

an exception or interrupt return is performed to restore the system
status by
• Unstacking: All the registers that have been pushed to the
stack are restored during this process. The sequence of POP
operation will match the one followed during register stacking.
The stack pointer register is also updated during this process.
• NVIC register update: The active bit corresponding to current
exception is cleared. If the interrupt input, for external
interrupts, is still asserted, the pending bit is set again. As a
result the program execution leads to reentering the interrupt
service routine.
37/47
Instructions for Return from ISR
Some of the instructions, which can be used for returning from ISR
are:
• POP instruction
• Load instruction with PC as the destination register
• Branch instruction with any register holding the label
Some of the microprocessors support special instructions for
returning from interrupts (for instance, 8051 has RETI instruction).
In the case of Cortex-M3, return from interrupt can be performed
using normal return instruction, allowing to implement the entire
interrupt service routine as a normal C function.
38/47
Interrupt Latency
The interrupt latency has two components.

1. Interrupt entry latency: The number of processor clock cycles
from the arrival of an interrupt signal at the processor until
the execution of the first instruction in the interrupt service
routine starts.
2. Interrupt exit latency: The number of clock cycles required
from the execution of the interrupt return instruction until the
execution of the next instruction of the interrupted task.
The Cortex-M3/M4 processor has the minimum interrupt entry
latency of 12-cycles and interrupt exit latency of 10-cycles.
39/47
Minimum Interrupt Latency Conditions
• To achieve 12-cycle interrupt entry latency it is required that

register stacking (requiring 9 cycles to PUSH 8 registers) takes
place on one memory interface (usually system bus) in parallel
with vector fetch and interrupt handler fetch (requiring 6
cycles) on the other memory interfaces (usually I-Code).
• 12-cycle interrupt entry latency also requires that there are no
memory wait-states.
• Memory access without wait-states is also required to achieve
10-cycle interrupt exit latency.
40/47
Illustration of tail-chaining implementation in nested

vectored interrupt controller
Interrupt 1 Interrupt 2
Time
Conventional
Stacking ISR 1 Unstacking Stacking ISR 2 Unstacking
interrupt handling
Interrupt Tail-
Stacking ISR 1 ISR 2 Unstacking
tail-chaining chaining
41/47
Interrupt Tail Chaining
• Tail-chining allows NVIC to switch from pending interrupt to

active interrupt without unstacking/stacking of the registers.
Tail-chaining reduces the latency between two interrupt
handlers to 6 cycles compared to 22 (10+12) cycles.
• The 6-cycle latency in tail-chaining is due to the vector fetch
and interrupt handler fetch corresponding to the second ISR.
• In the case of multiple nested interrupts, the processor will
tail-chain a pending interrupt that has higher priority than all
other interrupts in pending state.
42/47
Interrupt Nesting with Multi-Level Priority

• The NVIC in Cortex-M3/M4 processor core provides nested
interrupt support, allowing higher priority interrupts to preempt
lower priority interrupts.
• The NVIC is responsible for decoding interrupt priorities and assign
appropriate interrupt status to each interrupt event.
• When an interrupt is enabled with an appropriate priority level and
processor is executing its ISR, all the interrupts with the same or
lower priority will be blocked by pending them.
• When a large number of different priorities are assigned to multiple
interrupts, then the size of the main stack should be assigned by
taking into account the possibility of multiple nested interrupts.
• For n nested interrupt levels, the minimum stack size required for
worst case sequence of nested interrupt occurrences will be 32n
bytes.
43/47
Multi-Level Interrupt Priority
• The 8-bit interrupt priority register is divided into two

sub-fields.
1. The most significant bit field determines the group priority
2. the least significant bit field determines the sub-priority of an
interrupt within the same priority group.
• Interrupt priority register can be from 3 bits to 8 bits in size.
44/47
Relation between number of group priorities and

sub-priorities for different configurations of PRIGROUP bit
field of AIRC register. The interrupt priority register of size
8-bit is considered
PRIGROUP Group priorities (associated bits) Sub-priorities (associated bits)

0 128 (b7-b1) 2 (b0)
1 64 (b7-b2) 4 (b1-b0)
2 32 (b7-b3) 8 (b2-b0)
3 16 (b7-b4) 16 (b3-b0)
4 8 (b7-b5) 32 (b4-b0)
5 4 (b7-b6) 64 (b5-b0)
6 2 (b7) 128 (b6-b0)
7 1 (none) 256 (b7-b0)
45/47
Interrupt Pending Behavior

The NVIC has dedicated programmable registers for storing
pending status of interrupts.
• When an interrupt signal is asserted on an arbitrary input of
NVIC, it results in setting the pending bit of the corresponding
pending status register associated with that interrupt.
• The pending status remains active even after interrupt signal
is deasserted, allowing NVIC to function properly for edge
(pulsed) interrupts.
• When no other higher priority interrupts are being served, the
processor immediately starts serving this interrupt changing
the pending status to become active.
• The interrupt pending status is stored in dedicated interrupt
pending status registers of NVIC, which can be accessed from
user program.
46/47
Relationship of interrupt pending and active states with

the processor execution
Interrupt 1
Time
Pending
status
Active
status
Processor
Stacking ISR 1 Unstacking
execution
Handler mode
47/47

Exceptions and Interrupts Architecture: Microprocessor Systems

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Exceptions and Interrupts Architecture: Microprocessor Systems

Uploaded by

Copyright:

Available Formats

Cortex-M Exceptions & Interrupts Interrupt Configuration Interrupt Handling Interrupt Tail Chaining Interrupt Nesting

Exceptions and Interrupts

University of Engineering and Technology Lahore

1 Cortex-M Exceptions & Interrupts

4 Interrupt Tail Chaining

Interrupt Service Routine

Procedure following occurrence of Interrupt

The sequence of operations involved from the occurrence of the

The Cortex-M Exceptions and Interrupts

• Exceptions 1 to 15 → (System) Exceptions

Nested Vectored Interrupt Controller

• All Cortex-M processors include a Nested Vectored Interrupt

Different Sources of Interrupts Interfaced with NVIC

NMI System Exceptions &

Exception and Interrupt Priority

• The NVIC allows multiple interrupt priority levels.

System Exceptions and Interrupts with Associated

• To reduce the number of

registers are used by ignoring 0x00

for another device.

Interrupt configuration process has multiple components.

Basic Interrupt Configuration

There are two aspects related to interrupt configuration.

The following configurations are normally involved in setting up

Peripheral Specific Interrupt Configuration

Some of the important local device specific configurations, based

• The PRIMASK interrupt masking register is a 1-bit register.

• 3 to 8 bits can be used by the BASEPRI register.

Registers used for interrupt masking. For the BASEPRI

Setting Up Interrupt Vector Table

Interrupt vector table at the default location. Observe that

0x00000048 Interrupt #2 handler

For simple applications,

The sequence of steps required for setting up the interrupts is

Handling of Exceptions or Interrupts

When an exception takes place, a sequence of operations is

Exception Handling Cont’d

4. Before the execution of the interrupt service routine begins,

Register Stacking in Response to Interrupt Occurrence

• If the process stack pointer is being used by the application

Register Stacking in Response to Interrupt Occurrence

• The set of eight registers pushed to the stack is commonly

Stacking of the registers in case of interrupts. The order in

C/C++ procedure call standard for the ARM architecture

Description of bit fields on LR register for exception return

Bits Value Description

Possible exception returns based on LR register

Due to the special EXC RETURN value format, one cannot

LR is set to 0xFFFFFFF9 on the occurrence of low priority

Main Stack, Main Stack, Main Stack,

LR is set to 0xFFFFFFFD on the occurrence of low priority

Process Stack, Main Stack, Process Stack,

Exception Exit or Return

After completing the execution of exception or interrupt handler,

Instructions for Return from ISR

The interrupt latency has two components.

Minimum Interrupt Latency Conditions

• To achieve 12-cycle interrupt entry latency it is required that

Illustration of tail-chaining implementation in nested

Interrupt Tail Chaining

• Tail-chining allows NVIC to switch from pending interrupt to

Interrupt Nesting with Multi-Level Priority

Multi-Level Interrupt Priority