Data Processing Instructions: Microprocessor Systems

Shift, Rotate, and Logical Instructions Arithmetic Instructions Bitfield Instructions Test and Compare Instructions
Microprocessor Systems
Data Processing Instructions
University of Engineering and Technology Lahore

Contents
1 Shift, Rotate, and Logical Instructions
Logical Instructions
2 Arithmetic Instructions
3 Bitfield Instructions
4 Test and Compare Instructions
2/36
Data Processing Instructions
• Shift, rotate, and logical instructions

• Basic math instructions
• Data movement instructions
• Bitfield instructions
• Test and compare instructions
• Saturating instructions
3/36
Shift and Rotate Instructions
General syntax for shift and rotate instructions
LSR{S}{cond}{.size} Rd, Rm, Rs or #n

ASR{S}{cond}{.size} Rd, Rm, Rs or #n
LSL{S}{cond}{.size} Rd, Rm, Rs or #n
ROR{S}{cond}{.size} Rd, Rm, Rs or #n
RRX{S}{cond} Rd, Rm
4/36
Shift and Rotate Instructions Cont’d
{} Represents the optional field.

S Is an optional suffix. If S is specified, the condition code flags are
updated on the result of the operation, see conditional execution
below.
cond This is an optional condition code suffix. See Chapter 7 for details.
.size The optional suffix to enforce 16-bit or 32-bit instruction size en-
coding and is formerly called instruction size qualifier .
Rd Specifies the destination register.
Rm Specifies the register containing the value to be shifted.
Rs Specifies the register holding the shift length to apply to the value
in Rm. Only the least significant byte is used.
n Specifies the shift length using an immediate value. The range of
shift length depends on the instruction.
5/36
Table: Instruction encoding and flag(s) affected by shift and rotate

instructions.
Mnemonic Brief description Encoding Flags

ASR Arithmetic shift right 16 or 32 bit N,Z,C
LSR Logical shift right 16 or 32 bit N,Z,C
LSL Logical shift left 16 or 32 bit N,Z,C
ROR Rotate right 16 or 32 bit N,Z,C
RRX Rotate right with extend 32 bit N,Z,C
6/36
• Instruction size can enforced using the instruction size

qualifier suffix
• The .W suffix generates a 32-bit instruction encoding
• To force a 16-bit instruction encoding, the .N suffix can be
used
• Specifying an instruction width suffix for which encoding
cannot be generated, results in an error
• When instruction size qualifier is not specified, the assembler
or compiler chooses appropriate instruction size
7/36
Shift Right Instruction

Logical Shift Right
C
0 b31 b30 ... b1 b0 X
After Two Bit

Logical Shift 0 0 b31 b30 ... b3 b2 b1
Right
Arithmetic Shift Right
b31 b30 ... b1 b0 X
After Two Bit

Arithmetic b31 b31 b31 b30 ... b3 b2 b1
Shift Right
8/36
Shift Right Instruction Cont’d
LSR R4 , R3 , #3 ; R4 = R3 >> 3
ASR R5 , R3 , #3 ; R5 = R3 >> 3
• If R3 = 64 then we get R4 = 8 and R5 = 8

• If R3 = -64 = 0xFFFFFFC0 then we get R4 = 0x1FFFFFF8
= 536870904 and R5 = 0xFFFFFFF8 = -8
• For unsigned integers the LSR and ASR give the same result
• However, for signed integers ASR gives the correct result
9/36
Shift Right Instruction Cont’d
• Illustration of the use of ‘S’ suffix

• Assuming R2 = 4 and R3 = 3
ASRS R4 , R2 , #3 ; R4 = R2 >> 3 and C = 1 after execution
ASRS R5 , R3 , #3 ; R5 = R3 >> 3 and C = 0 after execution
10/36
Rotate Right Instruction

Rotate Right
b31 b30 ... b1 b0 X
After Two
Bit Rotate b1 b0 b31 b30 ... b3 b2 b1
Right
Rotate Right eXtended
b31 b30 ... b1 b0 X
After One Bit

Rotate Right x b31 b30 ... b3 b2 b1 b0
eXtended
11/36
Logical Instructions
• General syntax for logical instructions
AND{S}{cond}{.size} {Rd, } Rn, Operand2

BIC{S}{cond}{.size} {Rd, } Rn, Operand2
EOR{S}{cond}{.size} {Rd, } Rn, Operand2
ORN{S}{cond}{.size} {Rd, } Rn, Operand2
ORR{S}{cond}{.size} {Rd, } Rn, Operand2
• Operand2 or Op2 is the flexible second operand
12/36
Logical Instructions Cont’d
Table: Instruction encoding and flag(s) affected by logical instructions.
Mnemonic Brief description Encoding Flags

AND Logical AND operation 16 or 32 bit N,Z,C
ORR Logical OR 16 or 32 bit N,Z,C
EOR Exclusive OR 16 or 32 bit N,Z,C
ORN Logical OR NOT 32 bit N,Z,C
BIC Bit clear 16 or 32 bit N,Z,C
13/36
Flexible Second Operand
• Constant: An Operand2 constant is specified in the form

#constant where constant can be any constant that can be
produced by shifting an 8-bit value left by any number of bits
within a 32-bit word. See [ARM, 2014] for details.
• Register: You specify an Operand2 register in the form of Rm
where Rm specifies the register holding the data for the
second operand.
14/36
Flexible Second Operand Cont’d

• Register with Optional Shift: Operand2 is specified as
Rm {, shift}, where Rm specifies the register holding the data
for second operand and shift is an optional shift to be applied
to Rm. Can be one of the following:
ASR #n Arithmetic shift right n bits, 1 ≤ n ≤ 32.

LSL #n Logical shift left n bits, 0 ≤ n ≤ 31.
LSR #n Logical shift right n bits, 1 ≤ n ≤ 32.
ROR #n Rotate right n bits, 1 ≤ n ≤ 31.
RRX Rotate right one bit, with extend.
If omitted, no shift occurs, equivalent to LSL#0.
• When Operand2 is specified as register with optional shift,

the contents in the register Rm remain unchanged.
15/36
Operand 1 Operand 2 Operand 2 = Register with Optional Shift
Rm {, shift}
Barrel
Shifter
ALU
Result
16/36
• Illustration of flexible second operand

AND R3 , R1 , R2 , LSL #5 ; Shift left ( logical ) R2 by five
; bits , AND with R1 and finally
; store result in R3 . This operation
; is equivalent to
; R3 = R1 & ( R2 << 5)
17/36
Arithmetic Instructions
• General syntax for addition and subtraction instructions
ADD{S}{cond}{.size} {Rd, } Rn, Operand2

ADC{S}{cond}{.size} {Rd, } Rn, Operand2
SUB{S}{cond}{.size} {Rd, } Rn, Operand2
SBC{S}{cond}{.size} {Rd, } Rn, Operand2
RSB{S}{cond}{.size} {Rd, } Rn, Operand2
ADDW{cond} {Rd, } Rn, #imm12
SUBW{cond} {Rd, } Rn, #imm12
• Note that ADDW and SUBW cannot affect the status flags
because of the absence of ‘S’ field
18/36
Arithmetic Instructions Cont’d

• Example 64-bit addition
ADDS R4 , R0 , R2 ; adding lower 32 - bit words
ADC R5 , R1 , R3 ; adding higher 32 - bit words along with
; carry flag from lower word addition
• Implementing y = 32x + c
LSL R2 , R2 , #5 ; Multiplying R2 with 32
ADD R3 , R2 , R1 ; Now perform the addition operation
OR
ADD R3 , R1 , R2 , LSL #5 ; Shift left ( logical ) R2 by five
; bits , add to R1 and finally store
; result in R3 . This operation is
; equivalent to R3 = R1 + ( R2 << 5)
19/36
Arithmetic Instructions Cont’d

• Multiply Instructions, 32-bit result
MUL{S}{cond} {Rd, } Rn, Rm
MLA{cond} Rd, Rn, Rm, Ra
MLS{cond} Rd, Rn, Rm, Ra
• Multiply Instructions, 64-bit result

UMULL{cond} RdLow , RdHigh, Rn, Rm
UMLAL{cond} RdLow , RdHigh, Rn, Rm
SMULL{cond} RdLow , RdHigh, Rn, Rm
SMLAL{cond} RdLow , RdHigh, Rn, Rm
• Divide Instructions
SDIV{cond} Rd, Rn, Rm
UDIV{cond} Rd, Rn, Rm
20/36
Multiply Instruction Example
• Implementing S = (n2 + n)/2

MLA R1 , R2 , R2 , R2 ; Multiply with accumulate ,
; R1 = ( R2xR2 )+ R2
LSR R1 , R1 , #1 ; R1 = R1 /2
• The equivalent C code

R1 = ( R2 *( R2 + 1) ) >> 1 ;
21/36
Divide Instruction Example
• For variables x and y , the remainder is evaluated as x%y in C

programming
• Let R0 = x and R1 = y
SDIV R2 , R0 , R1 ; Signed divide , R2 = R0 / R1
MLS R3 , R1 , R2 , R0 ; R3 = R0 - ( R2 x R1 )
22/36
Data Movement Instructions
• General syntax for data move instructions
MOV{S}{cond} Rd, Operand2

MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
MOVW{cond} Rd, #imm16
MOVT{cond} Rd, #imm16
• Pair of instructions MOVW and MOVT can be used to

generate 32-bit constants
23/36
MOV Instruction Illustration
0x1FFFFFFC
3 0x00000124 R0
0x00000000 R1
...
0x00000268
Code
Memory 0x00000264 0xF04F1024 MOV R0, #0x124 2
...
0x00000260
...
0x00000004
1 0x00000264 PC (R15)
0x00000000
Figure: Move instruction execution.
24/36
Bitfield Instructions: Bit and Byte Reversal
• General syntax for byte and bit reversal instructions
REV{cond} Rd, Rn
REV16{cond} Rd, Rn
REVSH{cond} Rd, Rn
RBIT{cond} Rd, Rn
• REV instruction can be used to convert big-endian format to

little-endian format and vice versa
25/36
Bitfield Instructions: REV Instruction
Byte 3 Byte 2 Byte 1 Byte 0
REV
Figure: Illustration of byte reversal in REV instruction.

REV16
26/36
REV
Bitfield Instructions: REV16 and REVSH Instructions

REV16
Byte 1 Byte 0
REVSH
Sign Extended Byte 1 Byte 0
Figure: Illustration of byte reversal in REV16 and REVSH instructions.

R2 R3
55 77 AA CC 00 00 01 23
27/36
Byte 1 Byte 0
Bitfield Instructions: Bitfield Clear and Insert Instructions

REVSH
• General syntax for bitfield clear and insert instructions
BFC{cond} Rd, #lsb,Byte#width
Sign Extended 1 Byte 0
BFI{cond} Rd, Rn, #lsb, #width
R2 R3
55 77 AA CC 00 00 01 23
BFI R2, R3, #4, #12
55 77 12 3C 00 00 01 23
R2 R3
(Modified) (Unchanged)
28/36
Bitfield Instructions: Bitfield Extract Instructions

• General syntax for bitfield extract instructions
SBFX{cond} Rd, Rn, #lsb, #width
UBFX{cond} Rd, Rn, #lsb, #width
R3 R1
00 00 00 00 AA BB 55 33
UBFX R3, R1, #6, #10
00 00 01 54 AA BB 55 33
R3 R1
Figure: Bit extraction with the UBFX instruction.

29/36
00 00
Shift, Rotate, and Logical Instructions 01 54 Instructions
Arithmetic 55
AA Instructions
Bitfield BB 33
Test and Compare Instructions
R3 R1
Bitfield Instructions: Bitfield Extract Instructions
R2 R1
00 00 00 00 AA BB 55 33
SBFX R2, R1, #16, #16
FF FF AA BB AA BB 55 33
R2 R1
Figure: Bit extraction with the SBFX instruction.
30/36
More Bitfield Instructions

• Syntax for sign/zero extend bitfield and count leading zeros
instructions
SXTB{cond} {Rd, } Rm, {, ROR #n}
SXTH{cond} {Rd, } Rm, {, ROR #n}
UXTB{cond} {Rd, } Rm, {, ROR #n}
UXTH{cond} {Rd, } Rm, {, ROR #n}
CLZ{cond} Rd, Rm
• SXT and UXT optionally rotate right Rm by 0, 8, 16, or 24 and

then extend sign or zero
• SXTB instruction extracts 8 bits, bits[7:0] and sign extends it to 32
bits
• SXTH instruction extracts 16 bits, bits[15:0] and sign extends to 32
bits
31/36
Test and Compare Instructions

• Syntax for test and compare instructions
CMN{cond} Rn, Operand2

CMP{cond} Rn, Operand2
TEQ{cond} Rn, Operand2
TST{cond} Rn, Operand2
• TST performs bitwise AND of Rn and Operand2

• TEQ performs bitwise Exclusive OR of Rn and Operand2
• CMP instruction subtracts Operand2 from Rn
• CMN instruction adds Operand2 to Rn
• All the instructions perform the operation, update the flags and
discard the result
32/36
Saturating Instructions
• Signal saturation due to hardware amplification
Original signal
Amplified signal
33/36
Saturating Instructions Cont’d

• Signal saturation due to software amplification
Original signal
Amplified signal without saturation instructions
Amplified signal using saturation instructions
34/36
Saturating Instructions Cont’d
• Syntax for signed and unsigned saturate instructions
SSAT{cond} Rd, #n Rm{, shift #s}

USAT{cond} Rd, #n Rm{, shift #s}
• SSAT and USAT instructions saturate a given value, respectively, to

a signed or unsigned n-bit final result
• SSAT applies the specified shift and saturates to the signed range
−2n−1 ≤ x ≤ 2n−1 − 1
• USAT applies the specified shift and saturates to the unsigned range
0 ≤ x ≤ 2n − 1
35/36
References
ARM (2014).
ARMv7-M architecture reference manual.
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Data Processing Instructions: Microprocessor Systems

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Shift, Rotate, and Logical Instructions Arithmetic Instructions Bitfield Instructions Test and Compare Instructions

Data Processing Instructions

University of Engineering and Technology Lahore

1 Shift, Rotate, and Logical Instructions

4 Test and Compare Instructions

Data Processing Instructions

• Shift, rotate, and logical instructions

Shift and Rotate Instructions

General syntax for shift and rotate instructions

LSR{S}{cond}{.size} Rd, Rm, Rs or #n

Shift and Rotate Instructions Cont’d

{} Represents the optional field.

Shift and Rotate Instructions Cont’d

Table: Instruction encoding and flag(s) affected by shift and rotate

Mnemonic Brief description Encoding Flags

Shift and Rotate Instructions Cont’d

• Instruction size can enforced using the instruction size

Shift Right Instruction

0 b31 b30 ... b1 b0 X

After Two Bit

Arithmetic Shift Right

b31 b30 ... b1 b0 X

After Two Bit

Shift Right Instruction Cont’d

• If R3 = 64 then we get R4 = 8 and R5 = 8

Shift Right Instruction Cont’d

• Illustration of the use of ‘S’ suffix

Rotate Right Instruction

b31 b30 ... b1 b0 X

Rotate Right eXtended

b31 b30 ... b1 b0 X

After One Bit

• General syntax for logical instructions

AND{S}{cond}{.size} {Rd, } Rn, Operand2

• Operand2 or Op2 is the flexible second operand

Logical Instructions Cont’d

Table: Instruction encoding and flag(s) affected by logical instructions.

Mnemonic Brief description Encoding Flags

Flexible Second Operand

• Constant: An Operand2 constant is specified in the form

Flexible Second Operand Cont’d

ASR #n Arithmetic shift right n bits, 1 ≤ n ≤ 32.

• When Operand2 is specified as register with optional shift,

Flexible Second Operand Cont’d

Operand 1 Operand 2 Operand 2 = Register with Optional Shift

Flexible Second Operand Cont’d

• Illustration of flexible second operand

• General syntax for addition and subtraction instructions

ADD{S}{cond}{.size} {Rd, } Rn, Operand2

Arithmetic Instructions Cont’d

Arithmetic Instructions Cont’d

• Multiply Instructions, 64-bit result

Multiply Instruction Example

• Implementing S = (n2 + n)/2

• The equivalent C code

Divide Instruction Example

• For variables x and y , the remainder is evaluated as x%y in C

Data Movement Instructions

• General syntax for data move instructions

MOV{S}{cond} Rd, Operand2

• Pair of instructions MOVW and MOVT can be used to

MOV Instruction Illustration

Figure: Move instruction execution.