Topic 3: ARM

Part 3: More Data Transfer and Data

Processing Instructions
 Data Transfer Instruction: LDR

 We bring data from memory into one of the

registers since arithmetic operations occur only
in registers in ARM instructions
 So ARM includes instructions that transfer data
between memory and registers (these are called
data transfer instructions)
 The specific (ARM) instruction name is LDR
which stands for ‘load word into register’

2
 Data Transfer Instruction: STR

 We have brought (read) data from

memory and performed an addition using
registers
 Can we do the converse ? Can we store
the result in memory ? – Yes, the ARM
assembly language command is STR

3
 How to add two 32-bit numbers
stored in memory ?

 We will discuss a solution using LDR,

STR and other instructions

4
 32-bit addition program with assembler
directives and instructions

AREA Reset, CODE, READONLY

ENTRY

LDR R0 , NUM1
LDR R1 , NUM2
ADR R3, R0, R1
LDR R5, =RESULT
STR R3, [R5]
Program continues ….
5 SWI &11
 32-bit addition program –
remaining code

NUM1 DCD &12A2E640

NUM2 DCD &001019BF

AREA DataRAM, Data, READWRITE

RESULT DCD 0
END

6
 What about adding 16-bit numbers ?

 General prog structure remains the same

 However, when we provide the numbers at
the end, we need to introduce an “ALIGN”
statement after
NUM1 ….
and
NUM2 …
 This ensures 00 00 padding to get the correct
7 results
 What about addition of 64-bit
numbers ?

 Let A and B be two 64-bit unsigned binary

integers; let A be in registers R0 and R1
with the least significant (right) half of A
in R0. Similarly, let B be in registers R2
and R3 with the right half in R2
 The ARM code for addition would then be
…

8
 64-bit addition program (assuming no
carry out of MSB after ADC)

AREA Reset, CODE, READONLY

ENTRY
LDR R0 , NUM1
LDR R1 , NUM1 + 4
LDR R2, NUM2
LDR R3, NUM2 + 4
ADDS R4, R0, R2
ADC R5, R1, R3
9 LDR R6, =RESULT Program continues ….
 64-bit addition – remaining code

STR R4, [R6]

STR R5, [R6, #4]
SWI &11
NUM1 DCD &12A2E640
DCD &00110112
NUM2 DCD &001019BF
DCD &0114A234

AREA DataRAM, Data, READWRITE

RESULT DCD 0
10 END
 More Data Processing Instructions

 We considered arithmetic operations.

There are instructions for performing
logical operations as well.
 AND, ORR, EOR, BIC are some of these.

11
 AND, ORR, EOR and BIC

 AND r0, r1, r2 ; r0 := r1 and r2

 ORR r0, r1, r2 ; r0 := r1 or r2
(ORR instead of OR for uniformity)
 EOR r0, r1, r2 ; r0 := r1 xor r2
(Exclusive OR is shortened to EOR)
 BIC r0, r1, r2 ; r0 := r1 and not r2
(BIC stands for bit clear where every 1 in
second operand clears the corresponding bit
12 in the first)
 Comparison Operations

 These are also in the data processing

category
 These do not produce a result but just set
the condition code bits (N, Z, C and V) in
Current Program Status Register (CPSR)
 N: Negative; Z: Zero; C: Carry; V:
oVerflow
 CPSR is 32-bits long: N is the MSB, Z is
13 the 31st, C is the 30th and V is the 29th bit
 CMP and CMN

 CMP r1, r2 ; set condition code on r1 – r2

(comparison of numbers
with same sign; flags set will be N or Z)
 CMN r1, r2 ; compare negative; have r1 +
r2; comparison of numbers with different
sign, CMP will not work correctly if a
number is negative since r1 – r2 with
negative r2 will cause r1 to be added to r2
14
 CMP, CMN and effect on CPSR

 The Current Program Status Register

(CPSR) is 32-bits long; in Keil µVision-5
you will see its value in the form
0x--- --- --- --- --- --- --- ---
with each --- representing a hex digit. We
are interested in the hex digit immediately
to the right of 0x as far as effect of
comparison is concerned
15
 Exercise: What will be the leftmost
hex digit (after 0x) in CPSR ?

AREA Reset, CODE, READONLY

ENTRY

MOV r0, #13

MOV r1, #-12
CMN r1, r0

stop
B stop

16 END
 Second case: What will be the
leftmost hex digit in CPSR now ?

AREA Reset, CODE, READONLY

ENTRY

MOV r0, #12

MOV r1, #-12
CMN r1, r0

stop
B stop
17
END
 Third case: What will be the
leftmost hex digit in CPSR now ?

AREA Reset, CODE, READONLY

ENTRY

MOV r0, #11

MOV r1, #-12
CMN r1, r0

stop
B stop
18
END
 MUL instruction

 MUL r4, r3, r2 ; r4 := (r3 x r2)

(when multiplication of two 32-bit

numbers yields a 64-bit result, least
significant 32 bits are placed in the result
register, rest are ignored)
- ARM provides extensions to store the
most significant 32 bits in another
19 register
 Exercise …

 Write a program to compute

4 x2 + 3 x

Assume x is stored in register r0 and the

result
goes to register r1
20
 Solution for 4 x2 + 3 x (assuming
x is 7)

AREA Reset, CODE, READONLY

ENTRY
MOV r0, #7
MUL r1, r0, r0
MOV r2, #4
MUL r1, r2, r1
MOV r3, #3
MUL r3, r0, r3
ADD r1, r1, r3
stop
B stop
END
21
 Exercise

 Rewrite the program for computing

4 x2 + 3 x using LDR in place of MOV

22
 How to realize 7 x2 + 4 x using
shifts (assuming x = 6) ?

AREA Reset, CODE, READONLY

ENTRY
LDR r0, =6
MUL r1, r0, r0
LDR r2, =7
MUL r3, r2, r1
ADD r4, r3, r0, LSL #2
stop
B stop
END

23
 Another feature of the ARM instruction set

 The ARM instruction set is quite rich in

that it allows different sets of instructions
to accomplish the same task
 ARM provides instructions that can help
reduce the size of the program. In
particular, it supports two instructions
called LDMIA and STMIA to handle (input
of data from) multiple registers elegantly

24
 Format of LDMIA and STMIA

 LDMIA R6, {R1,R2,R3,R4}

Can have even more registers within { }
 STMIA R6, {R0,R1,R2,R3}
Can have additional registers within { }

25
 64-bit addition program with
LDMIA and STMIA instructions

AREA Reset, CODE, READONLY

ENTRY
Main
ADR R0 , Value1
LDMIA R0 , {R1,R2 }
ADR R0 , Value2
LDMIA R0 , {R3,R4 }
ADDS R6 , R2 , R4
ADC R5 , R1 , R3 Program Continues ...
26
 64-bit addition program –
remaining code

LDR R0 , =Result
STMIA R0 , {R5, R6}
SWI &11

Value1 DCD &12A2E640 ,&F2100123

Value2 DCD &001019BF ,&40023F51

AREA DataRAM, Data, READWRITE

Result DCD 0
27 END
 Does ARM address each word ?

 To access a word in memory, the

instruction should supply the memory
address
 However, a word is 32 bits and often,
individual bytes are useful in programs
 ARM addresses each byte, hence word
addresses are multiples of 4 as illustrated
next
28
Actual ARM Memory Addresses and
Contents of Memory
 Alignment Restriction

 Since address of a word matches one of

the bytes in a word (in byte addressing),
addresses of sequential words differ by 4
 In ARM, words must start at addresses
that are multiples of 4. This requirement is
called as Alignment Restriction
 Many architectures use this (and in
general leads to fast data transfers)
30
 Big-Endian vs. Little-Endian

 Microprocessors follow either “big-

endian” or “little-endian” convention
when it comes to byte storage
 If the most significant (biggest) byte of a
word is assigned the lowest address (and
the least significant byte is assigned the
highest address), it is called Big-endian.
Example: Motorola 680X0

31
 What is Little-Endian ?

 If a microprocessor assigns the lowest

address to byte 0, then it follows the
`little-endian’ convention. Example: Intel
80X86 series
 ARM follows the `little-endian’ convention

Aside: The allusion is to an argument that appears in

Gulliver’s Travels on whether an egg should be opened at
its big end or little end
32
 Illustration of big-endian and little-endian

big-endian little-endian

Byte 1,0 Byte 1,3

Byte 1,1 Byte 1,2

Byte 1,2 Byte 1,1

Byte 1,3 Byte 1,0

003 Byte 0,0 Byte 0,3

002 Byte 0,1 Byte 0,2

Word Byte 0,1
001 Byte 0,2

Byte 0,3 Byte 0,0

000
33 Byte address