ECE 521:

Microprocessor System
Microprocessor Assembly Language Programming
What we will learn in this section:

❑Instruction set : COMPARE & TEST

❑ Instruction sets: LOOP & BRANCH
❑ Time Delay Calculation
❑ Flow Chart Review
Microprocessor Assembly
Language Programming

TEST AND COMPARE INSTRUCTION

Test and Compare Instructions

 Test and compare instructions update the condition flags on

the result, but do not place the result in any register.
In other words, these instructions are useful for testing and
comparing a variable against another when the actual
difference between their values is not important.
The list of instructions and the flags that are updated as a
consequence of these instructions is tabulated in the next
slide.
Mnemonic Brief Description Flags
CMP Compare N, Z, C, V
TST Test N, Z, C
CMP Instruction
 Syntax: CMP Rn, Op2
where:
Op2 can be a constant or a register
Rn is a source operand register (R0 – R12).
 The CMP instruction compares two operands and update
the condition flags based on the result, but do not place
the result in any register.
 The CMP instruction subtracts the value of Op2 from the
value in Rn and updates the flags accordingly.
Flags N, Z, C and V are updated.
Flag setting is similar to SUBS instruction.
 TST Instruction To test whether a bit of
 Syntax: TST Rn, Op2 Rn is 0 or 1, use the TST
instruction with an Op2
where: constant that has
 Op2 can be a constant or a register that bit set to 1 and all
other bits cleared to 0.
 Rn is a source operand register (R0 – R12).
 The TST instruction performs a bitwise AND operation on the value in
the register Rn and the value of Op2. This is the same as an ANDS
instruction, except that the result is discarded.
 Flags N, Z and C are updated.
Example 1:
TST R1,#0x01 ;check to see if bit 0 of R1 is zero, if so Z=1.;R1 remain unchanged

Example 2:
TST R1,#0xFF ;check to see if any bits of R1 is zero, if so ;Z=1. R1 remain unchanged
Microprocessor Assembly
Language Programming

INSTRUCTION SETS: LOOP & BRANCH

INSTRUCTIONS
Conditional vs Unconditional

 CONDITIONAL BRANCH
WHEN CPU executes a conditional branch, it check a condition, if the
condition is true then it jumps to the target location, otherwise, it executes the
next instruction

➢ UNCONDITIONAL BRANCH
WHEN CPU executes a unconditional branch, it jumps unconditionally (without
checking any condition) to the target location,
ARM Conditional Branch

ARM Conditional Branch Instructions for Unsigned Data

 LOOP
 Repeating a sequence of instructions or an operation a certain number of
times is called a loop.
 Example : Add 0x9 to R0 six times. That makes 6 × 9 = 54 = 0x36.

MOV R0,#0 ;R0 = 0

MOV R1,#9 ;R1 = 6 (R1 as a counter)
ADD R0,R0,R1 ;R0 = R0 + R1, add 9 to R0 (Now R0 is 0x09)
ADD R0,R0,R1 ;R0 = R0 + R1, add 9 to R0 (Now R0 is 0x12) Add 0x9
(six times)
ADD R0,R0,R1 ;R0 = R0 + R1, add 9 to R0 (Now R0 is 0x1B)
ADD R0,R0,R1 ;R0 = R0 + R1, add 9 to R0 (Now R0 is 0x24)
ADD R0,R0,R1 ; R0 = R0 + R1, add 9 to R0 (Now R0 is 0x2D
ADD R0,R0,R1 ; R0 = R0 + R1, add 9 to R0 (Now R0 is 0x36)
BNE (Branch if Not Equal)
 BNE uses the zero flag in the status register (xPSR).
 If Z = 0, the CPU branch to execute the instruction at the label .
 If Z = 1, the CPU will execute the next instruction after BNE.
 Example usage:
MOV Rn, #value ;initialize loop counter Rn
BACK ................. ;start of the loop
................. ;body of the loop
................. ;body of the loop
SUBS Rn, Rn, #1 ;Rn = Rn – 1 (Z=1 if Rn=0)
BNE BACK ;branch to BACK if Z = 0
................. ;instruction after loop
 Write a program to add 9 to R0 a SIX times

EXAMPLE LDR R2,=6

MOV R0,#0

AGAIN ADD R0,R0,#9

SUBS R2,R2,#1

BNE AGAIN
 Compare Instructions (Unsigned Number)
CMP Instruction
 The CMP instruction compares two operands and changes the flags
according to the result of the comparison.
CMP Rn, Op2 ; Compare Rn with Op2 and set the flags

Flag Settings for Compare (CMP Rn, Op2) of Unsigned Data

Example :
MOV R0,#50
MOV R1,#40
CMP R0,R1 ; will effect the flags, C=1 and Z=0
ARM Conditional Branch
 Conditional branch (BNE) used for increment counter

; clear R2 (R2 is counter)

; clear R0

;R0=R0+9
; increment R2 is a counter

;check R2, if R2 not equal 6

; jump to AGAIN until R2=6

 Write a program to inspect data in R2. If it is not equal,
save result in R3. Otherwise save in R7.
 Unconditional Branch
 The unconditional branch is a jump in which control is transferred
unconditionally to the target location
 In the ARM there are two unconditional branches: B (branch) and
BX (branch and exchange).
 In cases where there is no operating system or monitor program,
we use the Branch to itself in order to keep the microcontroller
busy.

 Unconditional Branch can jump anywhere

 Unconditional Branch –Branch (B)
 B (branch) is an unconditional jump that can go to any memory location in
the 32M byte address space of the ARM.
 Example: R3 is initialized with 2 when R1 is
lower than R2. Otherwise, it is
CMP R1,R2
initialized with 5.
BHS L1 ; branch if R1>R2
MOV R3,#2 ;R2=2
B OVER
L1 MOV R3,#5 ;R3=5
OVER NOP

NOTES: All branch is short jump size 32M Byte means that the address of the target must
be within 32M bytes of the program counter (PC). That means the short jumps cannot
cover the entire address space of 4G bytes (0x00000000 to 0xFFFFFFFF). To jump over 32M
byte can use BX
Unconditional Branch BX (branch and
exchange)
 To branch beyond the address space of 32M bytes, we use BX instruction.
 “BX Rn” instruction uses register Rn to hold target address.
 Since Rn can be any of the R0–R14 registers and they are 32-bit registers,
the “BX Rn” instruction can land anywhere in the 4G bytes address space
of the ARM.
 Subroutine
 BL (branch and link) instruction, used to call a subroutine.
 BX LR, used to return from subroutine [LR is (R14)]
 Every subroutine needs “BX LR” as the last instruction for return
address.
AREA A_SIMPLE_PROGRAM,CODE,READONLY
ENTRY
EXPORT main
Main
………………… ;main loop
BL SUBR_n ;Call Subroutine n where n=1,2,3….
HERE B HERE ;stay here.
;end of main
;SUBROUTINE n
SUBR_n …………
………………………
BX LR ;return to main
;end of subroutine n
Subroutine -Example

Notes:
Can also used BX R14 or
MOV PC,LR
22 Example

Write a program to examine the contents of memory location

0x20000000. If it is zero, fill it with 0xAA. If it is otherwise, leave the content
as it is.
 Solution
23

Flowchart
Start

Get the data LDR R5,=0x20000000

from location
LDR R1, [R5]
0x20000000

Is it SUBS R2, R1, #0

N
zero BNE Next
?
Y
Store 0xAA MOV R3, #0xAA
in location STR R3, [R5]
0x20000000

END
24 Program
 Example of Looping & Branching

 Write the program to calculate the result of 9+8+7+6+5+4+3+2+1

store the result in R7
START

;Set R6 as a counter

;clear R7

;R7=R7+R6

;Decrement R6

;IF not equal go to L1

END
Example of Loop & Branch
 Write the program to add 0x99999999 together 10 times.
 Example of Looping & Branching
 Write a program to place value 0x55 into 100 bytes of
RAM locations.
 Example : Nested Loop (loop within a loop)
 Write a program to (a) load the R0 register with the value 0x55, and (b)complement it 20,000
times.
 Rx is a 32-bit register, it can hold a maximum of 0xFFFFFFFF (2 – 1 decimal); therefore, the loop
can be repeated a maximum of 232 – 1 times. This example shows how to create a nesting
loop to go beyond 4 billion times. Because 20,000 is larger than 0xFFFFFFFF (the maximum
capacity of any R0–R12 registers), we use two registers to hold the count. The following code
shows how to use R2 and R1 as a register for counters in a nesting loop.
MOV R0,#0x55 ;R0 = 0x00000055
MOV R2,#100 ;load 100 into R2 (outer loop count)
L1 LDR R1,=200 ;R1 = 200 (inner loop count)
L2 EOR R0,R0,#0xFF ;complement R0 (R0 = R0 Ex-OR 0xFF)
SUBS R1,R1,#1 ;R1 = R1 – 1, dec. R1 (inner loop) This is a loop within a loop. The inner loop
BNE L2 ;repeat it until R1 = 0 runs 200 times but it is within an outer loop
SUBS R2,R2,#1 ;R2 = R2 – 1, dec. R2 (outer loop) that runs 100 times so the loop body runs 100 x
BNE L1 ;repeat it until R2 = 0 200 = 20,000 times.
HERE B HERE ;stay here LDR R1, =100;
END L1 LDR R2, =200;
L2 ;Loop body goes here
SUBS R2, #1;
BNE L2;
SUBS R1, #1;
BNE L1;
Microprocessor Assembly
Language Programming

TIME DELAY CALCULATIONS

 Time Delay

 Time for CPU to execute an instruction is called machine cycle.

 To calculate the machine cycle, we take the inverse of the crystal
frequency,
 Execution time = 1/f x machine cycle
 For delay subroutine, the time delay is calculated as follows; For Frequency=100MHz
 Time Delay= [1+((1+1+3)*255)+1] x 1/ 100M =15,320 ns Instruction cycle=1/100M
Time Delay Calculations
Find the size of the delay of the code snippet below if the crystal frequency is
100 MHz:
Instruction Machine Cycles
DELAY MOV R0,#255 1
AGAIN NOP 1 Given Crystal Frequency =100MHz
NOP 1 Period of the instruction cycle
= 1/f = 1/100M=10ns
SUBS R0,R0,#1 1
BNE AGAIN 3
MOV PC,LR ;return 1
A time delay = [1 + ((1+1+1+3) × 255) + 1] × 10 ns = 15,320 ns.
General programming logic

Flow chart
General Programming Logic

◆ Algorithm: the computational

procedure/method for solving a problem. An
algorithm describes:
➢ The actions to execute
➢ The order in which these actions execute
◆ Choice of Algorithm
➢ Most problems have more than one
possible algorithm
➢ Choose the most efficient algorithm
➢ Reasonable compromise between speed,
resource constraints, and flexibility
 General Programming Logic

◆ Use flow chart/flow diagram to describe the

steps in an algorithm
◆ It is highly recommended that you should draw a
flow chart to outline your program before writing
the codes
◆ Or at least, describe verbally what your program
is going to do
◆ Avoid going directly to coding part!
Flow chart

Graphical method to plan flow of

our programs.
Shows program’s step-by-step
operation.
Easy to understand and analyze.
Can be used to write organized
programs.
Flowchart

Basic shapes:
Terminator.
Process.
Decision.
Input/Output.
Connectors.
Basic Shapes – Terminator

Indicates beginning and end of

flowchart.
Once at beginning, once at end.
Examples:
START FINISH
Basic Shapes - Process
Describes actions to be done.
Represented as rectangles.
Short description of process in
rectangle.
Example:

A=AxB Reset Ports Clear R0

Basic Shapes - Decision

Shows alternative program flow based

on condition.
Represented as diamond shape.
 Should have 2 arrows, representing TRUE
and FALSE program flows.
Can be used in “if…else”, “while”, and
“for” situations.
Basic Shapes - Decision

Examples:

A = 3?
Port is active?
FALSE
TRUE

TRUE FALSE
Basic Shapes – Input/Output

Shows the process of inputting or

outputting data.
Represented using rhombus.
Examples:

Input B Show calculation

results
Basic Shapes - Connectors

Used to link large process flows together.

Represented using circles, with numbers inside.
Numbers indicate connection.
Examples:

1 3
Example: Connector

START
1

Input A
OPERATION

Input B
FINISH

1
Programming Procedures

1. Identify the task to be done

2. Draw a flow chart use words to describe your
algorithm
3. Write codes that represent your algorithm
4. Assemble your program and debug if
necessary
5. Test your program against a number of cases
6. Program completed!!
Translation to Assembly
AREA EXAMPLE7_1, CODE, READONLY
ENTRY
START EXPORT main
main

R1 MOV R1, #2

R2 MOV R2, #6

R1x R2 MUL R0,R2,R1

R3 MOV R3,R0

HERE B HERE
FINISH END
 EXERCISE
1) Compare B and BX instructions.
2) Write a program to add 9 to R0 a thousand times and place the sum in R4 using
loop instruction.
3) Write a program to examine the contents of memory location 0x20000004. If it is
nonzero, AND it with 0x0F. If it is otherwise, OR the content with 0x55.
4) Modify the program in question 3) into subroutine program
5) Find the number of times the following loop is performed:
MOV R0,#0x55
MOV R2,#40
L1 LDR R1,=10000000
L2 EOR R0,R0,#0xFF
SUB R1,R1,#1
BNE L2
SUB R2,R2,#1
BNE L1
EXERCISE
6) Assuming a crystal frequency of 100 MHz, find the time delay associated with the
loop section of the following DELAY subroutine:
Machine Cycle
DELAY LDR R2,=50000000 1
HERE NOP 1
NOP 1
NOP 1
NOP 1
NOP 1
SUBS R2,R2,#1 1
BNE HERE 3
BX LR 1