ECE 521:

Microprocessor System
Assembly language programming and simple I/O
Programming
 What we will learn in this section:

 Introduction of STM32F446RE Nucleo Board

 GPIO Registers & Programming
 Interfacing to LED
 Interfacing to SWITCH-LED
 STM32 Microcontroller
Built on ARM Cortex M processor core.
Cortex M0, M0+, M3, M4 and M7 cores.
Flash memory: few K bytes to few M bytes
SRAM: vary depending on the chip
STM32 Nucleo trainer board uses STM32F446RE
chip.
STM32F4xx is based on Cortex- M4
STM32 Arm Cortex Portfolio
 STM32 Arm Naming
 The STM32 part numbers have the following format;
STM32 F 4xxx P FFF T 6

 The STM32F446_Nucleo
board used the
STM32F446RE T6 chip
that has 64 pins and
512kB size of on-chip
Flash Memory
https://doc.riot-os.org/group__boards__nucleo-f446re.html#details

Nucleo-F446RE

 The Nucleo-F446RE is a
board from ST's Nucleo
family supporting a ARM
Cortex-M4 STM32F446RE
microcontroller with
128Kb of RAM and 512Kb
of ROM Flash.

For detail features please refer https://www.st.com/resource/en/datasheet/stm32f446re.pdf

 STM32F446RE Nucleo Board and Top Layout

The ARM Nucleo board. The USB port at the top of

the board (mini-B) is the programming port.[3]
STM32F446RE Nucleo Block Diagram
Programmer

 The ST-LINK allows us to program the board

stm32
NUCLEO BOARD SCHEMATICS
 STM32F446RET6 Pin Assignments

The microcontroller on the

Nucleo board is the
STM32F446RET6 which
comes in a 64 pin
LQFP 64 (Low profile Quad
Flat Pack) package.
STM32F446RET6 Pin Assignments

 The Nucleo board has two connectors

each consisting of two columns of pins.
Connector CN7 is on the left in Figure and
CN10 is on the right.
 CN7 and CN10 each have 38 pins in two
19-pin columns for a total of 76 pins so that
all pins of the LQFP 64 package are
brought out along with multiple power and
ground lines.
 A few pins have no connection (NC). See
Table 29 in the User's Manual (Board
Manual-page 58) for a complete mapping
of all of the package pins to the board pins
at CN7 and CN10.
NUCLEO-F446RE Extension Connectors
 ARM Busses
 The ARM chips have two types of buses:
 APB (Advanced Peripheral Bus)
Designed for lower speed and low power consumption memory and
peripherals.
 AHB (Advanced High-Performance Bus)
Designed to interface memory and fast I/Os directly to the CPU.
 AHB is much faster than APB
 AHB allows one clock cycle access to the memory and fast peripherals
without any wait state.
 APB access time is a minimum of 2 clock cycles.
 There are multiple AHB-APB bridges to connect AHB to the APB busses.
STM Arm Bus Matrix
GPIO ports are connected to
AHB bus via AHB/APB1 and
AHB/APB2 bridges.

The AHB and memories are

connected to CPU via a Bus
Matrix.

For detail, see page 54 in

STM32F446RE Reff Manual
 STM32F446RET6 Processor Microcontroller Block
Diagram

For the Nucleo

board the
STM32F446RET6
has 512 KB of flash
memory and 128 K
of RAM.
 Memory Map of STMF446RE

 Flash memory used for Program Code

 SRAM used for variables, scratch pad and stack
 Example I/O : GPIO,Timer and ADCs
Notes: the upper limit address varies among the chips depending on the size of
on-chip Flash, SRAM and peripherals.
Memory map for STM32F446RE
 The ARM has 4GB of memory address
space use memory mapped I/O
(meaning the I/0 peripherals registers are
mapped into the 4GB memory space.
 The ARM has a 32-bit address and in hex
addresses range from 0000 0000 to FFFF
FFFF. This is a linear address space and
there are no I/O instructions since all ports
are mapped from memory.
 All of the I/O ports are mapped into the 4
GByte memory space.(mapped to the
address range 0x4000 0000 to 0x5FFF FFFF.)
 Alternatives ARM Compilers

STM32CubeIDE MBED STM32DUINO KEIL uVISION

Specific and optimize Cross platform and Access to various Assembly and
for STM32 chips support multiple Arduino library debugging capability
vendors
Hardware Abstraction C C Assembly and C
Layer (HAL)
programming
 What we will learn in this section:

 Introduction of STM32F446RE Nucleo Board

 GPIO Registers & Programming
 Interfacing to LED
 Interfacing to SWITCH-LED
 General Purpose I/O (GPIO)
 I/O ports are used by the CPU to access input and output devices.
 There two types of I/O
 General Purpose I/O (GPIO)
For interfacing devices such as LEDs, switches, LCD, keypad, etc.
 Special Purpose I/O
Ports that have designated function such as ADC, Timer, UART, etc.
 In STM ARM chips, GPIO ports are named A, B, C, D, E, F, G and H.
 Each port can have up to 16 pins.
Pins are designated as PA0 – PA15, PB0 – PB15, PC0 – PC15, and so on.
NOT ALL 16 pins of each port are implemented in every chip.
 Nucleo Board Available Pins
 For the I/O ports, Table 2 gives the pins are available for the Nucleo Board:

Notes:
1. PB11 is not brought out to a board pin.
2. PA13 and PA14 are shared with the debug
circuitry and should be avoided if possible.
3. A User LED (green) is connected to PA5 and is
on when the pin is high.
4. A User push-button is connected to PC13.
GPIO Registers
 STM32F4xx microcontroller on the Nucleo board has several general purpose
input/output (GPIO) ports named Port A,B,C,D,E,F,G & H.
 Each of the GPIO ports on the ARM Cortex M4 processor has ten 32-bit registers that
are used to configure the port and get information in and out and Table 3 defines
these registers.

A GPIO register is a 32-bit

storage area that hold
configuration bits for a
GPIO pin

Note: alternate function include timers, UARTs, CAN, Ethernet, I2C, and SPI to be attached to a port pin.
 GPIO Registers Address
 Each GPIO has:
 Four 32-bit configuration registers
 GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR
 Two 32-bit data registers
 GPIOx_IDR and GPIOx_ODR
 A 32-bit set/reset register
 GPIOx_BSRR
 A 32-bit locking register
 GPIOx_LCKR
 Two 32-bit alternate function selection register
 GPIOx_AFRH and GPIOx_AFRL
 GPIO Registers Address
 Address ranges assigned to ports of STM32F4xx chips:

Port Address Range

GPIO Port A 0x4002 0000 – 0x4002 03FF
GPIO Port B 0x4002 0400 – 0x4002 07FF
GPIO Port C 0x4002 0800 – 0x4002 0BFF
GPIO Port D 0x4002 0C00 – 0x4002 0FFF
GPIO Port E 0x4002 1000 – 0x4002 13FF
GPIO Port F 0x4002 1400 – 0x4002 17FF
GPIO Port G 0x4002 1800 – 0x4002 1BFF
GPIO Port H 0x4002 1C00 – 0x4002 1FFF
The first address of each GPIO is called the base address.
Each register has an address.
The register address is an offset address from the base address.
 GPIO Registers Address
 Some of the registers associated with each GPIO port:

Address Offset Register Name Description Type

0x00 GPIOx_MODER GPIOx Port Mode (Direction) R/W
Register
0x04 GPIOx_OTYPER Output Type Register R/W
0x08 GPIOx_OSPEEDR Output Speed Register R/W
0x0C GPIOx_PUDR Pull-Up/Down Register R/W
0x10 GPIOx_IDR Port Input Data Register R/W
0x14 GPIOx_ODR Port Output Data Register R/W
0x18 GPIOx_BSRR Bit Set/Reset Register R/W
Where x = A, B, C, D, E, F, G, H (for ports)
 Some GPIO Registers & their functions
 RCC_AHB1ENR (RCC AHB1) peripheral clock enable register) enables or disables
clock supply to various peripherals. AHB1 indicates these peripherals are on AHB1
bus of processor. To use GPIO port x, we need to enable clock for GPIO-x via this
register.
 GPIOx_MODER (GPIO-x Mode register) used to select the I/O direction. We can
configure each pin independently as either of these modes: Digital Input, Digital
Output, Analog Function and Alternate function peripheral within the
microcontroller.
 GPIOx_IDR and GPIOx_ODR (I/O port data registers )
Each GPIO has two 16-bit memory-mapped data registers: input and output data
registers.
 GPIOx_ODR stores the data to be output, it is read/write accessible. The data
input through the I/O are stored into the input data register
 GPIOx_IDR, stores the data to be input, a read-only register.
 GPIOx_BSRR (Bit set reset register )
 32-bit register where the lower 16-bits are used to set any of the 16 pins and the
higher 16-bits to clear/reset any of the 16 pins of a particular IO port.
 It allows the application to set and reset each individual bit in the output data
register (GPIOx_ODR).
 The bit set reset register has twice the size of GPIOx_ODR.
 OTHER GPIO Registers & their functions
GPIOx_OTYPER (GPIO-x Output Type register) controls whether the pin works in push-pull
mode or as an open-drain pin. In case of open drain, we need external pull-up or pull-
down.
GPIOx_OSPEEDR (GPIO-x Output Speed register) controls the maximum switching speed
on the port pin. The maximum speed also depends on supply voltage, current drawn from
pin and load capacitance. We can configure the speed as low / medium / high / very
high.
GPIOx_PUPDR (GPIO-x Pull-up / Pull-down register) enables internal pull-up or pull-down
resistor for each port x pin. GPIOx_ODR (GPIO-x Output Data register) is the register to
write data to output on the port pins.
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register
I/O alternate function input/output
Two registers are provided to select one out of the sixteen alternate function
inputs/outputs available for each I/O. This means that a number of possible peripheral
functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate
function registers.
Clock Enable of the Peripheral
Registers
 Note that the clocks for the serial communication
modules, timers and other peripherals are not enabled
upon reset.
 There are several registers belonging to RCC_AHBxENR
group of registers depending on which family of STM32.
 RCC_AHB1ENR, RCC_AHB2ENR
Clock Enable of the Peripheral Registers
 The clock to a given I/O port or peripheral must be enabled before using it.
 By default, GPIO modules of the STM32 ARM® microcontrollers have the
clock disabled after power-on reset to conserve power.
 GPIO clock enable is controlled by the lower bits of RCC_AHB1ENR
(Reset and Clock Control AHB1 Enable Register).
 RCC_AHB1ENR register bits:
Refer page 144 in STM32F446RE Reff Manual)
GPIO Port Mode Register
(GPIOx_MODER) Refer page 187 in STM32F446RE Reff Manual)
 GPIO PINS

A GPIO pin is a
generic pin
controllable by
the user at run
time and
configurable to
be input or
output.

Basic structure of a 5 V tolerant I/O port bit(Refer page 177 in STM32F446RE Reff Manual)
GPIO Port Input Register (GPIOx_IDR)
Refer page 189 in STM32F446RE Reff Manual)
GPIO Port Output Register
(GPIOx_ODR) Refer page 190 in STM32F446RE Reff Manual)
GPIO Port Bit/Set Register (GPIOx_BSRR)

Refer page 190 in STM32F446RE Reff Manual)

BASIC STEPS Of GPIO CONFIGURATION

The fundamental initialization steps

required to utilize any of the peripheral
are:
1)Enable clocks to the peripheral
2)Configure pins required by the peripheral
3)Configure peripheral hardware
Interfacing to LED in assembly
language
Example: Write a program in assembly program that
will turn ON Green LED (LD2) on the STM32F446RE
board.
STM32 NucleoF446RE trainer board has a single user LED (LD2)
connected to port pin PA5.The LED will turn on when the I/O
pin is HIGH.

User LED connection for STM32F446RE Nucleo board

Steps to TURN ON the LD2 (green) ONCE of
the Nucleo board

1. Enable GPIOA clock.

2. Set the MODE register bits for PA5 as output.
3. Write HIGH to PA5 in Output Data Register.
Steps to TURN ON the LD2 (green) of the
Nucleo board
1) Enable Port A clock START

2) Set the Mode register bits for PA5 as output

3) Write HIGH to PA5 in data OUTPUT register Enable Port A clock

Configure PA5 as
output

Turn on LED
Step1 : Enable GPIO clock RCC_AHB1ENR

To enable GPIOA clock

Set GPIOAEN = 1 i.e. RCC_AHB1ENR[0] = 1
Register information:
RCC Base Address: 0x4002 3800
RCC_AHB1ENR Address Offset: 0x30
Step1 : Enable GPIO clock RCC_AHB1ENR
Refer page 144 in STM32F446RE Reff manual

Find out the address of register RCC_AHB1ENR. This register is part of the RCC registers (Reset and
Clock control). The offset of this register is 0x30 as described in section 6.3.10 of reference manual.
The memory map shows the RCC boundary address range as 0x40023800 to 0x40023BFF. Therefore
the address of RCC_AHB1ENR register is 0x40023800 + address offset (0x30) = 0x40023830
Step1 :Enable GPIO clock RCC_AHB1ENR : Clock Setting for
GPIOx
 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
 Refer Section 6.3.10
 Loading 0000 0000 0000 0001

Enable GPIOA
0 0 0 1
Step1 : Enable GPIO clock RCC_AHB1ENR

 Program segment:
RCC_AHB1ENR equ 0x40023830 ;Define address of RCC_AHB1ENR
LDR R4, =RCC_AHB1ENR ;R4 <- RCC_AHB1ENR
LDR R5, [R4] ;R5 <- contents of RCC_AHB1ENR
ORR R5, #1 ;set bit0 (GPIOAEN = 1 )
STR R5, [R4] ;RCC_AHB1ENR <- R5
Step 2 : Configure the desired I/O as OUTPUT or INPUT in the
GPIOx_MODER register

0 1

Set GPIOA PA5 to be an OUTPUT

0x40020000 + address offset (0x00) = 0x40020000

Step 2 : Configure the desired I/O as OUTPUT or INPUT in the
GPIOx_MODER register
 To configure PA5 as output
 Set MODER5[1:0] = 01 i.e. GPIO_MODER[11:10] = 01
 Register address:
 GPIOA Base Address: 0x4002 0000
 GPIO_MODER Address Offset: 0x00
 Program segment:
GPIOA_MODER equ 0x40020000 ;Define address of GPIOA_MODER
LDR R4, =GPIOA_MODER ;R4 <- address of GPIOA_MODER
LDR R5, [R4] ;R5 <- contents of GPIOA_MODER
BIC R5, #0x00000C00 ;Reset MODER5 mode i.e. R5[11:10] = 00
ORR R5, #0x00000400 ;Set MODER5 mode as output i.e. R5[11:10] = 01
STR R5, [R4] ;GPIOA_MODER <- R5 i.e. GPIOA_MODER[11:10] = 01
Step 3 : GPIO port bit set/reset register (GPIOx _BSRR)

The lower 16 bits of

BSRR turns ON the
pins

0 0 1 0

0x40020000 + address offset (0x18) = 0x40020018

Flowchart

START

LDR R4, =RCC_AHB1ENR

LDR R5, [R4]
Enable Port A clock
ORR R5, #1
STR R5, [R4]

LDR R4, =GPIOA_MODER

Configure PA5 as
output
LDR R5, [R4]
ORR R5, #0X00000400
STR R5, [R4]
LDR R4, =GPIOA_BSRR
Turn on LED LDR R5, =0X00000020
STR R5, [R4]
HERE B HERE
END
Coding using GPIOA_BSSR register
Coding using GPIOA_ODR register
Interfacing to LED in assembly
language
For controlling an LED on/off, we need to configure a GPIO pin in
output mode.
 Program Descriptions
 The green LED (LD2) is connected to
PA5.
 The LED is high active (a '1' turns on the
LED).
 The default system clock is running at
16 MHz.
 This program toggles LD2 for 0.5
second ON and 0.5 second OFF by
writing 0 or 1 to bit 5 or bit 21 of the
User LED connection for STM32F446RE Nucleo board Port A Output Data Register i.e Bit
Set/Reset Register (BSRR).
 The lower 16 bits of BSRR turns on the
pins and the upper 16 bits of BSRR
turns off the pins.
Steps to toggle the LD2 (green) continuously
of the Nucleo board

1) Set the Mode register bits for PA5 as output

2) Write HIGH to PA5 in data OUT register
3) Call a delay function
4) Write LOW to PA5 in data OUT register
5)Call a delay function
6)Repeat step 2 To 5
Step1 : Enable GPIO clock RCC_AHB1ENR
Step1 Enable GPIO clock RCC_AHB1ENR : Clock Setting for
GPIOx
 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)
 Refer Section 6.3.10
 Loading 0000 0000 0000 0001

Enable GPIOA
0 0 0 1
Step 2 : Configure the desired I/O as OUTPUT or INPUT in the
GPIOx_MODER register

0 1 0 0

Set GPIOA PA5 to be an OUTPUT

0x40020000 + address offset (0x00) = 0x40020000

Step 3 : GPIO port bit set/reset register (GPIOx _BSRR)

The lower 16 bits of

BSRR turns ON the
pins

0 0 1 0

0x40020000 + address offset (0x18) = 0x40020018

Step 4 : GPIO port bit set/reset register (GPIOx _BSRR)

0 0 1 0

The upper 16 bits of

BSRR turns off the
pins.

BR5=1
 START

Flowchart LDR R4, =RCC_AHB1ENR

Enable Port A clock LDR R5, [R4]
ORR R5, #1
STR R5, [R4]

Configure PA5 as LDR R4, =GPIOA_MODER

output LDR R5, [R4]
ORR R5, #0X00000400
STR R5, [R4]
L1 LDR R4, =GPIOA_BSRR
Turn on LED LDR R5, =0X00000020
STR R5, [R4]
BL Delay
B L1
Delay 0.5s
L1 LDR R4, =GPIOA_BSRR
LDR R5, =0X00200000
STR R5, [R4]
Turn OFF LED
BL Delay
B L1

Delay 0.5s
Sample Coding in Assembly Program for blinking LEDs
Assembly program to toggle the green LED (LD2) on STM32F446RE Nucleo64 board at 16Hz

Coding using GPIOA_BSSR register

Coding using GPIOA_ODR register
Interfacing to switch in
assembly language
For controlling an LED on/off by pressing button, we need to configure
a GPIO pin in input mode.
Program Description
 This program turns on the green LED (LD2) by pressing
the user button B1 of the Nucleo board.The user
button is connected to PC13. It has a pull-up resistor
so PC13 stays high when the button is not
pressed.When the button is pressed, PC13 becomes
low.The green LED (LD2) is connected to PA5.A high
on PA5 turns on the LED.

 To read a switch and turn on the LED LD2 if the switch is

pressed:
1. Enable GPIO clock for port GPIOA and GPIOC.
2. Configure pin PA5 as output.
3. Configure pin PC13 as input.
4. Read switch from PC13.
5. If PC13 is LOW, set PA5 HIGH to turn on LD2.
6. If PC13 is HIGH, clear PA5 (LOW) to turn off LD2.
7. Repeat steps 4 to 6.

Switch connection to STM32F4-NUCLEO board

 Connecting external switches to the
microcontroller

Depending on how the external SW is connected , we need to enable the internal pull-up
or pull-down Resistor for the pin.
 If the SW connected to the ground, the internal Pull-up Resistor is enabled.
 If the SW connected to the power, the internal Pull-down Resistor is enabled.
Input and Output Data
Step1 : Enable GPIO clock RCC_AHB1ENR :
Clock Setting for GPIOA and
GPIOC

0 1 0 1
Enable both GPIOA & GPIOC
Step 2 : Configure the desired I/O as OUTPUT or INPUT in the
GPIOx_MODER register
See Table 1 in
pg 57 in
STM32F446RE
Reff manual

0 0
STEP 3:GPIO port INPUT Data
Register (GPIOx _IDR)

0 0 1 0 PC13 is high

0x40020800 + address offset (0x10) = 0x40020810

Step 4:GPIO port bit set/reset register (GPIOx _BSRR)

The lower 16 bits of

BSRR turns ON the
pins

0 0 1 0

0x40020000 + address offset (0x18) = 0x40020018

Step 4:GPIO port bit set/reset register (GPIOx _BSRR)

0 0 1 0

The upper 16 bits of BSRR

turns off the pins.

BR5=1
 Flowchart
L1 LDR R4, =GPIOC_IDR;
LDR R3, [r4] ; Copy PA13 to r3
AND R3, #0x2000 ; Mask bit13 (i.e PA13
CMP R3, #0 ; Is it zero?
Read the status of BEQ turnon ; branch to turnon
the switch
START

LDR R4, =RCC_AHB1ENR

Turn off LED
LDR R5, [R4] Enable Port A & C
ORR R5, #5 clock
STR R5, [R4] Is the LDR R4, =GPIOA_BSRR
N
switch LDR R5, =0x00200000 ; turn off LED
LDR R4, =GPIOA_MODER pressed STR r5, [r4]
LDR R5, [R4] Configure PA5 as ? B L1 ; branch to L1
ORR R5, #0X00000400 output
STR R5, [R4] Y turnon LDR r4, =GPIOA_BSRR
LDR r5, =0x00000020 ; turn on LED
LDR R4, =GPIOC_MODER Turn on LED STR r5, [r4]
LDR R5, [R4] Configure PC13 as B L1 ; loop forever
BIC R5, #0X0C000000 input
END
STR R5, [R4]
APPENDICES

See Table 1 in
pg 57 in
STM32F446RE
Reff manual
APPENDICES
APPENDICES