ECE 521:

Microprocessor System
Microprocessor Assembly Language Programming
 What we will learn in this section:

 Addressing Modes
 Instruction sets: Data Transfer
 MOV instruction
 LDR / STR Instruction
ECE 521:
Microprocessor System
Addressing Modes
Addressing modes
 refer to the ways the operands are specified in the instruction.
 Specifies the ways , the effective address of an operand is
represented in the instruction.
 the way CPU generates addresses from instruction to read/
write the operands in the memory
 Some of the simple ARM addressing modes are:
1. Register
2. Immediate
3. Register indirect (indexed addressing mode)
 Destinations of all ARM instructions are always a register, except
the “STR” instructions.
 Register Addressing Mode
 The register addressing mode involves the use of registers to hold the data to be
manipulated, symbol R.
 Memory is not accessed; therefore, it is relatively fast
 Examples of register addressing mode:
MOV R6, R2 ; copy the contents of R2 into R6
ADD R1, R1, R3 ; add the contents of R3 to contents of R1
SUB R7, R7, R2 ; subtract R2 from R7

Fig 4-1: Register Addressing Mode

 Immediate Addressing Mode
 the source operand is a literal constant. Symbol #.
 when the instruction is assembled, the operand comes immediately
after the opcode. For this reason, this addressing mode executes
quickly.
 Examples:
MOV R9, #0x25 ; move 0x25 into R9
MOV R3, #62 ; load the decimal value 62 into R3
ADD R6, R6, #0x40 ; add 0x40 to R6

Fig 4-2: Immediate Addressing Mode

 Register Indirect Addressing Mode (Indexed addressing mode)
 the address of the memory location where the operand resides is
held by a register. Symbol [ ].
 For example:
STR R5, [R6] ; write the content of R5 into the
; memory location pointed to by R6
LDR R10, [R3] ; load into R10 the content of
; the memory location pointed to by R3

Fig 4-3: Register Indirect Addressing Mode

 ARM Instruction Sets
Types of Instruction Sets
 Data Transfer
 Flow Control
 Register to register
 Register to memory  Conditional Branch
 Memory to register  Unconditional Branch
 Data Processing
 Arithmetic
 Logic
 Multiply & Division
 Shift & Rotate
 Bit Clear
 Test & Compare
Microprocessor Assembly
Language Programming

INSTRUCTION SETS: Data Transfer

MOV INSTRUCTIONS
 MOV / MOVS
 MVN
 MOVW
 MOVT
MOV instruction
 The MOV instruction is used to transfer data within the processor.
 Between different registers or an immediate value to a register.
 the MOV instruction copies data into register or from (register or
immediate value) to register. It has the following formats:

MOV Rn, Op2 ;load Rn register with Op2 (Operand2).

 Op2 can be immediate(8 to16-bit value) or register Rm
 Example:
 MOV R2,#0x25 ;load R2 with 0x25 (R2 = 0x25)
 MOV R5,R7 ;copy contents of R7 into R5 (R5 = R7)

Notes: cannot load values larger than 0xFFFF (0–65535) into registers R0 to
R12 using the MOV instruction (for ARM CORTEX M)
 MOV instruction (Immediate Values)
 MOV R2,#0x25 ;load R2 with 0x25 (R2 = 0x25)
 MOV R1,#0x87 ;copy 0x87 into R1 (R1 = 0x87)
 MOV R1,#87 ;copy decimal value 87 into R1(R1=0x135)

Notes:
 We put # in front of every immediate value.
 If we want to present a number in hex, we put a 0x in front of it. If we put nothing in front of a
number, it is in decimal. For example, in “MOV R1,#50”, R1 is loaded with 50 in decimal,
whereas in “MOV R1,#0x50”, R1 is loaded with 50 in hex ( 80 in decimal).
 If values 0 to FF are moved into a 32-bit register, the rest of the bits are assumed to be all zeros.
For example, in “MOV R1,#0x5” the result will be R1=0x00000005; that is,
R1=00000000000000000000000000000101 in binary.
 MOVS (update flags)

Flags: Affected: C, N, Z
Format: MOVS Rd,#imm_value
Function: Load the Rd register with an immediate value
and update the flags.
Example:
MOVS R0,#0x25 ;R0=0x25,N=0,Z=0, and C=0
MOVS R0,#0x0 ;R0=0x0, N=0,Z=1, and C=0
MVN instruction
MVN instruction store the negative of OP2 (1st complement)
in Rd.
the following formats:

MVN Rn, Op2

Op2 can be immediate or register Rm

Example:
MVN R2,#0x25
MVN R5,R7
 MOVW (Move 16-bit constant)
 Format: MOVW Rd,#16-bit imm_value

 Function: Load the Rd register with an immediate value.

 The immediate value cannot be larger than 0xFFFF (0–65535).

 Example:
MOVW R1,#0x5555 ;R1=0x5555
 MOVT (Move Top)
 Format:
MOVT Rd,#imm_value
 Function: Loads the upper 16-bit of Rd register with an
immediate value.
 The immediate value cannot be larger than 0xFFFF (0–65535).
 The lower 16-bit of the Rd register remains unchanged.

 Example:
LDR R0,=0x25579934 ;R0=0x25579934
MOVT R0,#0xAAAA ;R0=0xAAAA9934
Load and Store Instructions

 ARM CPU allows direct access to all locations in the memory

but they are done with specific instructions
 Since these instructions either load the register with data from
memory or store the data in the register to the memory, they
are called the load/store instructions
 LDR and STR instructions allow data to be transferred
between register and memory.
 Variants of these instructions allow data transfers of size
byte, halfword and word.
 The load register, LDR, instruction is used to transfer data from
memory to the register.
 The store register, STR, instruction is used to transfer data from
register to memory.
18 Memory Organisation
Table 4.1 Memory Space Allocation in ARM Cortex
Recap: Cortex M4 Memory System
0xE00FFFFF 0xE000EFFF
0xFFFFFFFF
Private peripherals including Private System
Vendor specific
built-in interrupt controller (NVIC) Peripheral Control Space
memory 511MB
and debug components. Bus (PPB) (SCS)
0xE0000000 1.0MB
0xDFFFFFFF 0xE0000000 0xE000E000

External
1.0GB
Mainly used for external peripherals. device

0xA0000000
0x9FFFFFFF

External
Mainly used for external memory. 1.0GB
RAM 0x43FFFFFF

32MB Bit band alias

0x60000000 0x42000000
0x5FFFFFFF

Mainly used for peripherals. Peripheral 0.5GB 0x400FFFFF

1MB Bit band region
0x40000000
0x40000000
0x3FFFFFFF
0x23FFFFFF
Mainly used for data memory 0.5GB
SRAM 32MB Bit band alias
(e.g. static RAM).
0x20000000 0x22000000
Mainly used for program code. 0x1FFFFFFF
0x200FFFFF
Also used for exception vector Code 0.5GB 1MB Bit band region
0x20000000
table.
0x00000000
 20 Load Instruction (LDR)
Data transfer from Memory to Register
Format: Opcode destination, source

LDR Rx,=Op2 ; load immediate data into register

LDR Rd, [Rx] ; load Rd with the contents of location pointed to by Rx register.

 Rx is an address between 0x00000000 to 0xFFFFFFFF

 Op2 is immediate data (up to 32-bits)
 Load Instruction (LDR)

 tells the CPU to load (copy) into register Rd one word (32-bit or 4
bytes) of data starting from the memory location pointed to by
(stored in) Rx
Rx contains a value 0x00000000 to 0xFFFFFFFF which the
instruction will interpret as an address
 Since ARM is a byte addressable CPU, each memory location
holds one byte. So, LDR will bring in 4 bytes of data from 4
consecutive memory locations ( SRAM, Flash memory or I/ O
registers)
22 Load Instruction (LDR)

Can be byte, half word and word

LDR-word
LDRH-half word
LDRB-byte

NOTES: In ARM microcontroller, in placing of the code or data in the ARM

program memory used LITTLE ENDIAN METHOD : the low byte goes to the
low address and the high byte goes to the high address.
 Assume that R5 = 0X40000202, and locations 0X40000202
through 0X40000205 contain 0x05,0x34,0xA2 and 0x3B,
23 LDR Rd, [Rx] respectively, after running the following instruction;
LDR R7,[R5], What is the value contain in register R7?

E.g. LDR R5, =0x40000202 ; point R5 to location

0x40000202
LDR R7,[R5] ; load R7 with the contents
;of locations 0x40000202-0x40000205

Location Data
Memory to register
R5 0x40000202 0x05
0x40000203 0x34
0x40000204 0xA2
0x40000205 0x3B

R7 =0X3BA23405 R7 0x3B 0xA2 0x34 0x05

  instruction loads (copies) one byte from a
memory location pointed to by Rx into the
24 LDRB Rd, [Rx] least significant byte of Rd
 the unused portion (the upper 24 bits) of the
Rd register will be filled by all zeros

E.g. LDR R5, =0x40000202 ; point R5 to location

0x40000202
LDRB R7,[R5] ; load R7 with the contents
of locations 0x40000202

Location Data
Memory to register
R5 0x40000202 0x05
0x40000203 0x34
0x40000204 0xA2
0x40000205 0x3B

R7 =0X00000005 R7 0x00 0x00 0x00 0x05

  instruction loads (copies) half-word (16-bit or 2
bytes) starting from the memory location
25 LDRH Rd, [Rx] pointed to by Rx into the lower 16-bits of Rd
register
 the unused portion (the upper 16 bits) of the
Rd register will be filled with all zeros

E.g. LDR R5, =0x40000202 ; point R5 to location

0x40000202
LDRH R7,[R5] ; load R7 with the contents
;of locations 0x40000202-0x40000203

Location Data
Memory to register
R5 0x40000202 0x05
0x40000203 0x34
0x40000204 0xA2
0x40000205 0x3B

R7 =0X00003405 R7 0x00 0x00 0x34 0x05

26 Store Instruction (STR)

Data transfer from Register to Memory

 Format: STR Rx,[Rd]

;store register Rx into locations pointed to by Rd

 Since general purpose register is 32-bit wide (4-byte) we need four

consecutive memory locations to store the contents of Rx.
27 Store Instruction (STR)
 Can be byte, half word and word

 STR-word
 STRH-halfword
 STRB-byte
 Assume that R4 = 0X40000300 and R3 contain value
0X00234067.After running the following instruction;
28 STR Rx, [Rd] STR R3,[R4], What is the value contain in the memory
location pointed by R4?

LDR R3, =0X00234067 ; store #0X00234067 into R3

LDR R4, =0x40000300 ; point R4 to location 0x40000300
STR R3,[R4] ; load R3 into the location pointed by R4

Location Data Register to memory

R4 0x40000300 0x67
0x40000301 0x40
0x40000302 0x23
0x40000303 0x00

R3 0X00 0X23 0X40 0X67

  instruction stores (copies) the lower 16-bit
(half-word) contents of Rx to two address
29 STRH Rx, [Rd] locations with the first pointed to by the Rd
register

LDR R3, =0X00234067 ; store #0X00234067 into R3

LDR R4, =0x40000300 ; point R4 to location 0x40000300
STRH R3,[R4] ; load R3 into the location pointed by R4

Location Data Register to memory

R4 0x40000300 0x67
0x40000301 0x40
0x40000302 0x00
0x40000303 0x00

R3 0X00 0X23 0X40 0X67

  instruction stores (copies) the least significant byte of
Rx to a memory location pointed to by the Rd
30 STRB Rx, [Rd] register

LDR R3, = 0X00234067 ; store #0X00234067 into R3

LDR R4, = 0x40000300 ; point R4 to location 0x40000300
STRB R3,[R4] ; load R3 into the location pointed by R4

Location Data Register to memory

R4 0x40000300 0x67
0x40000301 0x00
0x40000302 0x00
0x40000303 0x00

R3 0X00 0X23 0X40 0X67

 EXERCISE
1) Write instructions to load value 0x95 into location with address 0x20000000.
2) Write instructions to move the contents of R2 to memory location pointed to by R8.
3) Write instructions to load values from memory locations 0x40000020–0x40000023 to R4
register.
4) Show a simple code to store values 0x30 and 0x97 into locations 0x20000015 and
0x20000016, respectively.
5) Show a simple code to load the value 0x11 into locations 0x20000010– 0x20000015.
6) Assume that R5 = 0X40000400, and locations 0X40000400 through 0X40000403 contain
0x56,0x34,0x78 and 0xAB, respectively, after running the following instruction;
LDR R7,[R5], What is the value contain in register R7?
 EXECISE
7) Assume that R4 = 0X40000100 and R3 contain value of 0X11223467.After
running the following instruction;
STR R3,[R4],
What is the value contain in the memory location pointed by R4?
8) Show the placement of data in following code:
LDR R1,=0x22334455
LDR R2,=0x20000000
STR R1,[R2]
using little endian method.
 EXERCISE
QUESTION 9

State the contents of registers and memory location after the

execution of the following program. (Please use KEIL assembler)

AREA A_SIMPLE_PROGRAM,CODE,READONLY
ENTRY
EXPORT main
main
LDR R5,=0x40000200
LDR R3,=0X11223344
STR R3,[R5]
LDRB R7,[R5]
HERE B HERE
END
34 EXERCISE
QUESTION 10
 State the contents of registers and memory location after the
execution of the following program. (Please use KEIL assembler)
MOV R2,#0x06 ;load R2 with 6
MOV R1,#0x08 ;load R1 with 8
ADD R2,R1,R2 ;R2 = R1 + R2
ADD R2,R1,R2 ;R2 = R1 + R2
LDR R5,=0x40000000 ;R5 = 0x40000000
STRB R2,[R5] ;store R2 into location pointed to by R5