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Experiment 6

Interrupts from Multiple Sources

TM4C123GH6PM implements Nested Vectored Interrupt Controller to handle the interrupts.
All the exceptions and interrupts are processed in handler mode. The processor returns to
the thread mode when it is finished with all exception processing. The NVIC has dedicated
programmable registers for storing pending status of interrupts. When an interrupt signal is
asserted on an arbitrary input of NVIC, it results in setting the pending bit of the corresponding
pending status register associated with that interrupt. The processor automatically saves its
current state to the stack when it accepts an interrupt to be serviced. The state is automatically
restored from the stack upon the exit from the interrupt service routine (ISR). (Figure 6.1).

Figure 6.1: interrupt pending and activation behavior

The Nested Vectored Interrupt Controller (NVIC) provides configurable interrupt handling abil-
ities to the processor, facilitates low-latency exception and interrupt handling. Nested interrupt
handling is where the software is prepared to accept another interrupt, even before it finishes
handling the current interrupt. When multiple different priorities can be assigned to interrupts,
the occurrence of nested interrupts is a natural consequence.

Three different phenomena can occur while dealing with nested interrupts.

1. Tail chaining

2. Late Arrival

3. Pre-emption

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Tail Chaining

The NVIC maintains knowledge of the stacked, or nested, interrupts to enable tail-chaining of
interrupts. When an exception takes place but the processor is handling another exception of
the same or higher priority, the exception will enter the pending state. When the processor
finishes executing the current exception handler, it can then proceed to process the pending
exception/interrupt request. Instead of restoring the registers back from the stack (unstacking)
and then pushing them on to the stack again (stacking), the processor skips the unstacking and
stacking steps and enters the exception handler of the pended exception as soon as possible
(Figure 6.2). In this way, the timing gap between the two exception handlers is considerably
reduced. For a memory system with no-wait state, the tail-chain latency is only six clock
cycles.

Figure 6.2: Tail chaining

Late Arrival

The NVIC and the processor core interface are closely coupled, to enable low latency interrupt
processing and efficient processing of late arriving interrupts. When an exception takes place,
the processor accepts the exception request and starts the stacking operation. If during this
stacking operation another exception of higher priority takes place, the higher priority late
arrival exception will be serviced first (Figure 6.3)

Figure 6.3: Late Arrival

4 CHAPTER 6. INTERRUPTS FROM MULTIPLE SOURCES

Pre-emption
When the exception priorities are enabled, a higher priority exception can preempt a lower
priority (correspondingly a larger value in priority level) exception i.e. when an interrupt occurs
and has priority higher than any active interrupt already being processed by the processor,
the previous interrupt state is changed to pending and newly arriving interrupt is processed
immediately by the processor (Figure 6.4).

Figure 6.4: Pre-emption

Base Priority Register

The flexibility in masking the interrupts is introduced by the BASEPRI register. The interrupt
masking by the BASEPRI is performed depending on the current priority level con

guration. Since the number of priority levels in TM4C123GH6PM is 8, it requires 3 bits to be

used by the BASEPRI register (Figure 6.5).

Figure 6.5: 3-bit implementation for the BASEPRI register

When BASEPRI is set to a non-zero value, it blocks all the interrupts of the same and lower
priority, while it allows the processor to accept the interrupts of higher priority for process-
ing. When BASEPRI is set to 0, it is disabled. These interrupt masking registers are accessed
through special register access instructions. Move to special register from general-purpose regis-
ter (MSR) and move special register to general-purpose register (MRS) assembly programming
instructions are used for this purpose.
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EXPORT EnablePriorityInterrupts

EnablePriorityInterrupts

MOV R5 , #0 x 4 0 ; s e t b a s e p r i o r i t y 2
MSR BASEPRI , R0
BX LR

Source Code
For this task, two interrupts are configured with different priorities on PB4 and PF4. Base
priority value will govern which interrupt is accepted. Template for the code has been provided
on piazza. Understand the code and complete the missing portions. Consult the datasheet for
complete understanding of the code.

Note1: The register map for System Control module (for RCGCGPIO) is to be consulted from
article 5.4 - System Control - Register Map of the controller datasheet.

Note2: Consult table 2-8 and 2-9 for the entries of the vector table from article 2.5.2 The
Cortex-M4F Processor - Exception Types of the datasheet.

Note3: The register map for NVIC is to be consulted from article 3.2 - Cortex-M4 Periph-
erals - Register Map of the controller datasheet.

Note4: The register map for GPIO is to be consulted from article 10.4 - General-Purpose
Input/Outputs (GPIOs) - Register Map of the controller datasheet.