8085 Interrupts

Learning Objectives I
 Describe the interrupt process
 Explain the difference between Polling and Interrupt
 Explain the difference between a nonmaskable and a
maskable interrupt
 Explain the difference between a direct and a
vectored interrupt
 List the priority of interrupt in 8085
 List the 8085 vectored interrupts, nonmaskable
interrupt and their vectored addresses

04/23/2024 2
8085 Interrupts

 What is interrupt?
 Vectored interrupt
 Non vectored interrupt
 Enable and disable interrupt instructions
 Pending interrupts
Necessity of Interrupts

 Polling
 In polling, CPU steadily checks whether the device needs
attention.
 Interrupt Method
 In interrupt, the device notices the CPU that it requires its
attention
What is interrupt?

 An interrupt is considered to be an emergency signal

- The Microprocessor should respond to it as soon as possible.
 When the Microprocessor receives an interrupt signal, it
suspends the currently executing program and jumps to an
Interrupt Service Routine (ISR) to respond to the
incoming interrupt.
Interrupt Event Sequence
normal interrupt resume normal
processing occurs processing
1 2 7

save PC retrieve PC
3 6
on stack from stack

branch to 4 5
ISR
execute
ISR
6
 Classification of Interrupts
 Single Level Interrupts
 Multilevel Interrupts
 Maskable and Non-Maskable Interrupts
 Vectored Interrupts
Single Level Interrupts
Multi Level Interrupts
Multi Level Interrupts

 Flowchart
 Maskable and Non-maskable Interrupts
Maskable Interrupts
(Can be delayed or Rejected)

 If maskable interrupt is asserted, it will only interrupt the

processor if it is enabled ( unmasked ).
 Maskable interrupts can be enabled ( unmasked ) or disabled
( masked ) by software.
 Most maskable interrupts automatically become disabled
(masked) after an interrupt has occurred.
 It requires further software commands to re-enable maskable
interrupts.

04/23/2024 11
 Maskable and Non-maskable Interrupts
Non-maskable Interrupts
(CANNOT be delayed or Rejected)

 If a non-maskable interrupt is asserted, it will always interrupt the

processor.

 The non-maskable interrupt is not affected by the value of the

Interrupt Enable flip-flop.

 There is no software mechanism to prevent the processor being

interrupted by a non-maskable interrupt.

04/23/2024 12
Direct and Vectored Interrupts
Direct interrupts

 The interrupting device need to provide the interrupt signal

only.
(i.e. to assert the signal to the interrupt pin of the
processor.)
 The address of the subroutine is already known to the
Microprocessor.

 The address of the first instruction of the ISR for the

particular interrupt is pre-programmed into the CPU.

04/23/2024 13
Direct and Vectored Interrupts
Vectored interrupts

 Microprocessor requires external hardware to supply the

address of the service routine.
 The interrupting device has to supply both the interrupt
signal and the 16-bit address of the first instruction of the
ISR.
 Interrupt service routines for vectored interrupts can reside
anywhere in the memory map of the computer system.

04/23/2024 14
Hardware Interrupts

 The 8085 has five hardware interrupts

 TRAP
 RST 7.5
 RST 6.5
 RST 5.5
 INTR
Interrupt vector and vector table
Interrupt structure of 8085
SIM: Set Interrupt Mask
Pending Interrupts: RIM
TRAP Interrupt
Summary
Software Interrupts