Madrid SB Schematics

5 4 3 2 1
Project code :3PD00L010001 Project Name :PIM81L/aMadrid

Title Page Title Page
PCB No :13094 Size : 165x240mm
COVER PAGE 1 Run Power & Sequence 35 Revision :SB
BLACK DIAGRAM 2 DC to DC_12V(SY8246A) 36
D TABLE OF CONTENT
CPU (DMI/FDI)
3
4
DC to DC_5V/3D3V(RT8243B)
DC to DC_DDR3 1D5VS3
37
38 Madrid_SB Schematics Document D
HASWELL INTEL LYNX POINT

CPU (DDR) 5 DC to DC_1D5V(Reserve) 39
CPU (Power) 6 DC to DC_1D05V(APL5611) 40
CPU (Thermal/JTAG) 7 CPUCORE_ISL95825(1/2) 41
CPU(VSS)
DDR3-SODIMM1
8
9
CPUCORE_ISL95825(2/2)
HDMI IN
42
43 Haswell LGA1150
M
DDR3-SODIMM2 10 HDMI OUT 44
PCH (FDI/PCIE/DMI/USB) 11 HDD/ODD 45
aMadrid 195" UMA SKU : U,N,O S: Scalar
O
PCH (SATA/FAN/DP/VGA) 12 Mini PCIE Card WLAN and BT 46
aMadrid 195" GPU SKU : U,N,O,G A: AMP
C C
PCH (AUDIO/GPIO/SPI) 13 Mini PCIE Card TV Tuner 47

aMadrid 23" UMA SKU : S,A,L,O L : AspireLINK
.C
PCH CLOCK 14 Mini PCIE Card mSATA(res) 48
PCH ( POWER1) 15 PWRBTN / SIDE KEY / LED 49 aMadrid 23" GPU SKU : S,A,L,G,O (unmount Q58) G: GPU
PCH ( STRAPS) 16 Debug connector 50 O: OCP
AM
OCP BOM manual control:
PCH(VSS) 17 GPU (1/5): PEG 51
R439,R440,R441,R862 [63.R0031.16L] N: non AMP
Audio Codec_ALC269 18 GPU (2/5): DIGITALOUT 52 Mount by BOM change list when w/o OCP U: UMA(NOT S)
Audio_ SW/ AMP/Con/DePop 19 GPU (3/5): VRAM I/F 53 R: Unmount
SIO ITE8732F_CX 20 GPU (4/5): GPIO/STRAP 54 New P/N for manual control (1A):
T
Scalar-RTD2586HD 21 GPU (5/5): PWR/GND 55
LA
B
RTD2136 eDP to LVDS 22 GPU VRAM1 (1/4) 56 manual control (SB): VGA1 : 071.0N15S.0B0U B
LCD/Inverter Connector 23 GPU VRAM3 (2/4) 57 23U : SCA1,DCIN2 SCA1 : 071.02586.000G

Card reader_RTS5143 24 GPU VRAM2 (3/4) 58 23G : SCA1,VGA1 SKT2 : 022.70001.0121
Aspire Link 25 GPU VRAM4 (4/4) 59 DCIN2 : 22.10261.661
IX
SideIO_USB30 26 GPU PWR_NVVDD(NCP81172) 60
Rear USB/TOU/Dongle/Web Cam 27 GPU PWR_1D5V_VGA_S0 61
LAN-RTL8111GA 28 GPU PWR_1D05V/3D3V
.F 62
SPI/RTC 29 Stand off&EMI Cap&DUMMY BOM 63 GPU SKU:
Hynix H5TC4G63AFR-11C
KN.0040G.002 -> R619=4.99K(64.49915.6DL)
W
Scalar Power 30 DUMMY PARTS 64
A
USB 2.0 Power SW 31 SYSTEM & GPU POWER SEQUENCE 65 Samsung K4W4G1646D-BC1A <Core Design> A
Battery Charger(Reserve) 32 SMBUS table 66 KN.0040B.005 -> R619=15K(64.15025.6DL)

Wistron Corporation
W
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

ADAPTER OCP / S3 reduction 33 THERMAL/AUDIO BLOCK DIAGRAM 67 Taipei Hsien 221, Taiwan, R.O.C.
Title
DCIN JACK 34 POWER BLOCK DIAGRAM 68 Cover Page
Size Document Number Rev
W
Custom
Madrid SA
Date: Tuesday, January 21, 2014 Sheet 1 of 68
5 4 3 2 1
5 4 3 2 1
Project code :3PD00L010001

PCB No :13094
Madrid Block Diagram (GPU) Revision :SA
Project Name :Madrid SYSTEM DC/DC
RT8223MGQW 31
INPUTS OUTPUTS
DDRIII 1333/1600 Channel A DDRIII Slot 0 5V_AUX_S5
D VRAM 3D3V_AUX_S5 D
1066/1333 DCBATOUT 5V_Charger
3D3V_A
2GB Intel CPU
DDRIII 1333/1600 Channel B DDRIII Slot 1 CPU DC/DC
Haswell 1066/1333 ISL95832HRTZ 32~33
DDR3
900MHz Intel pGA Core INPUTS OUTPUTS
HDMI OUT
DDI DCBATOUT VCC_CORE
DDIB
M
49 SYSTEM DC/DC
ISL95832HRTZ 34
PCIe x 4(Gen3_8Gb/s) RTD2136 LVDS INPUTS OUTPUTS
eDP
O
(Synergy) DCBATOUT VCC_GFXCORE
Nvidia N15S-GT
SYSTEM DC/DC
Scalar BD ISL95870BHRZ 35
.C
LVDS LCD
RTD2586 INPUTS OUTPUTS
DMIx4 DCBATOUT 1D05V_VTT
FDIx2 SYSTEM DC/DC

(FDI Port for legacy VGA HDMI IN
AM
C TPS51116RGER 36 C
support on PCH)
Line out INPUTS OUTPUTS
1D5V_S3
DCBATOUT 0D75V_S0
Mic in SW DDR_VREF_S3
Debug Port Intel Amp 26
(Reserve)
RGB CRT LDO
RT9025-25PSP 37
T
Front side AZALIA
INPUTS OUTPUTS
USB3.0 x 1 PCH SW
USB3.0 ALC269 SPDIF
LA
Lynx Point 3D3V_S0 1D8V_S0
H81 Int Digital MIC IN
From Webcam
SYSTEM DC/DC
TPS51461RGER 38
INPUTS OUTPUTS
Web cam USB2.0 x 7 2 USB 3.0 / 8 USB 2.0/1.1 ports PCIE x 1 5V_S5 0D85V_S0
IX
ETHERNET (10/100/1000Mb) MDI RJ45
RTL8111GA CONN
Front side High Definition Audio 25MHZ OSC PCB LAYER
Card Reader SATA ports (4)
B
.F
PCIE ports (6) PCIE x 1,USB x 1 Mini-Card L1:Top L4:Signal B
L2:VCC L5:GND
TOUCH Flash ROM SPI LPC I/F Wireless Lan+ Bluetooth L3:Signal L6:Bottom
8MB ACPI 1.1
W
PCIE x 1 AspireLink 26
KB,MS DON CONN
Rear side
W
USB2.0*3 SATA x 2 ODD (SATA2_3Gb/s)

LPC Bus
LPC debug port HDD (SATA3_6Gb/s)

W
Flash ROM SPI SIO ITE8732 Temp Ctrl

125KB
A A
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Fan Scalar Ctrl
Title
25
BLOCK DIAGRAM
Custom
Madrid SA
5 4 3 2 1
A B C D E
4 PCH Strapping Huron River Schematic Checklist Rev.0_7 4

Name Schematics Notes
SPKR Reboot option at power-up
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ
- 10-kΩ weak pull-up resistor.
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
M
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile.
GNT2#/GPIO53 Mobile: Used as GPIO only
GNT1#/GPIO51 Pull-up resistors are not required on these signals.
If pull-ups are used, they should be tied to the Vcc3_3power rail.
O
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor.
SPI_MOSI
Disable Danbury:Left floating, no pull-down required.
.C
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm
weak pull-up resistor [CRB has it pulled up
with 1-kohm no-stuff resistor]
Processor Strapping Huron River Schematic Checklist Rev.0_7
AM
3 NV_ALE Pin Name Strap Description Configuration (Default value for each bit is Default 3
Disable Danbury:Leave floating (internal pull-down) 1 unless specified otherwise) Value
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low. CFG[2] PCI-Express Static 1: Normal Operation.
Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Disabled - No Physical Display Port attached to
T
CFG[4] 1: Embedded DisplayPort.
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. 0
/GPIO[33] Platform design should provide appropriate pull-up or pull-down depending on Enabled - An external Display Port device is
the desired settings. If a jumper option is used to tie this signal to GND as 0: connectd to the EMBEDDED display Port
LA
required by the functional strap, the signal should be pulled low through a weak
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
strapping functions. Straps function 2 disabled
01 : Reserved - (Device 1 function 1 disabled ; 11
function 2 enabled)
IX
00 : x8, x4, x4 - Device 1 functions 1 and 2
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. enabled
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
GPIO15
.F
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher 0: PEG Wait for BIOS for training
2 suite with confidentiality 2
Note : This is an un-muxed signal.
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low.
Sampled at rising edge of RSMRST#.
W
CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
W
enabled.
Default = Do not connect (floating)

High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
W
Low (0) = Disables the VccVRM. Need to use on-board filter

circuits for analog rails.
1 <Core Design>
1
Wistron Corporation
Title
Table of Content
A3
Madrid SA
5 4 3 2 1
DMI 20131010 Madrid SA Charles

checked
CPU1D 4 OF 10
11 DMI_IT_MR_DP[0..3] 2013/04/03 20131010 Madrid SA Charles V_VCCIOA_LOAD
11 DMI_IT_MR_DN[0..3] GPU PEG BUS Rossi delete PCIEX16 signal checked p73 HASWELL
DDIB_TXB0
E17 DDSP_B_TX_DATA0
F17 DDSP_B_TX_DATA0#
11 DMI_MT_IR_DP[0..3] DDIB_TXB#0
1
CPU1C 3 OF 10 FDI_CSYNC D16 F18 DDSP_B_TX_DATA1
11 DMI_MT_IR_DN[0..3] FDI_CSYNC DDIB_TXB1 DDSP_B_TX_DATA1#
R77 G18
D HASWELL A12 PEG_TXP0_C C23 (G) 1 2 SCD22U10V2KX-1GP 24D9R2F-L-GP FDI_INT D18 DDIB_TXB#1 D
PEG_TX0 PEG_TXN0_C C24 PEG_TXP0 51 FDI_INT DDSP_B_TX_DATA2
HDMIOUT
E15 B12 (G) 1 2 SCD22U10V2KX-1GP G19
51 PEG_RXP0 PEG_RX0 PEG_TX#0 PEG_TXN0 51 DDIB_TXB2 DDSP_B_TX_DATA2#
F15 H19
51 PEG_RXN0
2
PEG_RX#0 PEG_TXP1_C C21 FDI_COMP DDIB_TXB#2 DDSP_B_TX_DATA3
FDI
B11 (G) 1 2 SCD22U10V2KX-1GP R4 F20
PEG_TX1 PEG_TXN1_C C22 PEG_TXP1 51 DP_COMP DDIB_TXB3 DDSP_B_TX_DATA3#
D14 C11 (G) 1 2 SCD22U10V2KX-1GP G20
51 PEG_RXP1 PEG_RX1 PEG_TX#1 PEG_TXN1 51 CK_DP_DN DDIB_TXB#3
11 FDI_CSYNC E14 U5
51 PEG_RXN1 PEG_RX#1 PEG_TXP2_C C19 CK_DP_DP SSC_DPLL_REF_CLK#
C10 (G) 1 2 SCD22U10V2KX-1GP U6 D19
11 FDI_INT PEG_TX2 PEG_TXN2_C C20 PEG_TXP2 51 SSC_DPLL_REF_CLK DDIC_TXC0
E13 D10 (G) 1 2 SCD22U10V2KX-1GP E19
11 FDI_TX_DN[0..1] 51 PEG_RXP2 PEG_RX2 PEG_TX#2 PEG_TXN2 51 DISP_UTIL_CPU DDIC_TXC#0
F13 1 E16 C20
11 FDI_TX_DP[0..1] 51 PEG_RXN2 PEG_RX#2 PEG_TXP3_C C17 EDP_DISP_UTIL DDIC_TXC1
D12 PEG_TX3
B9
C9 PEG_TXN3_C C18
(G) 1
(G) 1
2 SCD22U10V2KX-1GP
2 SCD22U10V2KX-1GP
PEG_TXP3 51
TPAD28-1-GP-U TP40
1 TP_DISP_K11 K11
FDI DDIC_TXC#1
D20
14 CK_DP_DP 51 PEG_RXP3 PEG_RX3 PEG_TX#3 PEG_TXN3 51 TP_DISP_J12 RSVD_TP_K11 20131010 Madrid SA Charles DP
E12 TPAD28-1-GP-U TP54 1 J12 D21 Madrid has no DP
14 CK_DP_DN 51 PEG_RXN3 PEG_RX#3 RSVD_TP_J12 DDIC_TXC2
C8 TPAD28-1-GP-U TP60 E21
E11 PEG_TX4 D8 DDIC_TXC#2 C22
PEG_RX4 PEG_TX#4 FDI_TX_DN0 DDIC_TXC3 eDP
F11 B14 D22
PEG_RX#4 FDI_TX_DP0 FDI0_TX0#0 DDIC_TXC#3 Scalar & LVDS Transmiter
HDMIOUT
B7 A14
F10 PEG_TX5 C7 FDI0_TX00 B15 DPD_LANE0P_S
G10 PEG_RX5 PEG_TX#5 FDI_TX_DN1 C13 DDID_TXD0 C15 DPD_LANE0N_S
20131014 Madrid SA Charles E9 PEG_RX#5 A6 FDI_TX_DP1 B13 FDI0_TX0#1 DDID_TXD#0 A16 DPD_LANE1P_S
need HDMIOUT F9 PEG_RX6 PEG_TX6 B6 FDI0_TX01 DDID_TXD1 B16 DPD_LANE1N_S
PEG_RX#6 PEG_TX#6 DDID_TXD#1
M
F8
44 DDSP_B_TX_DATA0 G8 PEG_RX7 B5 B17
C 44 DDSP_B_TX_DATA0# D3 PEG_RX#7 PEG_TX7 C5 DDID_TXD2 C17 C
44 DDSP_B_TX_DATA1 D4 PEG_RX8 PEG_TX#7 20131010 Madrid SA Charles DDID_TXD#2 A18
44 DDSP_B_TX_DATA1# E4 PEG_RX#8 E1 checked DDID_TXD3 B18
20131007 Madrid SA Charles
44 DDSP_B_TX_DATA2 E5 PEG_RX9 PEG_TX8 E2 Connect to PCH 16,17 DDID_TXD#3 canncel 3&4 pairs
44 DDSP_B_TX_DATA2# F5 PEG_RX#9 PEG_TX#8
O
44 DDSP_B_TX_DATA3 F6 PEG_RX10 F2 HASWE1NFU
44 DDSP_B_TX_DATA3# G4 PEG_RX#10 PEG_TX9 F3
PEG_RX11 PEG_TX#9 (62.10055.761)
G5
H5 PEG_RX#11 G1
H6 PEG_RX12 PEG_TX10 G2
J4 PEG_RX#12 PEG_TX#10
.C
J5 PEG_RX13 H2
K5 PEG_RX#13 PEG_TX11 H3
K6 PEG_RX14 PEG_TX#11
L4 PEG_RX#14 J1
V_VCCIOA_LOAD L5 PEG_RX15 PEG_TX12 J2
PEG_RX#15 PEG_TX#12 K2
DMI_IT_MR_DP0 U3 PEG_TX13 K3
DMI_IT_MR_DN0 DMI_RX0 PEG_TX#13
T3 M2 20131027 CM
AM
DMI_IT_MR_DP1 U1 DMI_RX#0 PEG_TX14 M3
DMI_IT_MR_DN1 V1 DMI_RX1 PEG_TX#14 L1
DMI_RX#1 PEG_TX15
1
L2
DMI_IT_MR_DP2 PEG_TX#15
EDP
B R76 W2 B
DMI_IT_MR_DN2 V2 DMI_RX2 AA4 DMI_MT_IR_DP0
24D9R2F-L-GP DMI_RX#2 DMI_TX0
DMI_IT_MR_DP3 DMI_MT_IR_DN0
To SCALAR & 2136 Colay DMI_IT_MR_DN3
Y3
W3 DMI_RX3 DMI DMI_TX#0
AA5
2
21 DPD_LANE0N_S DMI_RX#3 AB3 DMI_MT_IR_DP1

21 DPD_LANE0P_S TPAD28-1-GP-U TP37 1 TP_PEG_D1 D1 DMI_TX1 AB4 DMI_MT_IR_DN1
21 DPD_LANE1N_S TPAD28-1-GP-U TP35 1 TP_PEG_C2 C2 RSVD_TP_D1 DMI_TX#1
21 DPD_LANE1P_S TPAD28-1-GP-U TP34 1 TP_PEG_B3 B3 RSVD_TP_C2 AC5 DMI_MT_IR_DP2
TPAD28-1-GP-U TP38 1 TP_PEG_A4 A4 RSVD_TP_B3 DMI_TX2 AC4 DMI_MT_IR_DN2
T
RSVD_TP_A4 DMI_TX#2
PEG_COMP P3 AC1 DMI_MT_IR_DP3
PEG_RCOMP DMI_TX3 AC2 DMI_MT_IR_DN3
DMI_TX#3
LA
HASWE1NFU
(62.10055.761)
<Core Design>

A checked Wistron Corporation A
Connect to PCH 16,17
IX
20131007 Madrid SA Charles 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
change Net to follow Pisa2
eDP Net Colay in Sheet 31,32,47 Title
CPU uLGA (DMI/FDI)

Custom
Madrid SA
.F Date: Tuesday, January 21, 2014 Sheet 4 of 68
5 4 3 2 1
W
W
W
5 4 3 2 1
DDR DATA
9 M_A_DQ[0..63]
10 M_B_DQ[0..63]
9 M_A_DQS[0..7]
9 M_A_DQS#[0..7]
10 M_B_DQS[0..7]
10 M_B_DQS#[0..7]
2013/04/10
D
DDR CMD/ADD
Rossi Change DIMM Net name reference swift D
9 M_A_A[0..15]
10 M_B_A[0..15]
9 M_A_WE#
9 M_A_CAS#
9 M_A_RAS#
9 M_A_BS0 1 OF 10
CPU1A
9 M_A_BS1 2 OF 10
CPU1B
9 M_A_BS2 M_A_DQ0 AD38 HASWELL AU13 M_A_A0
M_A_DQ1 AD39 SA_DQ0 SA_MA0 AV16 M_A_A1 M_B_DQ0 AE34 HASWELL AL19 M_B_A0
M
10 M_B_WE# M_A_DQ2 SA_DQ1 SA_MA1 M_A_A2 M_B_DQ1 SB_DQ0 SB_MA0 M_B_A1
AF38 AU16 AE35 AK23
10 M_B_CAS# M_A_DQ3 AF39 SA_DQ2 SA_MA2 AW17 M_A_A3 M_B_DQ2 AG35 SB_DQ1 SB_MA1 AM22 M_B_A2
10 M_B_RAS# M_A_DQ4 SA_DQ3 SA_MA3 M_A_A4 M_B_DQ3 SB_DQ2 SB_MA2 M_B_A3
AD37 AU17 AH35 AM23
10 M_B_BS0 M_A_DQ5 AD40 SA_DQ4 SA_MA4 AW18 M_A_A5 M_B_DQ4 AD34 SB_DQ3 SB_MA3 AP23 M_B_A4
10 M_B_BS1 M_A_DQ6 SA_DQ5 SA_MA5 M_A_A6 M_B_DQ5 SB_DQ4 SB_MA4 M_B_A5
AF37 AV17 AD35 AL23
10 M_B_BS2 M_A_DQ7 SA_DQ6 SA_MA6 M_A_A7 M_B_DQ6 SB_DQ5 SB_MA5 M_B_A6
AF40 AT18 AG34 AY24
M_A_DQ9 AH40 SA_DQ7 SA_MA7 AU18 M_A_A8 M_B_DQ7 AH34 SB_DQ6 SB_MA6 AV25 M_B_A7
O
M_A_DQ13 AH39 SA_DQ8 SA_MA8 AT19 M_A_A9 M_B_DQ8 AL34 SB_DQ7 SB_MA7 AU26 M_B_A8
M_A_DQ10 AK38 SA_DQ9 SA_MA9 AW11 M_A_A10 M_B_DQ9 AL35 SB_DQ8 SB_MA8 AW25 M_B_A9
M_A_DQ11 SA_DQ10 SA_MA10 M_A_A11 M_B_DQ10 SB_DQ9 SB_MA9 M_B_A10
DDR CTRL
AK39 AV19 AK31 AP18
M_A_DQ12 AH37 SA_DQ11 SA_MA11 AU19 M_A_A12 M_B_DQ11 AL31 SB_DQ10 SB_MA10 AY25 M_B_A11
M_A_DQ8 AH38 SA_DQ12 SA_MA12 AY10 M_A_A13 M_B_DQ12 AK34 SB_DQ11 SB_MA11 AV26 M_B_A12
9 M_A_DIM0_CS#0 M_A_DQ14 AK37 SA_DQ13 SA_MA13 AT20 M_A_A14 M_B_DQ13 AK35 SB_DQ12 SB_MA12 AR15 M_B_A13
9 M_A_DIM0_CS#1 M_A_DQ15 SA_DQ14 SA_MA14 M_A_A15 M_B_DQ14 SB_DQ13 SB_MA13 M_B_A14
.C
AK40 AU21 AK32 AV27
M_A_DQ17 AM40 SA_DQ15 SA_MA15 M_B_DQ15 AL32 SB_DQ14 SB_MA14 AY28 M_B_A15
M_A_DQ21 AM39 SA_DQ16 AW10 M_A_DIM0_ODT0 M_B_DQ17 AN34 SB_DQ15 SB_MA15
9 M_A_DIM0_CKE0 M_A_DQ18 AP38 SA_DQ17 SA_ODT0 AY8 M_A_DIM0_ODT1 M_B_DQ21 AP34 SB_DQ16 AM17 M_B_DIM0_ODT0
9 M_A_DIM0_CKE1 M_A_DQ19 SA_DQ18 SA_ODT1 M_B_DQ19 SB_DQ17 SB_ODT0 M_B_DIM0_ODT1
AP39 AW9 AN31 AL16
M_A_DQ20 AM37 SA_DQ19 SA_ODT2 AU8 M_B_DQ23 AP31 SB_DQ18 SB_ODT1 AM16
SA_DQ20 SA_ODT3 2013/04/10 SB_DQ19 SB_ODT2
M_A_DQ16 AM38 Rossi del M_B_DQ20 AN35 AK15 2013/04/10
9 M_A_DIM0_ODT0 M_A_DQ22 SA_DQ21 M_B_DQ16 SB_DQ20 SB_ODT3
AP37 AP35 Rossi del
9 M_A_DIM0_ODT1 M_A_DQ23 AP40 SA_DQ22 AW33 M_B_DQ18 AN32 SB_DQ21 AM26
AM
M_A_DQ25 AV37 SA_DQ23 SA_ECC_CB0 AV33 M_B_DQ22 AP32 SB_DQ22 SB_ECC_CB0 AM25
C C
M_A_DQ29 AW37 SA_DQ24 SA_ECC_CB1 AU31 M_B_DQ25 AM29 SB_DQ23 SB_ECC_CB1 AP25
10 M_B_DIM0_CS#0 M_A_DQ26 AU35 SA_DQ25 SA_ECC_CB2 AV31 M_B_DQ28 AM28 SB_DQ24 SB_ECC_CB2 AP26
10 M_B_DIM0_CS#1 M_A_DQ27 AV35 SA_DQ26 SA_ECC_CB3 AT33 M_B_DQ27 AR29 SB_DQ25 SB_ECC_CB3 AL26
M_A_DQ28 AT37 SA_DQ27 SA_ECC_CB4 AU33 M_B_DQ30 AR28 SB_DQ26 SB_ECC_CB4 AL25
M_A_DQ24 AU37 SA_DQ28 SA_ECC_CB5 AT31 M_B_DQ24 AL29 SB_DQ27 SB_ECC_CB5 AR26
10 M_B_DIM0_CKE0 M_A_DQ30 AT35 SA_DQ29 SA_ECC_CB6 AW31 M_B_DQ29 SB_DQ28 SB_ECC_CB6
10 M_B_DIM0_CKE1 SA_DQ30 SA_ECC_CB7
Can be left as no connects AL28
SB_DQ29 SB_ECC_CB7
AR25 Can be left as no connects
M_A_DQ31 AW35 if no support ECC. M_B_DQ26 AP29 if no support ECC.
M_A_DQ33 AY6 SA_DQ31 AV12 M_A_BS0 M_B_DQ31 AP28 SB_DQ30 AK17 M_B_BS0
M_A_DQ37 AU6 SA_DQ32 SA_BS0 AY11 M_A_BS1 M_B_DQ32 AR12 SB_DQ31 SB_BS0 AL18 M_B_BS1
10 M_B_DIM0_ODT0 M_A_DQ34 SA_DQ33 SA_BS1 M_A_BS2 M_B_DQ33 SB_DQ32 SB_BS1 M_B_BS2
AV4 AT21 AP12 AW28
10 M_B_DIM0_ODT1 M_A_DQ35 AU4 SA_DQ34 SA_BS2 M_B_DQ34 AL13 SB_DQ33 SB_BS2
M_A_DQ36 AW6 SA_DQ35 AV22 M_A_DIM0_CKE0 M_B_DQ35 AL12 SB_DQ34 AW29 M_B_DIM0_CKE0
T
M_A_DQ32 AV6 SA_DQ36 SA_CKE0 AT23 M_A_DIM0_CKE1 M_B_DQ36 AR13 SB_DQ35 SB_CKE0 AY29 M_B_DIM0_CKE1
M_A_DQ38 AW4 SA_DQ37 SA_CKE1 AU22 M_B_DQ37 AP13 SB_DQ36 SB_CKE1 AU28
SA_DQ38 SA_CKE2 2013/04/10 SB_DQ37 SB_CKE2
M_A_DQ39 AY4 AU23 Rossi del M_B_DQ38 AM13 AU29 2013/04/10
M_A_DQ41 AR1 SA_DQ39 SA_CKE3 M_B_DQ39 AM12 SB_DQ38 SB_CKE3
SA_DQ40 SB_DQ39 Rossi del
M_A_DQ45 AR4 AU14 M_A_DIM0_CS#0 M_B_DQ45 AR9
LA
M_A_DQ42 SA_DQ41 SA_CS#0 M_A_DIM0_CS#1 M_B_DQ41 SB_DQ40
DDR CLOCK
AN3 AV9 AP9
M_A_DQ43 AN4 SA_DQ42 SA_CS#1 AU10 M_B_DQ47 AR6 SB_DQ41
SA_DQ43 SA_CS#2 2013/04/10 SB_DQ42
M_A_DQ44 AR2 AW8 Rossi del M_B_DQ43 AP6
9 M_A_DIM0_CLK_DDR0 M_A_DQ40 AR3 SA_DQ44 SA_CS#3 M_B_DQ44 AR10 SB_DQ43 AP17 M_B_DIM0_CS#0
9 M_A_DIM0_CLK_DDR#0 M_A_DQ46 AN2 SA_DQ45 AY15 M_A_DIM0_CLK_DDR0 M_B_DQ40 AP10 SB_DQ44 SB_CS#0 AN15 M_B_DIM0_CS#1
9 M_A_DIM0_CLK_DDR1 M_A_DQ47 AN1 SA_DQ46 SA_CK0 AY16 M_A_DIM0_CLK_DDR#0 M_B_DQ46 AR7 SB_DQ45 SB_CS#1 AN17
9 M_A_DIM0_CLK_DDR#1 SA_DQ47 SA_CK#0 SB_DQ46 SB_CS#2 2013/04/10
M_A_DQ49 AL1 AW15 M_A_DIM0_CLK_DDR1 M_B_DQ42 AP7 AL15
SA_DQ48 SA_CK1 SB_DQ47 SB_CS#3 Rossi del
M_A_DQ53 AL4 AV15 M_A_DIM0_CLK_DDR#1 M_B_DQ52 AM9
M_A_DQ50 AJ3 SA_DQ49 SA_CK#1 AV14 M_B_DQ53 AL9 SB_DQ48 AM20 M_B_DIM0_CLK_DDR0
10 M_B_DIM0_CLK_DDR0 SA_DQ50 SA_CK2 2013/04/10 SB_DQ49 SB_CK0
M_A_DQ51 AJ4 AW14 Rossi del M_B_DQ50 AL6 AM21 M_B_DIM0_CLK_DDR#0
10 M_B_DIM0_CLK_DDR#0 SA_DQ51 SA_CK#2 SB_DQ50 SB_CK#0
IX
M_A_DQ52 AL2 AW13 M_B_DQ55 AL7 AP22 M_B_DIM0_CLK_DDR1
10 M_B_DIM0_CLK_DDR1 M_A_DQ48 AL3 SA_DQ52 SA_CK3 AY13 M_B_DQ48 AM10 SB_DQ51 SB_CK1 AP21 M_B_DIM0_CLK_DDR#1
10 M_B_DIM0_CLK_DDR#1 M_A_DQ54 AJ2 SA_DQ53 SA_CK#3 M_B_DQ49 AL10 SB_DQ52 SB_CK#1
M_A_DQ55 AJ1 SA_DQ54 AW12 TP_RSVD_AW12 1 TP110 TPAD28-1-GP-U M_B_DQ54 AM6 SB_DQ53 AN20
SA_DQ55 RSVD_AW12 SB_DQ54 SB_CK2 2013/04/10
M_A_DQ57 AG1 M_B_DQ51 AM7 AN21 Rossi del
M_A_DQ61 AG4 SA_DQ56 M_B_DQ61 AH6 SB_DQ55 SB_CK#2 AP19
M_A_DQ58 AE3 SA_DQ57 M_B_DQ60 AH7 SB_DQ56 SB_CK3 AP20
M_A_DQ59 AE4 SA_DQ58 M_B_DQ59 AE6 SB_DQ57 SB_CK#3
SA_DQ59 SB_DQ58
B
DDR OTHERS
M_A_DQ60
M_A_DQ56
M_A_DQ62
AG2
AG3
AE2
SA_DQ60
SA_DQ61
.F M_B_DQ63
M_B_DQ56
M_B_DQ57
AE7
AJ6
AJ7
SB_DQ59
SB_DQ60
SB_CAS#
RSVD_AL20
AP16
AL20
AM18
M_B_CAS#
M_B_RAS# B
33 SM_DRAMRST# M_A_DQ63 AE1 SA_DQ62 M_B_DQ58 AF6 SB_DQ61 SB_RAS# AK16 M_B_WE#
M_A_DQS0 AE39 SA_DQ63 M_B_DQ62 AF7 SB_DQ62 SB_WE#
10 M_VREF_DQ_DIMM1_C M_A_DQS1 SA_DQS0 M_B_DQS0 SB_DQ63 M_VREF_DQ_DIMM0_C
AJ39 AF35 AB39
9 M_VREF_DQ_DIMM0_C M_A_DQS2 SA_DQS1 M_B_DQS1 SB_DQS0 SA_DIMM_VREFDQ M_VREF_DQ_DIMM1_C
AN39 AL33 AB40
M_A_DQS3 AV36 SA_DQS2 M_B_DQS2 AP33 SB_DQS1 SB_DIMM_VREFDQ
W
M_A_DQS4 AV5 SA_DQS3 M_B_DQS3 AN28 SB_DQS2
M_A_DQS5 AP3 SA_DQS4 M_B_DQS4 AN12 SB_DQS3
SA_DQS5 SB_DQS4
2
M_A_DQS6 AK3 AU12 M_A_RAS# M_B_DQS5 AP8
M_A_DQS7 SA_DQS6 SA_RAS# M_B_DQS6 SB_DQS5
SCD022U16V2JX-GP
C73
SCD022U16V2JX-GP
C71
AF3 AL8
AV32 SA_DQS7 AU11 M_A_WE# M_B_DQS7 AG7 SB_DQS6
1
M_A_DQS#0 AE38 SA_DQS8 SA_WE# AN25 SB_DQS7
M_A_DQS#1 AJ38 SA_DQS#0 AV20 TP_RSVD_AV20 1 TP107 TPAD28-1-GP-U M_B_DQS#0 AF34 SB_DQS8
M_A_DQS#2 AN38 SA_DQS#1 RSVD_AV20 M_B_DQS#1 AK33 SB_DQS#0
M_VREF_DQ_DIMM1_R
M_VREF_DQ_DIMM0_R
W
M_A_DQS#3 AU36 SA_DQS#2 AW27 TP_RSVD_AW27 1 TP104 TPAD28-1-GP-U M_B_DQS#2 AN33 SB_DQS#1
M_A_DQS#4 AW5 SA_DQS#3 RSVD_AW27 M_B_DQS#3 AN29 SB_DQS#2
M_A_DQS#5 AP2 SA_DQS#4 AU9 M_A_CAS# M_B_DQS#4 AN13 SB_DQS#3
M_A_DQS#6 AK2 SA_DQS#5 SA_CAS# M_B_DQS#5 AR8 SB_DQS#4
M_A_DQS#7 AF2 SA_DQS#6 AK22 SM_DRAMRST# M_B_DQS#6 AM8 SB_DQS#5
AU32 SA_DQS#7 SM_DRAMRST# M_B_DQS#7 AG6 SB_DQS#6
SA_DQS#8 AN26 SB_DQS#7
SB_DQS#8
1
(R)
W
C420
SCD1U10V2KX-5GP
2
HASWE1NFU
(62.10055.761) HASWE1NFU
1
(62.10055.761)
24D9R2F-L-GP
R105
24D9R2F-L-GP
R104
2
2
A A
<Core Design>
Wistron Corporation
Title
CPU uLGA (DDR)

C
Madrid SA
5 4 3 2 1
5 4 3 2 1
VCC PCH_1D05V R91 1 2 0R0402-PAD

PCH_1D05V R63 1 (R) 2 0R2J-2-GP
7 VCCST
V_CPU_VCCIO2PCH P_CPU_VCCIO
12,13,20 PWRGD_3V
2
R87 VCC_CORE CPU1F 6 OF 10 VCC_CORE
0R0603-PAD-1-GP-U CPU1H 8 OF 10
HASWELL
R64 P8 C31 HASWELL K12 TP_RSVD_K12 1 TP79 TPAD28-1-GP-U
1
1 2 0R0402-PAD V_CPU_VCCIO_OUT L40 VCC VCC C33 RSVD_TP_K12 J13 TP_RSVD_J13 1 TP61 TPAD28-1-GP-U
VCCST R86 1 (R) 2 0R2J-2-GP VCCIO2PCH AB8 VCCIO_OUT VCC L16 RSVD_TP_J13
VCCIO2PCH VCC L15 P37 TP_RSVD_P37 1 TP69 TPAD28-1-GP-U
VCC J35 TPAD28-1-GP-U TP109 1 TP_RSVD_AY18 AY18 RSVD_TP_P37 N38 TP_RSVD_N38 1 TP75 TPAD28-1-GP-U
VCC RSVD_AY18 RSVD_TP_N38
1
L31 H33 TPAD28-1-GP-U TP106 1 TP_RSVD_AW24 AW24
C40 VCC_CORE VCC VCC TP_RSVD_AW23 RSVD_AW24 TP_RSVD_R36
C43 L18 H35 TPAD28-1-GP-U TP108 1 AW23 R36 1 TP77 TPAD28-1-GP-U
SCD1U16V2ZY-2GP SC4D7U6D3V3KX-GP L17 VCC VCC J21 TPAD28-1-GP-U TP103 1 TP_RSVD_AV29 AV29 RSVD_AW23 RSVD_TP_R36 C39 TP_RSVD_C39 1 TP36 TPAD28-1-GP-U
2
J33 VCC VCC J22 TPAD28-1-GP-U TP101 1 TP_RSVD_AV24 AV24 RSVD_AV29 RSVD_TP_C39
A24 VCC VCC J23 TPAD28-1-GP-U TP100 1 TP_RSVD_AU39 AU39 RSVD_AV24 U35
A25 VCC VCC J24 TPAD28-1-GP-U TP97 1 TP_RSVD_AU27 AU27 RSVD_AU39 VSS P40
D A26 VCC VCC J25 TPAD28-1-GP-U TP99 1 TP_RSVD_AU1 AU1 RSVD_AU27 VSS D
A27 VCC VCC J26 TPAD28-1-GP-U TP96 1 TP_RSVD_AT40 AT40 RSVD_AU1 R38
A28 VCC VCC J27 TPAD28-1-GP-U TP93 1 TP_RSVD_AK20 AK20 RSVD_AT40 VSS T37
A29 VCC VCC J28 VCCST_PWRGD Y7 RSVD_AK20 VSS V34
A30 VCC VCC J29 TPAD28-1-GP-U TP83 1 TP_RSVD_T34 T34 RSVD_Y7 VSS
G33 VCC VCC J30 TPAD28-1-GP-U TP82 1 TP_RSVD_R34 R34 RSVD_T34 R39
B25 VCC VCC J32 TPAD28-1-GP-U TP53 1 TP_RSVD_J40 J40 RSVD_R34 VSS
B27 VCC VCC J34 TPAD28-1-GP-U TP48 1 TP_RSVD_J17 J17 RSVD_J40 T38
B29 VCC VCC K19 TPAD28-1-GP-U TP63 1 TP_RSVD_J15 J15 RSVD_J17 VSS U36
B31 VCC VCC K21 TPAD28-1-GP-U TP67 1 TP_RSVD_H12 H12 RSVD_J15 VSS P39
J31 VCC VCC K23 RSVD_H12 VSS
B33 VCC VCC K25 T36
G31 VCC VCC K27 VSS R37
B35 VCC VCC K29 VSS
C24 VCC VCC K31 J14
C25 VCC VCC M13 VSS N36 TP_CPU_N36 1 TP65 TPAD28-1-GP-U
C26 VCC VCC K33 RSVD_TP_N36
C27 VCC VCC K35
C28 VCC VCC L19
C29 VCC VCC L20 HASWE1NFU
C30 VCC VCC L21
VCC VCC (62.10055.761)
C32 L22
C34 VCC VCC L23
C35 VCC VCC L24
D25 VCC VCC L25
VCCST_PWRGD
D27 VCC VCC L26
M
D29 VCC VCC L27
D31 VCC VCC L28
E33 VCC VCC L29
D33 VCC VCC L30
E31 VCC VCC L32
D35 VCC VCC L33
VCC VCC R578 R583
E24 M17
E25 VCC VCC M15 1 2 1 2 PWRGD_3V
E26 VCC VCC M19
E27 VCC VCC M21
VCC VCC 2K67R2F-2-GP 6K04R2F-GP
O
E28 M23
E29 VCC VCC M25
E30 VCC VCC M27
E32 VCC VCC M29
E34 VCC VCC M33
F23 VCC VCC
F25 VCC AJ12
VCC VDDQ 1D5V_S3
F27 AJ13
F29 VCC VDDQ AJ15
F31 VCC VDDQ AJ17
VCC VDDQ
.C
E35 AJ20
F33 VCC VDDQ AJ21
F35 VCC VDDQ AJ24
G22 VCC VDDQ AJ25
C G23 VCC VDDQ AJ28 C
G24 VCC VDDQ AJ29
G25 VCC VDDQ AJ9
G26 VCC VDDQ AT17
G27 VCC VDDQ AT22
G28 VCC VDDQ AU15
G29 VCC VDDQ AU20
G30 VCC VDDQ AU24
G32 VCC VDDQ AV10
VCC VDDQ
AM
G34 AV11
G35 VCC VDDQ AV13
H23 VCC VDDQ AV18
H25 VCC VDDQ AV23
H27 VCC VDDQ AV8
H29 VCC VDDQ AW16
H31 VCC VDDQ AY12
L34 VCC VDDQ AY14
VCC VDDQ AY9
VDDQ
HASWE1NFU
(62.10055.761)
T
LA
CPU Power Capacitor Quantity
PLACE ALL 0805 CAPS INSIDE CPU SOCKET CAVITY Net CAP AMOUNT
VCC_CORE
VCC_CORE Vcore 22uf 0805 22
V_SM 22uf 0805 4+5(R)
(R) (R)
1
1
C68 C61 C60 C59 C49 C365 C364
1
B C65 C64 C63 C52 SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP B
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
IX
2
2
2
VCC_CORE
(R)
1
1
C45 C51 C47 C367 C67 C66 C50
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
(R) (R)
2
2
1
C700 C701
SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP
DEFENSIVE DESIGN PWR_DEBUG
.F 3D3V_S0
2
1D5V_S3
1
R82
10KR2F-2-GP
1
C182 (R) C103 C183 C105 C79 (R) C78 C484 C483 (R)
SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC22U6D3V5MX-2GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP
2
2
2
W
20131128 Madrid SB Charles
NB team cost review
Q10
PWR_DEBUG 6 1
7 PWR_DEBUG
2
VCORE_PWRGD R78 1 (R) 2 10KR2F-2-GP PWR_DEBUG_N 5
7,13,35,41 VCORE_PWRGD 4 3 PWR_DEBUG_1
R75 1 (R) 2 10KR2F-2-GP MBT3904DW1T1G-2-GP

VCC_CORE
1
PLACE CAPS AT TOP SOCKET EDGE (R)
W
1
(R) (R)
R558 C380
0R2J-2-GP SCD1U16V2ZY-2GP
2
2
P_CPU_VCCIO
VCC_CORE
1
C15
(R) SC4D7U6D3V3KX-GP
2
1
C48 C46 C53 C366

W

A A
2
VCC_CORE
<Core Design>
(R) (R) (R) (R)
1
C362 C361 C360 C363

Wistron Corporation
2

Title
CPU uLGA (VCC)

D
Madrid SA
5 4 3 2 1
5 4 3 2 1
CLOCK P_CPU_VCCIO
SM_DRAMPWROK
14 CK_PE_100M_MCP_DP
14 CK_PE_100M_MCP_DN 2012/04/05 SB BOM Change 681 to 1k8
R39 1 2 75R2F-2-GP 2013/04/09
MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAL PAGE R284 1 2 1K8R2F-GP H_DRAMPWRGD
Rossi delete XDP_MBP 1D5V_S3
1
PLACE IN CRB AREA R47 1 2 110R2F-GP
CPU_VCORE
CPU1E 5 OF 10 R266
H_VIDSCK_VR R52 1 2 0R0402-PAD H_VIDSCK R51 1 (R) 2 90D9R2F-1-GP CK_PE_100M_MCP_DN V4 G39 TP_CPU_G39 1 TP42 TPAD28-1-GP-U 3K3R2J-3-GP
CK_PE_100M_MCP_DP V5 BCLK# HASWELL BPM#0 J39 TP_CPU_J39 1 TP50 TPAD28-1-GP-U
41 VCC_SENSE H_VIDSOUT_VR H_VIDSOUT BCLK BPM#1 TP_CPU_G38
41 VSS_SENSE R48 1 2 0R0402-PAD G38 1 TP41 TPAD28-1-GP-U 2012/04/05 SB BOM Change 1k47 to 3k3
2
H_VIDSCK C38 BPM#2 H37 TP_CPU_H37 1 TP44 TPAD28-1-GP-U
H_VIDALERT_N_VR R38 1 2 0R0402-PAD H_VIDALERT_N H_VIDSOUT C37 VIDSCLK BPM#3 H38 TP_CPU_H38 1 TP45 TPAD28-1-GP-U
41 H_VIDSCK_VR H_VIDALERT_N H_VIDALERT_N_1 VIDSOUT BPM#4 TP_CPU_J38
41 H_VIDSOUT_VR R50 1 2 44D2R2F-GP B37 J38 1 TP52 TPAD28-1-GP-U
R49 1 (R) 2 100R2J-2-GP VIDALERT# BPM#5 K39 TP_CPU_K39 1 TP56 TPAD28-1-GP-U
41 H_VIDALERT_N_VR H_DRAMPWRGD H_DRAMPWRGD_CPU BPM#6 TP_CPU_K37
D R277 1 2 0R0402-PAD AK21 K37 1 TP51 TPAD28-1-GP-U D
H_PWRGD AB35 SM_DRAMPWROK BPM#7 T35 TP_CPU_T35 1 TP78 TPAD28-1-GP-U
PLTRST_CPU_N R70 1 2 0R0402-PAD H_CPURST_N M39 PWRGOOD RSVD_T35 M38 TP_CPU_M38 1 TP62 TPAD28-1-GP-U P_CPU_VCCIO
RESET# RSVD_M38
XDP
1
(R) (R) (R) H_PM_SYNC_0 P36 P6 TESTLOW_1 R563 1 2 49D9R2F-GP
PM_SYNC TESTLO_P6
1
R67 R68 C32 H_PECI N37 K9 VCCST R62 1 2 51R2J-2-GP H_PROCHOT_R_N
16 HSW_STRAP_13 PECI RSVD_K9 TP_RSVD_H15
665R2F-2-GP 43R2J-GP SCD1U16V2ZY-2GP H15 1 TP43 TPAD28-1-GP-U
TP_H_CATERR_N RSVD_H15 TP_RSVD_J9 CPU_THERMTRIP_N
1 M36 THERMAL J9 1 TP49 TPAD28-1-GP-U R553 1 2 1KR2J-1-GP
2
TP57 H_PROCHOT_R_N K38 CATERR# RSVD_J9 H14 TP_RSVD_H14 1 TP71 TPAD28-1-GP-U
2
TPAD28-1-GP-U CPU_THERMTRIP_N F37 PROCHOT# RSVD_H14 M8
H_SKTOCC_N THERMTRIP# VCC_M8 TP_RSVD_AV2 VCC_CORE
D38 AV2 1
SKTOCC# RSVD_AV2 TP_RSVD_J16 H_PWRGD
Defensive Design
J16 1 TP98 TPAD28-1-GP-U R96 1 2 10KR2J-3-GP
+V_SM_VREF_CNT RSVD_TP_J16 TP_RSVD_H16
OTHER
AB38 H16 1 TP47 TPAD28-1-GP-U 2010/12/20 SB
SM_VREF RSVD_TP_H16
2
N40 PWR_DEBUG TP58 TPAD28-1-GP-U C57 2 (R) 1 SCD1U16V2ZY-2GP
PWR_DEBUG Add EMI Cap
P_CPU_VCCIO HSW_PCUDEBUG_0
C467
SCD022U16V2JX-GP
AA37 N39
HSW_PCUDEBUG_1 Y38 CFG0 VSS V7 TP_RSVD_V7 R589 1 2 0R0402-PAD R73 1 2 150R2F-1-GP PWR_DEBUG
PCH_1D05V
1
HSW_PCUDEBUG_2 AA36 CFG1 VSS AB6 TP_RSVD_AB6 R596 1 2 0R0402-PAD
6 VCCST CFG2 VSS
1
HSW_PCUDEBUG_3 W38 K13 TP_RSVD_K13 1 TP70 TPAD28-1-GP-U R74 2 (R) 1 10KR2J-3-GP
6 PWR_DEBUG +V_SM_VREF_CNT_1 HSW_PCUDEBUG_4 CFG3 RSVD_TP_K13 TP_RSVD_J8
R69 V39 J8 1 TP55 TPAD28-1-GP-U
75R2J-1-GP HSW_PCUDEBUG_5 U39 CFG4 RSVD_TP_J8 R1 DDR_RCOMP_0 R72 1 2 100R2F-L1-GP-U
13,41 H_PWRGD HSW_PCUDEBUG_6 CFG5 SM_RCOMP0 DDR_RCOMP_1
11,20,50 PLT_RST# (R) U40 P1 R71 1 2 75R2F-2-GP
HSW_PCUDEBUG_7 V38 CFG6 SM_RCOMP1 R2 DDR_RCOMP_2 R79 1 2 100R2F-L1-GP-U
2
CFG7 SM_RCOMP2
1
HSW_PCUDEBUG_8 T40 AB36 TP_RSVD_AB36 1 TP86 TPAD28-1-GP-U
13 H_SKTOCC_N PLTRST_CPU_N2 HSW_PCUDEBUG_9 CFG8 RSVD_AB36 TP_RSVD_AW2
24D9R2F-L-GP
R622
13 FP_RST_DBR_N
Y35 AW2 1 TP105 TPAD28-1-GP-U
3D3V_S5 HSW_PCUDEBUG_10 AA34 CFG9 RSVD_TP_AW2 AV1 TP_RSVD_AV1 1 TP102 TPAD28-1-GP-U
M
13 H_DRAMPWRGD HSW_PCUDEBUG_11 CFG10 RSVD_TP_AV1 TP_RSVD_AC8
V37 AC8 1 TP88 TPAD28-1-GP-U
VCORE_PWRGD R797 1 (R) 2 150KR2J-GP HSW_PCUDEBUG_12 Y34 CFG11 RSVD_AC8 P4 3D3V_S5
14 CK_DPNS_R_DN V_VCCIOA_LOAD
2
HSW_PCUDEBUG_13 U38 CFG12 VCOMP_OUT U8 TP_RSVD_U8 1 TP81 TPAD28-1-GP-U
14 CK_DPNS_R_DP HSW_PCUDEBUG_14 CFG13 RSVD_U8 TP_RSVD_AB33
6,13,35,41 VCORE_PWRGD Q78 W34 AB33 1 TP87 TPAD28-1-GP-U
HSW_PCUDEBUG_15 CFG14 RSVD_AB33 CPU_VSS_T8 (R)
1 6 V35 T8 R571 1 2 0R2J-2-GP R765 1 2 10KR2J-3-GP H_SKTOCC_PU 1 2 0R2J-2-GP H_SKTOCC_N
PLT_RST# R747 1 (R) 2 1K3R2F-1-GP PLTRST_N_R 2 CFG15 RSVD_T8 Y8 TP_RSVD_Y8 1 TP85 TPAD28-1-GP-U R753
12 H_PM_SYNC_0 RSVD_Y8
5 PLTRST_CPU_N1 R795 2 (R) 1 100KR2J-1-GP HSW_PCUSTB_0_DP Y36 M10 TP_RSVD_M10 1 TP74 TPAD28-1-GP-U
12,54 H_THERMTRIP_N HSW_PCUSTB_0_DN CFG17 RSVD_M10 TP_RSVD_L10
12,20 H_PECI (R) 3 4 Y37 L10 1 TP64 TPAD28-1-GP-U
CFG16 RSVD_L10
O
C569 HSW_PCUSTB_1_DP V36 M11 TP_RSVD_M11 1 TP80 TPAD28-1-GP-U
12 PLTRST_CPU_N 2013/04/09 CFG19 RSVD_M11
SC100P50V2JN-3GP MBT3904DW1T1G-2-GP HSW_PCUSTB_1_DN W36 L12 TP_RSVD_L12 1 TP72 TPAD28-1-GP-U
C Connect to PCH/SIO CFG18 RSVD_L12 TP_RSVD_W8 C
34,41 H_PROCHOT_N (R) 2013/04/09 W8 1 TP84 TPAD28-1-GP-U
2 H_TCK RSVD_W8 TP_RSVD_R33
MCP TERMINATION
D39 R33 1 TP76 TPAD28-1-GP-U 2013/04/09
Rossi reserved JTAG H_TDI F38 TCK RSVD_R33 P33 TP_RSVD_P33 1 TP68 TPAD28-1-GP-U
H_TDO F39 TDI RSVD_P33 E40 VCC_SENSE HSW_PCUDEUG[0-15] P/L reserved
H_TMS E39 TDO VCC_SENSE
TMS
9,10 +V_SM_VREF_CNT JTAG VSS
N33
.C
1 H_TRST_N E37 J11
TPAD28-1-GP-U TP33 1 H_PRDY_N L39 TRST# VSS M9
TPAD28-1-GP-U TP59 1 H_PREQ_N L37 PRDY# VSS J7 HSW_PCUDEBUG_0 R585 1 (R) 2 1KR2J-1-GP
FP_RST_DBR_N TPAD28-1-GP-U TP39 1 R42 2 0R0402-PAD G40 PREQ# VSS F40 VSS_SENSE
XDP_DBRESET_N DBR# VSS_SENSE HSW_PCUDEBUG_1 R576 1 (R) 2 1KR2J-1-GP
R568 2 1 49D9R2F-GP TESTLOW_2 N5 N35 V_1P05_PECI_VCOM 1 TP73 TPAD28-1-GP-U
1 TP_RSVD_K8 K8 TESTLO_N5 RSVD_N35 W6 CK_DPNS_R_DN HSW_PCUDEBUG_2 R582 1 (R) 2 1KR2J-1-GP
TPAD28-1-GP-U TP46 1 TP_RSVD_J10 J10 RSVD_TP_K8 DPLL_REF_CLK# W5 CK_DPNS_R_DP
TPAD28-1-GP-U TP66 RSVD_TP_J10 DPLL_REF_CLK H40 TPEV_CFG_RCOMP
CFG_RCOMP
HSW_PCUDEBUG_3 R570 1 (R) 2 1KR2J-1-GP
AM
1
HASWE1NFU
R60 HSW_PCUDEBUG_4 R562 1 (R) 2 1KR2J-1-GP
(62.10055.761)
49D9R2F-GP
2
Set CFG[6:5] as 1x16
THERMAL HSW_PCUDEBUG_8 R555 1 (R) 2 1KR2J-1-GP

H_PROCHOT_N R61 1 2 0R0402-PAD H_PROCHOT_R_N HSW_PCUDEBUG_10 R594 1 (R) 2 1KR2J-1-GP

2013/04/09
H_THERMTRIP_N CPU_THERMTRIP_N Rossi reserved JTAG P/H, P/L pin HSW_PCUDEBUG_11 R560 1
T
R552 1 2 0R0402-PAD (R) 2 1KR2J-1-GP
B HSW_PCUDEBUG_12 R561 1 (R) 2 1KR2J-1-GP B

P_CPU_VCCIO 3D3V_S0 PLace Near XDP CONN
R551 1 (R) 2 51R2J-2-GP H_TDI
P_CPU_VCCIO
1
1
LA
R36 (R) R54 1 (R) 2 51R2J-2-GP H_TMS
51R2F-2-GP R37 PLace Near CPU
249R2F-GP R53 1 2 51R2J-2-GP H_TCK
2
2
H_TDO H_TCK TERMINATION PLACE
HSW_PCUDEBUG_13 HSW_STRAP_13
NEAR CPU WITHIN 1.1 INCH R557 1 2 1KR2J-1-GP PCH Strap
1
1
(R) (R) R554 1 2 51R2J-2-GP H_TRST_N
R41 R57
825R2F-GP 100R2F-L1-GP-U PLace Any where VCC_SENSE R56 1 (R) 2 49D9R2F-GP VSS_SENSE
2
IX
PLace Near XDP CONN HSW_PCUSTB_0_DP R592 1 (R) 2 1KR2J-1-GP
HSW_PCUSTB_0_DN R584 1 (R) 2 1KR2J-1-GP

HSW_PCUSTB_1_DP R575 1 (R) 2 1KR2J-1-GP
HSW_PCUSTB_1_DN R581 1 (R) 2 1KR2J-1-GP

.F
XDP_DBRESET_N
CLOSE TO CPU
1
C26
SCD1U16V2ZY-2GP
2
A A
W
<Core Design>
Wistron Corporation
Title
W
CPU uLGA (VCORE/XDP)

Custom
Madrid SA
5 4 3 2 1
W
5 4 3 2 1
CPU1I 9 OF 10 CPU1G 7 OF 10 CPU1J 10 OF 10
A5 HASWELL AJ5 HASWELL HASWELL

A7 VSS VSS AJ8 AP11 AW32 G3
A11 VSS VSS AJ34 AP14 VSS VSS AW34 G6 VSS K15
A13 VSS VSS AJ35 AP15 VSS VSS AW36 G7 VSS VSS K16
A15 VSS VSS AJ36 AP24 VSS VSS AW7 G12 VSS VSS K32
A17 VSS VSS AJ37 AP27 VSS VSS AY17 G13 VSS VSS L36
D A23 VSS VSS AJ40 AP30 VSS VSS AY23 G14 VSS VSS M4 D
AA3 VSS VSS AK1 AP36 VSS VSS AY26 G15 VSS VSS M5
AA8 VSS VSS AK6 AR11 VSS VSS AY5 G21 VSS VSS
AA33 VSS VSS AK7 AR14 VSS VSS AY7 G36 VSS M35
AA35 VSS VSS AK8 AR16 VSS VSS B24 G37 VSS VSS M40
AA38 VSS VSS AK9 AR17 VSS VSS B26 H1 VSS VSS N1
AB5 VSS VSS AK10 AR18 VSS VSS B28 H4 VSS VSS N2
AC3 VSS VSS AK14 AR22 VSS VSS B4 H10 VSS VSS N7
AC6 VSS VSS AK18 AR23 VSS VSS B8 H11 VSS VSS N8
AC7 VSS VSS AK19 AR24 VSS VSS C4 H13 VSS VSS
AC33 VSS VSS AK24 AR27 VSS VSS C6 H17 VSS N34
AC34 VSS VSS AK25 AR30 VSS VSS C12 H18 VSS VSS
AC35 VSS VSS AK26 AR31 VSS VSS C14 H20 VSS
AC36 VSS VSS AK27 AR32 VSS VSS C16 H21 VSS P2
AC37 VSS VSS AK28 AR33 VSS VSS C18 H22 VSS VSS P5
AD1 VSS VSS AL5 AR37 VSS VSS C36 H30 VSS VSS P38
AD2 VSS VSS AL11 AR38 VSS VSS B10 H32 VSS VSS R3
AD3 VSS VSS AL14 AR39 VSS VSS B23 H34 VSS VSS R5
M
AD4 VSS VSS AL17 AR40 VSS VSS C3 H36 VSS VSS R6
AD5 VSS VSS AL21 AR5 VSS VSS D9 H39 VSS VSS R7
AD6 VSS VSS AL22 AT1 VSS VSS D11 J3 VSS VSS R8
AD33 VSS VSS AL30 AT12 VSS VSS D17 J19 VSS VSS T1
AD36 VSS VSS AL36 AT13 VSS VSS D2 J20 VSS VSS T2
AE5 VSS VSS AL37 AT14 VSS VSS D23 J36 VSS VSS T4
AE8 VSS VSS AL38 AT15 VSS VSS D24 J37 VSS VSS T5
AE33 VSS VSS AL39 AT16 VSS VSS D26 K1 VSS VSS T6
VSS VSS VSS VSS VSS VSS
O
AE36 AL40 AT2 D28 K4 T7
AE37 VSS VSS AM1 AT24 VSS VSS D30 K7 VSS VSS T33
AE40 VSS VSS AM2 AT25 VSS VSS D34 K10 VSS VSS T39
AF1 VSS VSS AM3 AT26 VSS VSS D36 K14 VSS VSS U2
AF36 VSS VSS AM15 AT30 VSS VSS E7 K24 VSS VSS U37
AG5 VSS VSS AM19 AT32 VSS VSS E8 K26 VSS VSS V3
.C
AG8 AM24 AT34 E10 K28 V6
C AG38 VSS VSS AM32 AT4 VSS VSS E22 K40 VSS VSS W1 C
AG39 VSS VSS AM33 AT5 VSS VSS E23 L3 VSS VSS W4
AG40 VSS VSS AM34 AT6 VSS VSS E36 L6 VSS VSS W7
AH1 VSS VSS AM35 AT7 VSS VSS E38 L7 VSS VSS W33
AH2 VSS VSS AM36 AT8 VSS VSS B32 L8 VSS VSS W35
AH3 VSS VSS AN5 AT9 VSS VSS E6 L9 VSS VSS W37
AH4 VSS VSS AN6 AU2 VSS VSS F1 L11 VSS VSS Y4
AV39,AW38,AY3,B38,B39,C40,D40
AM
AH33 AN9 AU30 F14 L35 Y33
AH36 VSS VSS AN10 AU34 VSS VSS F16 L38 VSS VSS
AJ11 VSS VSS AN11 AU38 VSS VSS F19 M1 VSS
AJ18 VSS VSS AN18 AV21 VSS VSS F24 M16 VSS AU40
NCTF TEST PIN: AU40,

AJ19 VSS VSS AN19 AV28 VSS VSS F26 M18 VSS VSS_NCTF_AU40 AV39
AJ22 VSS VSS AN22 AV3 VSS VSS F28 M20 VSS VSS_NCTF_AV39 AW38
AJ23 VSS VSS AN23 AV30 VSS VSS F30 M22 VSS VSS_NCTF_AW38 AY3
AJ26 VSS VSS AN24 AV34 VSS VSS F34 M24 VSS VSS_NCTF_AY3 B38
AJ27 VSS VSS AN27 AV38 VSS VSS F36 M26 VSS VSS_NCTF_B38 B39
AJ30 VSS VSS AN30 AV7 VSS VSS F4 M28 VSS VSS_NCTF_B39 C40
AJ31 VSS VSS AN36 AW26 VSS VSS D32 M30 VSS VSS_NCTF_C40 D40
AJ32 VSS VSS AN37 AW3 VSS VSS F7 M32 VSS VSS_NCTF_D40
AJ33 VSS VSS AN40 AW30 VSS VSS G9 M34 VSS
VSS VSS AP1 VSS VSS G11 M37 VSS
VSS VSS VSS
HASWE1NFU
T
(62.10055.761) HASWE1NFU
(62.10055.761)
HASWE1NFU
(62.10055.761)
LA
B B
IX
.F
W
W
W
A A
<Core Design>
Wistron Corporation
Title
CPU uLGA (VCC)

D
Madrid SA
5 4 3 2 1
5 4 3 2 1
DIMM1
M_A_A0
M_A_A1
98
97 A0 NP1
NP1
NP2
2013/05/02
M_A_A2
M_A_A3
96
95
A1
A2
NP2
110
Rossi Change DIMM type follow London2
M_A_RAS# 5
M_A_A4
M_A_A5
92
91
A3
A4
RAS#
WE#
113
115
M_A_W E# 5
M_A_CAS# 5
Symbol--> 62.10024.B81
5 M_A_A[15:0] M_A_A6 90 A5 CAS#
M_A_A7 86 A6 114
5 M_A_DQS#[7:0] M_A_A8 A7 CS0# M_A_DIM0_CS#0 5
89 121 Note:
M_A_A9 A8 CS1# M_A_DIM0_CS#1 5
85
5 M_A_DQS[7:0] M_A_A10 107 A9 73 If SA0 DIM0 = 0, SA1_DIM0 = 0
A10/AP CKE0 M_A_DIM0_CKE0 5
M_A_A11 84
A11 CKE1
74
M_A_DIM0_CKE1 5 SO-DIMMA SPD Address is 0xA0
M_A_A12 83
D
M_A_A13
M_A_A14
119 A12
A13 CK0
101
M_A_DIM0_CLK_DDR0 5
SO-DIMMA TS Address is 0x30 Thermal EVENT D
80 103
A14 CK0# M_A_DIM0_CLK_DDR#0 5
M_A_A15 78
A15
If SA0 DIM0 = 1, SA1_DIM0 = 0 3D3V_S0
79 102 SO-DIMMA SPD Address is 0xA2
5 M_A_BS2 A16/BA2 CK1 M_A_DIM0_CLK_DDR1 5 TS#_DIMM0_1
104 1R635 2
CK1# M_A_DIM0_CLK_DDR#1 5 SO-DIMMA TS Address is 0x32
109 10KR2J-3-GP
5 M_A_BS0 108 BA0 11
5 M_A_BS1 BA1 DM0 28
5 M_A_DQ[63:0] M_A_DQ0 5 DM1 46
M_A_DQ1 7 DQ0 DM2 63
M_A_DQ2 15 DQ1 DM3 136
M_A_DQ3 17 DQ2 DM4 153
M
M_A_DQ4 4 DQ3 DM5 170 1D5V_S3
M_A_DQ5 6 DQ4 DM6 187
M_A_DQ6 16 DQ5 DM7
M_A_DQ7 18 DQ6 200
SODIMM A DECOUPLING
M_A_DQ8 21 DQ7 SDA 202 SMB_DATA 10,13,21,22,46,54
M_A_DQ9 23 DQ8 SCL SMB_CLK 10,13,21,22,46,54
O
M_A_DQ10 33 DQ9 198 3D3V_S0 (R)
DQ10 EVENT# TS#_DIMM0_1 10
1
M_A_DQ11
SC10U6D3V3MX-GP
C77
SC10U6D3V3MX-GP
C76
SC10U6D3V3MX-GP
C485
SC10U6D3V3MX-GP
C75
35 20131128 Madrid SB Charles
M_A_DQ12 22 DQ11 199
DQ12 VDDSPD NB team cost review
M_A_DQ13 24
2
M_A_DQ14 34 DQ13 197
DQ14 SA0
.C
M_A_DQ15 36 201
M_A_DQ16 39 DQ15 SA1 C506
M_A_DQ17 DQ16
SCD1U25V2KX-2-GP
41 77
2
M_A_DQ18 DQ17 NC#1
change 20131025
51 122
M_A_DQ19 53 DQ18 NC#2 125 1D5V_S3
M_A_DQ20 40 DQ19 NC#/TEST
M_A_DQ21 42 DQ20 75
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
DQ21 VDD1
AM
M_A_DQ22 50 76 Layout Note:
change 20131216
C DQ22 VDD2 C
1
M_A_DQ23 52 81
C109
C104
M_A_DQ24 57 DQ23 VDD3 82 Place these Caps near
DQ24 VDD4
M_A_DQ25 59 87 SO-DIMMA.
2
M_A_DQ26 67 DQ25 VDD5 88
M_A_DQ27 69 DQ26 VDD6 93
M_A_DQ28 56 DQ27 VDD7 94
M_A_DQ29 58 DQ28 VDD8 99
M_A_DQ30 68 DQ29 VDD9 100
M_A_DQ31 70 DQ30 VDD10 105
M_A_DQ32 129 DQ31 VDD11 106
T
M_A_DQ33 131 DQ32 VDD12 111 1D5V_S3
M_A_DQ34 141 DQ33 VDD13 112
M_A_DQ35 143 DQ34 VDD14 117
M_A_DQ36 130 DQ35 VDD15 118
DQ36 VDD16
1
LA
M_A_DQ37 132 123
M_A_DQ38 140 DQ37 VDD17 124 R151
M_A_DQ39 142 DQ38 VDD18 1KR2F-3-GP
M_A_DQ40 147 DQ39 2
M_A_DQ41 149 DQ40 VSS 3 R148
2
M_A_DQ42 157 DQ41 VSS 8 M_VREF_DQ_DIMM0 1 2
M_A_DQ43 159 DQ42 VSS 9 0R0603-PAD-1-GP-U M_VREF_DQ_DIMM0_C 5
DQ43 VSS
1
M_A_DQ44 146 13
DQ44 VSS
1
M_A_DQ45 148 14 R149
IX
M_A_DQ46 158 DQ45 VSS 19 1KR2F-3-GP
DQ46 VSS
C110 Tracew should be at least 20 mils wide
M_A_DQ47
SCD1U25V2KX-2-GP
160 20
2
M_A_DQ48 DQ47 VSS
change 20131025
163 25
2
M_A_DQ49 165 DQ48 VSS 26
M_A_DQ50 175 DQ49 VSS 31
M_A_DQ51 177 DQ50 VSS 32
M_A_DQ52 164 DQ51 VSS 37
B
M_A_DQ53
M_A_DQ54
166
174
.F
DQ52
DQ53
VSS
VSS
38
43
B
M_A_DQ55 176 DQ54 VSS 44

M_A_DQ56 181 DQ55 VSS 48
M_A_DQ57 183 DQ56 VSS 49
M_A_DQ58 191 DQ57 VSS 54 1D5V_S3
W
0D75V_S0 M_A_DQ59 193 DQ58 VSS 55
Place these caps M_A_DQ60 180 DQ59 VSS 60
close to VTT1 and M_A_DQ61 182 DQ60 VSS 61
DQ61 VSS
1
VTT2. M_A_DQ62 192
DQ62 VSS
65
M_A_DQ63 194 66 R188
DQ63 VSS 71 1KR2F-3-GP
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
M_A_DQS#0 10 VSS 72
W
C513
C507
DQS0# VSS
1
M_A_DQS#1 27 127 R196
2
M_A_DQS#2 45 DQS1# VSS 128 M_VREF_CA_DIMM0 1 2
M_A_DQS#3 62 DQS2# VSS 133 0R0603-PAD-1-GP-U +V_SM_VREF_CNT 7,10
2
DQS3# VSS
1
M_A_DQS#4 135 134
DQS4# VSS
1
M_A_DQS#5 152 138 R185
M_A_DQS#6 169 DQS5# VSS 139 1KR2F-3-GP
DQS6# VSS
W
M_A_DQS#7
SCD1U25V2KX-2-GP
186 144
2
DQS7# VSS
change 20131025
145
2
M_A_DQS0 12 VSS 150
M_A_DQS1 29 DQS0 VSS 151
DQS7 VSS 172
116 VSS 173
5 M_A_DIM0_ODT0 120 ODT0 VSS 178
A A
5 M_A_DIM0_ODT1 ODT1 VSS 179
M_VREF_CA_DIMM0 126 VSS <Core Design>
184
M_VREF_DQ_DIMM0 1 VREF_CA VSS 185
VREF_DQ VSS 189
10,33 DDR3_DRAMRST#
30
RESET#
VSS
VSS
190 Wistron Corporation
195 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
VSS 196 Taipei Hsien 221, Taiwan, R.O.C.
203 VSS 205
0D75V_S0 VTT1 VSS
204 206 Title
VTT2 VSS
DDR3-DIMM1
H =8mm DDR3-204P-101-GP-U Custom
(62.10017.K01) Madrid SA
5 4 3 2 1
5 4 3 2 1
DIMM2
M_B_A0 98 NP1
M_B_A1
M_B_A2
97
96
A0
A1
NP1
NP2
NP2 2013/05/02
M_B_A3
M_B_A4
95
92
A2
A3 RAS#
110
113
M_B_RAS# 5 Rossi Change DIMM type follow London2
M_B_W E# 5
5 M_B_A[15:0]
M_B_A5
M_B_A6
91
90
A4
A5
WE#
CAS#
115
M_B_CAS# 5 Symbol--> 62.10017.W31
M_B_A7 86 A6 114
5 M_B_DQS#[7:0] M_B_A8 A7 CS0# M_B_DIM0_CS#0 5
89 121
M_B_A9 A8 CS1# M_B_DIM0_CS#1 5
85
5 M_B_DQS[7:0] M_B_A10 107 A9 73
M_B_A11 A10/AP CKE0 M_B_DIM0_CKE0 5
84 74 Note:
D
M_B_A12 A11 CKE1 M_B_DIM0_CKE1 5 D
83
M_B_A13 119 A12 101 SO-DIMMB SPD Address is 0xA4
A13 CK0 M_B_DIM0_CLK_DDR0 5
M_B_A14 80
A14 CK0#
103
M_B_DIM0_CLK_DDR#0 5 SO-DIMMB TS Address is 0x34
M_B_A15 78
79 A15 102
5 M_B_BS2 A16/BA2 CK1 M_B_DIM0_CLK_DDR1 5
104
CK1# M_B_DIM0_CLK_DDR#1 5
109 SO-DIMMB is placed farther from
5 M_B_BS0 108 BA0 11
5 M_B_BS1 BA1 DM0 28 the Processor than SO-DIMMA
5 M_B_DQ[63:0] M_B_DQ0 5 DM1 46
M_B_DQ1 7 DQ0 DM2 63
M_B_DQ2 15 DQ1 DM3 136
M
M_B_DQ3 17 DQ2 DM4 153
M_B_DQ4 4 DQ3 DM5 170
M_B_DQ5 6 DQ4 DM6 187
M_B_DQ6 16 DQ5 DM7
M_B_DQ7 18 DQ6 200
M_B_DQ8 21 DQ7 SDA 202 SMB_DATA 9,13,21,22,46,54
O
M_B_DQ9 23 DQ8 SCL SMB_CLK 9,13,21,22,46,54
M_B_DQ10 33 DQ9 198 3D3V_S0
M_B_DQ11 DQ10 EVENT# TS#_DIMM0_1 9
35
M_B_DQ12 22 DQ11 199
M_B_DQ13 24 DQ12 VDDSPD
DQ13
1
.C
M_B_DQ14 34 197
M_B_DQ15 36 DQ14 SA0 201 SA1_DIM1 2 1 C509
M_B_DQ16 DQ15 SA1
SCD1U25V2KX-2-GP
39
2
1D5V_S3 M_B_DQ17 DQ16
change 20131025
SODIMM B DECOUPLING 41 77 R639
M_B_DQ18 51 DQ17 NC#1 122 10KR2J-3-GP
M_B_DQ19 53 DQ18 NC#2 125 1D5V_S3
M_B_DQ20 40 DQ19 NC#/TEST
DQ20
AM
C
M_B_DQ21 42 75 C
C489 M_B_DQ22 50 DQ21 VDD1 76
DQ22 VDD2
1
M_B_DQ23
SC5D6P50V2CN-1GP
SC10U6D3V3MX-GP
C83
SC10U6D3V3MX-GP
C82
SC10U6D3V3MX-GP
C81
52 81
C482
SC56P50V2JN-2GP
M_B_DQ24 57 DQ23 VDD3 82

20131128 Madrid SB Charles DQ24 VDD4
(R) (R) NB team cost review M_B_DQ25 59 87
2
M_B_DQ26 67 DQ25 VDD5 88

M_B_DQ27 69 DQ26 VDD6 93
M_B_DQ28 56 DQ27 VDD7 94
M_B_DQ29 58 DQ28 VDD8 99
M_B_DQ30 68 DQ29 VDD9 100
M_B_DQ31 70 DQ30 VDD10 105 1D5V_S3
T
M_B_DQ32 129 DQ31 VDD11 106
M_B_DQ33 131 DQ32 VDD12 111
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
change 20131216
M_B_DQ34 141 DQ33 VDD13 112

DQ34 VDD14
1
1
M_B_DQ35
C99
143 117
C100
Layout Note: DQ35 VDD15
LA
M_B_DQ36 130 118 R170
Place these Caps near M_B_DQ37 132 DQ36 VDD16 123 1KR2F-3-GP
2
DQ37 VDD17
SO-DIMMB. M_B_DQ38 140
DQ38 VDD18
124
M_B_DQ39 142 R172
2
M_B_DQ40 147 DQ39 2 M_VREF_DQ_DIMM1 1 2
M_B_DQ41 149 DQ40 VSS 3 0R0603-PAD-1-GP-U M_VREF_DQ_DIMM1_C 5
DQ41 VSS
1
M_B_DQ42 157 8
DQ42 VSS
1
M_B_DQ43 159 9 R173
M_B_DQ44 146 DQ43 VSS 13 1KR2F-3-GP C129 Tracew should be at least 20 mils wide
IX
M_B_DQ45 DQ44 VSS
SCD1U25V2KX-2-GP
148 14
2
M_B_DQ46 DQ45 VSS
change 20131025
158 19
2
M_B_DQ47 160 DQ46 VSS 20
M_B_DQ48 163 DQ47 VSS 25
M_B_DQ49 165 DQ48 VSS 26
M_B_DQ50 175 DQ49 VSS 31
M_B_DQ51 177 DQ50 VSS 32
B
.F M_B_DQ52
M_B_DQ53
164
166
DQ51
DQ52
VSS
VSS
37
38
B
M_B_DQ54 174 DQ53 VSS 43

M_B_DQ55 176 DQ54 VSS 44
M_B_DQ56 181 DQ55 VSS 48 1D5V_S3
M_B_DQ57 183 DQ56 VSS 49
W
M_B_DQ58 191 DQ57 VSS 54
M_B_DQ59 193 DQ58 VSS 55
DQ59 VSS
1
M_B_DQ60 180 60
M_B_DQ61 182 DQ60 VSS 61 R190
M_B_DQ62 192 DQ61 VSS 65 1KR2F-3-GP
M_B_DQ63 194 DQ62 VSS 66
DQ63 VSS 71
W
R197
2
M_B_DQS#0 10 VSS 72 M_VREF_CA_DIMM1 1 2
M_B_DQS#1 27 DQS0# VSS 127 0R0603-PAD-1-GP-U +V_SM_VREF_CNT 7,9
DQS1# VSS
1
M_B_DQS#2 45 128
DQS2# VSS
1
M_B_DQS#3 62 133 R192
-2 M_B_DQS#4 135 DQS3# VSS 134 1KR2F-3-GP
DQS4# VSS
M_B_DQS#5
SCD1U25V2KX-2-GP
152 138
2
DQS5# VSS
W
M_B_DQS#6
change 20131025
169 139
2
M_B_DQS#7 186 DQS6# VSS 144
DQS7# VSS 145
Place these caps M_B_DQS0 12 VSS 150
0D75V_S0 close to VTT1 and M_B_DQS1 29 DQS0 VSS 151
DQS1 VSS
VTT2. M_B_DQS2 47
DQS2 VSS
155
M_B_DQS3 64 156
M_B_DQS4 137 DQS3 VSS 161
C501
C108
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
DQS6 VSS
1
M_B_DQS7 188 168

DQS7 VSS 172
116 VSS 173
A A
2
5 M_B_DIM0_ODT0 120 ODT0 VSS 178

5 M_B_DIM0_ODT1 ODT1 VSS <Core Design>
179
M_VREF_CA_DIMM1 126 VSS 184
M_VREF_DQ_DIMM1 1 VREF_CA VSS 185
VREF_DQ VSS
VSS
189 Wistron Corporation
30 190 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
9,33 DDR3_DRAMRST# RESET# VSS 195 Taipei Hsien 221, Taiwan, R.O.C.
VSS 196
203 VSS 205 Title
0D75V_S0 VTT1 VSS
204 206
VTT2 VSS DDR3-DIMM2
DDR3-204P-104-GP Custom
H = 5mm (62.10017.K11) Madrid SA
5 4 3 2 1
5 4 3 2 1
USB3.0 Port Mapping

DMI
4 DMI_MT_IR_DN[0..3]
4 DMI_MT_IR_DP[0..3] 3D3V_S0 USB 2.0 SuperSpeed
4 DMI_IT_MR_DN[0..3] Signals Signals
4 DMI_IT_MR_DP[0..3]
USB30_RN1
2
C503
USB Port USB_PN0 USB30_PN1 3D3V_S0
1 USB_PP0 2013/05/14
USB30_TN1
PCIE SCD1U16V2ZY-2GP Rossi P/H 8.2K follow design guide
1
USB30_TP1
28 HSI_DN3
28 HSI_DP3 USB30_RN2 GPIO2 R1941 2 8K2R2J-3-GP
D 28 HSO_C_DN3 USB Port USB_PN1 USB30_PN2 GPIO3 R1931 2 8K2R2J-3-GP
D
Stitching Capacitor for DMI GPIO4 R1911 2 8K2R2J-3-GP
28 HSO_C_DP3 2 USB_PP1 USB30_TN2 PCH_NMI#_PU R2541 2 8K2R2J-3-GP
USB30_TP2 PCH_GPIO50 R9001 2 8K2R2J-3-GP
PCH_GPIO52 R9011 2 8K2R2J-3-GP
25 PCIE_RXN4 PCH_GPIO54
25 PCIE_RXP4 R9021 2 8K2R2J-3-GP
25 PCIE_TXN4
25 PCIE_TXP4 3D3V_S0
DMI_MT_IR_DN0 L24
PCH1B 2 OF 11
AV10 USB_PN0
13/11/02 Delete USB2 port 0
for USB3S1--Kai USB Table PCH_GPIO5_TP R298 1 2 10KR2J-3-GP
DMI_RXN0 USB2N0 20131125 Madrid SB Charles 20131128 Madrid SB Charles
DMI_MT_IR_DP0 K24 AU10 USB_PP0
46 PCIE_RXN5 20131010 Madrid SA Charles DMI_RXP0 USB2P0 modify GPIO5 pull up to 3D3V_S0, Fix leakage
46 PCIE_RXP5 checked
DMI_IT_MR_DN0 C20
DMI_TXN0 USB2N1
AV11 USB_PN1
Modify the USB2R1 as USB3R1 Pair Device
2
DMI_IT_MR_DP0 USB_PP1
46 PCIE_TXN5
Connect to PCH 16,17 DMI_MT_IR_DN1
B20
DMI_TXP0 USB2P1
AW11
13/11/02 Add P_INTA_N
RN2
46 PCIE_TXP5 C508
DMI_MT_IR_DP1
G24
H24 DMI_RXN1 USB2N2
AN14
AP14 restore USB port 2 0 USB3.0 Ext. port 1 (Side) P_INTC_N
1
2
8
7
SCD1U16V2ZY-2GP
1
DMI_IT_MR_DN1 DMI_RXP1 USB2P2 USB_PN3 P_INTD_N
DMI_IT_MR_DP1
D21
DMI_TXN1 USB2N3
AJ16
USB_PP3 for USB2R1--Kai 1 USB3.0 Ext. port 2 (Side) P_INTB_N
3 6
DMI
B21 AK16 4 5
DMI_MT_IR_DN2 DMI_TXP1 USB2P3 USB_PN4
DMI_MT_IR_DP2
F26
G26 DMI_RXN2 USB2N4
AU15
AV15 USB_PP4
2 Real USB2.0 () 2012/06/25 SC Ryan
DMI_IT_MR_DN2 DMI_RXP2 USB2P4 USB_PN5 SWAP FORCE PWR & TBGPIO6
Stitching Capacitor for USB3.0 B22 AU12 3 Real USB2.0 () SRN8K2J-4-GP
M
DMI_IT_MR_DP2 C22 DMI_TXN2 USB2N5 AT12 USB_PP5
DMI_MT_IR_DN3 DMI_TXP2 USB2P5 3D3V_S5
DMI_MT_IR_DP3
K26
L26 DMI_RXN3 USB2N6
AV14
AW14
4 Real USB2.0 ()
DMI_RXP3 USB2P6 2013/04/15
DMI_IT_MR_DN3
DMI_IT_MR_DP3
A24
B24 DMI_TXN3 USB2N7
AU17
AT17
Rossi Delete not support 5 RF USB2.0 (Dual) 20131027 CM
USB2.0 DMI_TXP3 USB2P7
USB2N8
AW16 USB_PN8 6 X USB_OC_01_N R998 1 2 10KR2J-3-GP
R187 1 2 7K5R2F-1-GP DMIRCOMP B19 AV16 USB_PP8 PCH_GPIO71 R683 1 2 10KR2J-3-GP
26 USB_PN0 DMI_RCOMP USB2P8 USB_PN9 Wake#_LOM_EN
1D5V_S0 R643 1 2 7K5R2F-1-GP DMICOMP C13 AN16 20131010 Madrid 7 X R735 1 2 10KR2J-3-GP
O
26 USB_PP0 PCIE_RCOMP USB2N9 USB_PP9 Wake#_WLAN_EN
AP16 checked R200 1 2 10KR2J-3-GP
100M_DMI_PCH_DN USB2P9 USB_PN10
20131125 Madrid SB Charles R656 2
R657 2
1 10KR2J-3-GP
1 10KR2J-3-GP 100M_DMI_PCH_DP
G22
F22 CLKIN_DMI# USB2N10
AJ18
AK18 USB_PP10
8 CR
USB
CLKIN_DMI_P USB2P10
Modify the USB2R1 as USB3R1 L14 USB2N11
AP18
AN18
USB_PN11
USB_PP11
9 Wireless LAN+BT
PERN1/USB3RN2 USB2P11
K14
B12 PERP1/USB3RP2 USB2N12
AW18
AV18
10 Touch
26 USB_PN1 PETN1/USB3TN2 USB2P12 2013/04/15 2013/04/15
Webcam
.C
B11 AP20 Rossi Delete not support OC# function follow Swift 11
26 USB_PP1 PETP1/USB3TP2 USB2N13
Only USB 3.0 ports 1 and 2 are enabled F14
PERN2/USB3RN3 USB2P13
AN20
2013/04/15 G14 12 X
PERP2/USB3RP3 USB_OC_01_N
C
27 USB_PN3 close to CONN Rossi Delete not support D11
PETN2/USB3TN3 GPIO59
AE40 Rear USB 2.0 C
C11 AF37 USB_OC_23_N Side USB Charger
27 USB_PP3 HSI_DN3 PETP2/USB3TP3 GPIO40 USB_OC_45_N
13 X
F11 AD39
27 USB_PN4 HSI_DP3 PERN3 GPIO41 Wake#_LOM_EN
27 USB_PP4
H11
PERP3 GPIO42
AD40 LAN Wake function
FOR LAN HSO_C_DN3 C134 1 2 SCD1U10V2KX-5GP HSO_DN3 B9 AF39 Wake#_WLAN_EN WLAN Wake function OC[0..3] for Ports 0-7
27 USB_PN5 PETN3 GPIO43
PCI-E
HSO_C_DP3 C133 1 2 SCD1U10V2KX-5GP HSO_DP3 A9 AC41 BT_EN BT En
27 USB_PP5 PCIE_RXN4 PETP3 GPIO9 WLAN_EN
J11 AF40 WLAN En OC[4..7] for Ports 8-13
AM
24 USB_PN8 PCIE_RXP4 PERN4 GPIO10 LPC_PME#
24 USB_PP8
change 20131025 L11
PERP4 GPIO14
AG40 LPC_PME
PCIE_TXN4 C753 1 2 SCD1U10V2KX-5GP PCIE_C_TXN4 B8
46 USB_PN9 PCIE_TXP4 PCIE_C_TXP4 PETN4
FOR AspireLink C754 1 2 SCD1U10V2KX-5GP C8 AV20
46 USB_PP9 PCIE_RXN5 PETP4 USBRBIAS# USBRBIAS_PCH
27 USB_PN10
G9 AU20 R652 2 1 22D6R2F-L1-GP USBRBIAS_PHY (R465): TIE TRACES TOGETHER CLOSE TO PINS,
PCIE_RXP5 F9 PERN5 USBRBIAS
27 USB_PP10 PERP5
WITH LENGTH NO LONGER THAN 1 INCHE TO RESISTOR
PCIE_TXN5 C130 1 2 SCD1U10V2KX-5GP PCIE_C_TXN5 B7 AP11 CK_96M_DREF_DN R642 1 2 10KR2J-3-GP
27 USB_PN11 PCIE_TXP5 PCIE_C_TXP5 PETN5 CLKIN_DOT96# CK_96M_DREF_DP R644 1
FOR WLAN C131 1 2 SCD1U10V2KX-5GP A7 AM11 2 10KR2J-3-GP
27 USB_PP11 PETP5 CLKIN_DOT96_P
PCIE5 For WLAN F7
change 20131025 H7 PERN6
E1 PERP6
D2 PETN6
K6 PETP6
2013/04/08 K8 PERN7
Rossi delete Thunderbolt PCIE signal G3 PERP7
PETN7
T
G5
J2 PETP7
J3 PERN8
H2 PERP8
H1 PETN8
PETP8
LA
13/11/02 Delete USB3 port 1 for USB3S1--Kai 3D3V_S0
USB3.0 LYNX-POINT-2-GP-U 20131125 Madrid SB Charles

26 USB30_RN1 (KI.H8101.002) Modify the USB2R1 as USB3R1 PCH1F 6 OF 11
26 USB30_RP1
26 USB30_TN1 1D5V_S0
PLACE NEAR PCH
26 USB30_TP1
1
USB30_RN0 F20 N1 FDI_TX_DN0 C144
USB30_RP0 USB3RN0 FDI_RXN0 FDI_TX_DP0 C495
G20 N2 SC4D7U10V5ZY-3GP
3D3V_S5 USB30_TN0 USB3RP0 FDI_RXP0 FDI_TX_DN1 SCD1U10V2KX-5GP
26 USB30_RN0 Rear USB3.0 B18 P2
2
USB3TN0 FDI_RXN1
1
B 1 OF 11 USB30_TP0 C18 P3 FDI_TX_DP1 B
PCH1A
IX
26 USB30_RP0 USB3TP0 FDI_RXP1 R636 (R) (R)
26 USB30_TP0 USB30_RN1 FDI_CSYNC
26 USB30_TN0 G18 L2 7K5R2F-1-GP
R723 1 (R) 2 10KR2J-3-GP P_PME# AA31 USB30_RP1 H18 USB3RN1 FDI_CSYNC
CK_PCH_33M_FB PME# PLT_RST# USB30_TN1 USB3RP1 FDI_INT
AM22 AA37 2013/04/08 Side USB3.0 B15 L3
2
CLKIN_33MHZLOOPBACK PLTRST# USB30_TP1 B16 USB3TN1 FDI_INT
20131125 Madrid SB Charles PCH_NMI#_PU
Rossi delete thunderbolt GPIO USB3TP1 FDI_RCOMP
M40 USB3 K2
GPIO35_NMI# FDI_RCOMP
Modify the USB2R1 as USB3R1 TPAD28-1-GP-U
TPAD28-1-GP-U
TP113
TP114
1
1
TP_PCH_A2
TP_PCH_A3
A2
A3 TP16 GPIO50
AH26
AU31
PCH_GPIO50
P_GNT_N1
1 TP131 TPAD28-1-GP-U K20
L20 USB3RN4
TP_PCH_B2 TP17 GPIO51 PCH_GPIO52 P_GNT_N1 16 USB3RP4
TPAD28-1-GP-U TP111 1 B2 AJ26 1 TP132 TPAD28-1-GP-U D15
TPAD28-1-GP-U TP112 1 TP_PCH_B1
TD_IREF
B1
C3
TP18
TP19
TD_IREF
GPIO52
GPIO53
GPIO54
AV31
AW33
R30
.F P_GNT_N2
PCH_GPIO54
P_GNT_N3
1 TP19 TPAD28-1-GP-U
P_GNT_N2 16
2013/04/15
Rossi Delete not support
C15
L18
USB3TN4
USB3TP4 FDILINK
P_GNT_N3 16
1
GPIO55 K18 USB3RN5

R637 P_INTA_N AU29 B14 USB3RP5
8K2R2F-1-GP P_INTB_N AU27 PIRQA# A14 USB3TN5
P_INTC_N AW28 PIRQB# USB3TP5
P_INTD_N AV27 PIRQC#
2
PIRQD# KEY0_TEST
W
GPIO2 AR30 AK28
GPIO3 AV29 GPIO2 TPAD28-1-GP-U TP142 1 PCH_GPIO71 AT34 TACH6/GPIO70
GPIO4 AV28 GPIO3 TACH7/GPIO71
1 PCH_GPIO5_TP AT27 GPIO4
FDI 4 FDI_TX_DN[0..1]
TPAD28-1-GP-U TP130
GPIO5 LYNX-POINT-2-GP-U
(KI.H8101.002)
4 FDI_TX_DP[0..1]
4
4 FDI_INT
FDI_CSYNC Key test
W
3D3V_S0
OTHERS
1
USB_OC_01_N
R669
27 USB_OC_23_N 10KR2J-3-GP
27 USB_OC_45_N
(63.10234.1DL)
46
BT_EN
2
KEY0_TEST
W
46 WLAN_EN
A A
13 Wake#_LOM_EN
Q65
D
13 Wake#_WLAN_EN
2N7002-11-GP
20,21 LPC_PME#
(84.2N702.J31)
14 CK_PCH_33M_FB PANEL_SW G <Core Design>
7,20,50 PLT_RST# PCI
Wistron Corporation
S
LYNX-POINT-2-GP-U
(KI.H8101.002) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
49 PANEL_SW Taipei Hsien 221, Taiwan, R.O.C.
Title
20131010 Madrid SA Charles PCH(FDI/PCIE/DMI/USB)

FOR LPT: GP70 STRAP - USB3 PORT4 Size Document Number Rev
Need check GP71 - USB3 PORT5 Custom
SOFT STRAP TO DETERMINE NATIVE FUNCTION Madrid SA
5 4 3 2 1
5 4 3 2 1
Thermal shuntdown
20 PCH_GPIO6
VGA
2013/04/15
3D3V_S0
Modified SATA defined
Pull-up on MB 2013/04/15
D 20131010 Madrid SA Charles D
Madrid W/O VGA Rossi delete Chassis and MTST ID
PCH1C 3 OF 11
BATT_CTRL_EVENT R740 1 2 10KR2J-3-GP
TPAD28-1-GP-U TP145 1 CLINK_CLK_LAN U36 B28 SATA_RXN0
CLINK_DATA_LAN CL_CLK SATA_RXN0 SATA_RXP0
TPAD28-1-GP-U
TPAD28-1-GP-U
TP143
TP140
1
1 CLINK_RST_LAN_N
U35
U34 CL_DATA SATA_RXP0
A28
F31 SATA_TXN0 HDD1 20131023 Madrid SA Charles PCH_GPIO6 R896 1 2 10KR2J-3-GP
CL_RST# SATA_TXN0 H31 SATA_TXP0
PCH_MEPWROK_R SATA_TXP0 check list modify ; PCH_GPIO7
SATA
AA32 SATA 6G D30 R897 1 2 10KR2J-3-GP
APWROK SATA_RXN1 GPIO 6/7 pull high
CLINK
C30
PWRGD_3V R727 1 2 0R2J-2-GP SATA_RXP1 B34 INT_SERIRQ R258 1 2 10KR2J-3-GP
45 SATA_RXN0 SATA_TXN1 C34
45 SATA_RXP0 SATA_TXP1 H_A20GATE
HDD1 SB Stuff R481 for Realtek LAN (None AMT) R762 1 2 10KR2J-3-GP
45 SATA_TXN0 A31
45 SATA_TXP0 1 TP_PCH_PWM0 AL31 SATA_RXN2 B31 H_RCIN#
TPAD28-1-GP-U TP135 R238 1 2 10KR2J-3-GP
TPAD28-1-GP-U TP136 1 TP_PCH_PWM1 AM31 PWM0 SATA_RXP2 B35
TP_PCH_PWM2 PWM1 SATA_TXN2 13.05/22 EC_SMI#
TPAD28-1-GP-U TP139 1 AP31 D35 Add EC_SMI P/H Core PWR R199 1 2 10KR2J-3-GP
AV30 PWM2 SATA_TXP2 B32
FAN
PWM3 SATA_RXN3 C32
SATA_RXP3 G33
BOARD_ID_2 AP28 SATA_TXN3 F33
45 SATA_RXN4 EC_SMI# AT31 TACH0/GPIO17 SATA_TXP3
45 SATA_RXP4 PCH_GPIO6 AM28 TACH1/GPIO1 A26 SATA_RXN4 PCH_GP38_PU
ODD1 R257 1 2 10KR2J-3-GP
45 SATA_TXN4 PCH_GPIO7 TACH2/GPIO6 SATA_RXN4/PERN1 SATA_RXP4
45 SATA_TXP4 SMBUS_ISP
AV34
AT30 TACH3/GPIO7 SATA_RXP4/PERP1
B26
L28 SATA_TXN4 ODD1
TACH5 AV35 TACH4/GPIO68 SATA_TXN4/PETN1 K28 SATA_TXP4 PCH_GPIO16 R252 1 2 10KR2J-3-GP
TACH5/GP69 SATA_TXP4/PETP1 C27
2013/04/15 SATA_RXN5/PERN2
Rossi delete Front Audio Det B27
SATA_RXP5/PERP2 G28 VGA_DET R283 1 2 10KR2J-3-GP
R680 1 (R) 2 0R2J-2-GP SST_CTL_R AJ31 SATA_TXN5/PETN2 F28
SSTCTL SATA_TXP5/PETP2
M
H35 CK_SATA_PCH_DN R684 1 2 10KR2J-3-GP R282 1 (R) 2 10KR2J-3-GP
BOARD_ID_1 L38 CLKIN_SATA# H36 CK_SATA_PCH_DP R696 1 2 10KR2J-3-GP GPIO49 CAN BE USE AS PCIE/MSATA MUX SELECT IN LPT
PCH_GP38_PU H41 SCLOCK/GPIO22 CLKIN_SATA_P
PCH_GP39_PU R31 SLOAD/GPIO38 J39
PCH_GP48_PU SDATAOUT0/GPIO39 SATALED# SATARBIAS_PCH
GPIO Header
L40 D33 R203 1 2 7K5R2F-1-GP
SDATAOUT1/GPIO48 SATA_RCOMP 1D5V_S0
OTHERS
PCH_1D05V
2013/04/15 13.05/15 SCI Event to SIO for Smart BAT CTRL TIE TRACES TOGETHER CLOSE TO PINS,
M37 BATT_CTRL_EVENT WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
7 H_PM_SYNC_0 Rossi add GPIO Signal SATA0GP/GPIO21 H_THERMTRIP_N
C J40 SATA1GP R233 1 (R) 2 51R2J-2-GP C
7,54 H_THERMTRIP_N SATA1GP/GPIO19 H40
GPIO
SATA2GP
7,20 H_PECI SATA2GP/GPIO36
O
N41 SATA3GP
SATA3GP/GPIO37 M39 PCH_GPIO16
SATA4GP/GPIO16 N40 VGA_DET
6,13,20 PWRGD_3V SATA5GP/GPIO49
13 PCH_GP34_PU
20 H_A20GATE
20 H_RCIN# AP2 EDP_BKLTCTL
20 INT_SERIRQ EDP_BKLTCTL AT2 EDP_BKLTEN
EDP_BKLTEN AP1 EDP_VDDEN
GPIO
.C
7 PLTRST_CPU_N 13.05/20 EDP_VDDEN
change GPIO by BOM change 2013/04/23
20 EC_SMI# Rossi reserved PCH Panel control
3D3V_S0 3D3V_S0 N30 H_A20GATE
RSVD#N30 H_RCIN#
HOST
K36
RCIN# G39 INT_SERIRQ
SERIRQ C40 H_THERMTRIP_N (R)
THRMTRIP#
2
G40 PECI_PCH R261 1 2 0R2J-2-GP H_PECI

21 SMBUS_ISP PECI F40 H_PM_SYNC_0
R288 R763
PM_SYNCH F41 PLTRST_CPU_N
BATT_CTRL_EVENT 10KR2J-3-GP 10KR2J-3-GP PLTRST_PROC#
1
C168
AM
SC47P50V2JN-3GP
1
(R)
2
PCH_GP39_PU PCH_GP48_PU
ID
LYNX-POINT-2-GP-U
1
(KI.H8101.002)
1
R770
13 BOARD_ID_1
1KR2J-1-GP R764
13 BOARD_ID_2
(R) 1KR2J-1-GP
(R)
2
Straps 3D3V_S0
16 SATA1GP
B PCH_GP34_PU B
R741 1 2 10KR2J-3-GP
16 SATA2GP
R739 1 (R) 2 10KR2J-3-GP
16 SATA3GP
T
HDMI_DETECT R139 1 2 10KR2J-3-GP
PCH1E 5 OF 11 R138 1 (R) 2 10KR2J-3-GP
2013/10/22 Madrid TACH5 R206 1 (R) 2 10KR2J-3-GP

HPD_HDMI_CON_R AJ2 AH3
EDP AH5 DDPB_HPD
DDPC_HPD
VGA_HSYNC
VGA_VSYNC
AH2
Charles checked
R204 1 2 47KR2J-2-GP
LA
EDP_HPD_N AJ4
21 EDP_HPD_N DDPD_HPD AC2 VGA_RED
AK6 VGA_RED AE2 VGA_GREEN EDP_HPD_N R164 1 2 4K7R2J-2-GP
21 DPD_AUXN_S AK8 DDPB_AUXN VGA_GREEN AC3 VGA_BLUE
21 DPD_AUXP_S AG7 DDPB_AUXP VGA_BLUE
AG6 DDPC_AUXN AG4
DDPC_AUXP VGA_IRTN
1
DPD_AUXN_S AG11 AL3
21,22,23 EDP_BKLTCTL DPD_AUXP_S AG10 DDPD_AUXN VGA_DDC_DATA AL2 R168 R166 R167
23 EDP_BKLTEN DDPD_AUXP VGA_DDC_CLK AF5 VGA_DACREFSET R638 1 2 649R2F-GP 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP
23 EDP_VDDEN DAC_IREF (R) (R) (R)
AN3 DDPC_CTRL_CLK CLOSE TO PCH : 2013/04/18
2
DDPC_CTRLCLK AM2 DDPC_CTRL_DATA
DDPC_CTRLDATA DDPB_CTRL_CLK
<500 MIL TO PIN BALLS Rossi add EDP AUX PH
AM1
DDPB_CTRLCLK AJ5 DDPB_CTRL_DATA
DDPB_CTRLDATA AN4 DDPD_CTRL_CLK CLOSE TO PCH :<250 MIL TO PIN BALLS
IX
DDPD_CTRLCLK AN2 DDPD_CTRL_DATA 3D3V_S0
44 HPD_HDMI_CON_R DDPD_CTRLDATA scalar
RN10
HPD_HDMI_CON_R DPD_AUXP_S 1 4
EDP_HPD_N
2013/10/17 DPD_AUXN_S
Charles modify 2 3
2013/04/15
LYNX-POINT-2-GP-U Rossi Delete HDMI CTRL_CLK SRN10KJ-11-GP-U
1
(KI.H8101.002) (R)
1
R165 R153 R630 R629
100KR2J-1-GP
100KR2J-1-GP 1K8R2-GP 1K8R2-GP

3D3V_S0
A (R)
.F (R) (R) A
2
2
20131007 Madrid SA Charles R1631 2 2K2R2J-2-GP DDPD_CTRL_CLK
P54 HDMIOUT 2012/10/4 David
DDPD_CTRL_DATA <Core Design>
Follow design guide(Dallas) R1611 2 2K2R2J-2-GP 2012/11/09 David
44 DDPB_CTRL_DATA vendor suggest(Dallas)
44 DDPB_CTRL_CLK DDPB_CTRL_CLK
R1621 2 2K2R2J-2-GP
DDPB_CTRL_DATA
Wistron Corporation
R6401 2 2K2R2J-2-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
W
R1591 2 2K2R2J-2-GP DDPC_CTRL_CLK
Title
R1521 (R) 2 2K2R2J-2-GP DDPC_CTRL_DATA
PCH(SATA/FAN/DP/VGA)
(R) 13.06/27 Rossi add for 1L Size Document Number Rev
Custom
Madrid SA
5 4 3 2 1
W
W
5 4 3 2 1
LPC 20,50 LPC_AD0

20,50 LPC_AD1
20,50 LPC_AD2
20,50 LPC_AD3
20,50 LPC_FRAME#
20131002 Madrid check done
HD LINK
18 HDA_CODEC_BITCLK
HDA & GPIO & SPI RTC_AUX_S5
PCH1D 4 OF 11
18,19 HDA_CODEC_RST# RTC_AUX_S5
18 HDA_SDIN0 TPAD28-1-GP-U TP133 1 LPC_DRQ1_N AK26 G38 PCH_GPIO0_TP 1 TP21 TPAD28-1-GP-U
18 HDA_CODEC_SDOUT LPC_AD0 R654 1 2 33R2J-2-GP L_AD0_R AN24 LDRQ1#/GPIO23 BMBUSY#/GPIO0 N32 PCH_GPIO32
18 HDA_CODEC_SYNC LPC_AD1 L_AD1_R LAD0 CLKRUN#/GPIO32 SOP_ENABLE_GP33 PCH_INTRUDER_N
R663 1 2 33R2J-2-GP AP26 AV26 R225 1 2 1MR2J-1-GP
LPC_AD2 1 2 33R2J-2-GP L_AD2_R AJ24 LAD1 DOCKEN#/GPIO33 N34 PCH_GP34_PU 13.07/04 add for auto-testing
R653
LAD2 STPPCI#/GPIO34 20131023 Madrid SA Charles
LPC_AD3 R670 1 2 33R2J-2-GP L_AD3_R AN26
LPC_DRQ0_N LAD3 IGC_EN_N check List
TPAD28-1-GP-U TP123 1 AK22 AC40
SMBUS LPC_FRAME# R658 1 2 33R2J-2-GP L_FRAME_N_R AP24 LDRQ0#
LFRAME#
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
AL40 TP_GPIO12 1 TP26 TPAD28-1-GP-U 0R2J-2-GP
Reserve PCH SPI WP#
AN22 SPI_WP_R_N_PCH 1 2(R) R646 SPI_WP_R_N
HDA_CODEC_BITCLK R182 1 HDA_BITCLK HDA_DOCK_RST#/GPIO13 TLS_EN
LAN HDA_CODEC_RST#
2 33R2J-2-GP
HDA_RST#
AV23
HDA_CLK GPIO15
AC32
H_SKTOCC_R_N H_SKTOCC_N
3D3_A
D R183 1 2 33R2J-2-GP AU24 AE34 R746 1 2 0R2J-2-GP D
HDA_SDIN0 AT26 HDA_RST# GPIO24 V41
9,10,21,22,46,54 SMB_CLK madrid for madrid 20131002 Charles HDA_SDI0 GPIO28 13.05/12 Charger change to GPIO28
TPAD28-1-GP-U TP15 1 TP_PCH_AP18 AV22 AL39 SLP_WLAN_N 3D3V_S5
9,10,21,22,46,54 SMB_DATA AudioCodec TP_PCH_AV13 HDA_SDI1 SLP_WLAN#/GPIO29 PCH_GP73_PD
OTHERS TPAD28-1-GP-U TP16
TPAD28-1-GP-U TP14
1
1 TP_PCH_AN16
AT22
AW23 HDA_SDI2 PCIECLKRQ0#/GPIO73
W34
P39 PCH_XDP_GP18
HDA_CODEC_SDOUT R180 1 2 33R2J-2-GP HDA_SDOUT AU22 HDA_SDI3 PCIECLKRQ1#/GPIO18 P37 LANCLK_REQ_N
20 SML1_CLK HDA_SYNC_R HDA_SYNC HDA_SDO PCIECLKRQ2#/GPIO20/SMI# PCH_GP25_PD
SIO 20 SML1_DATA
R184 1 2 33R2J-2-GP AV24
HDA_SYNC PCIECLKRQ3#/GPIO25
AA39
W35 CLK_PCIE_WLAN_REQ#
SPI_SI_R SPI_MOSI PCIECLKRQ4#/GPIO26 USB_PWR_CRL1
20131023 Madrid SA Charles 1 R330 2 P40
SPI_MOSI_IO0 PCIECLKRQ5#/GPIO44
AA36
15R2J-GP SPI_MISO R36 W32 PCH_GPIO45
check list modify ; cancel 1.05VTT_PWRGD SPI_CS0#_R SPI_MISO_IO1 PCIECLKRQ6#/GPIO45 EDID_RDY PCH_AUD_MUTE
R38 AA40 R695 1 2 10KR2J-3-GP
SPI_CLK_R 1 R335 2 SPI_CLK U39 SPI_CS0# PCIECLKRQ7#/GPIO46
15R2J-GP R35 SPI_CLK AC36 ME_CNTL
R40 SPI_CS1# GPIO57 W31 PCH_SYSPWROK
madrid 20131002 Charles SPI_CS2# SYS_PWROK
SPI_WPI U40 AE36 PCH_RI
check how exactly to support Quad solution SPI_HOLD SPI_IO2 RI# PCIE_WAKE#
U37 AK34
SPI_IO3 WAKE# AN37 PCH_GPIO_11 R898 1 2 10KR2J-3-GP
SLP_A# AU36 SLP_LAN_N_C 1 TP20 TPAD28-1-GP-U
R221 1 2 20KR2F-L-GP SRTC_RST# SLP_LAN# AC35
SPI 29
29
SPI_HOLD
SPI_WPI
RTC_AUX_S5 SLP_S0#
SLP_S3#
AK40 PM_SLP_S3# SPI_WP_R_N_PCH R899 1 2 10KR2J-3-GP
AT35 PM_SLP_S4#
29 SPI_SI_R PCH_RTCX1 AN40 SLP_S4# AA35 SLP_S5_N 1
29 SPI_MISO X9502 RTCX1 SLP_S5#/GPIO63
TP144 TPAD28-1-GP-U SIO_SUSACK is for SIO DSW
1
C151 PCH_RTCX2 AN39 AD37 20131105 Madrid SA Charles
29 SPI_CS0#_R SC1U6D3V2KX-GP RTC_RST# RTCX2 SUS_STAT#/GPIO61
RTCrst AR38 W36 SUSCLK cancel GPIO61 for Layout Ball out
M
29 SPI_CLK_R SRTC_RST# RTCRST# SUSCLK/GPIO62 USB_WAKE_SLP
3D3V_S5
AR39 AJ40
2
PCH_INTRUDER_N AR41 SRTCRST# GPIO72 AJ37 SUSACK_N
INTRUDER# SUSACK# SB need Add TP
PWRGD_3V AT40 AG41 SUS_WARNB 1 TP27 TPAD28-1-GP-U
20,29 SPI_WP_R_N 2013/04/29 PCH_PWROK SUSWARN#/PWRDNACK/GPIO30
PM_RSMRST# AM40 AE38 H_DRAMPWRGD USB_PWR_CRL1 R725 1 2 10KR2J-3-GP
Rossi keep swift RSMRST solution PCH_INTVRMEN RSMRST# DRAMPWRGD Wake#_WLAN_PCH
AV36 AU34
PM_RSMRST# R226 1 2 0R0402-PAD PCH_SIO_DPWROK_1 AV38 INTVRMEN GPIO27 AM36 PCH_AUD_MUTE R724 1 2 10KR2J-3-GP
PM_RSMRST# used for SIO DSW DPWROK ACPRESENT/GPIO31
(R)
DSWVRMEN AM41 AK38 SLP_SUSB 1 TP24 TPAD28-1-GP-U
RTC 29 RTC_RST#
2013/05/08
DSWODVREN SLP_SUS#
PWRBTN#
AK41 PM_PWRBTN#
Panel on/off use SCI enent PCH_GPIO_11 FP_RST_PCH_N PCH_RI
AG31 N36 R729 1 2 10KR2J-3-GP
SMB_CLK_RESUME SMBALERT#/GPIO11 SYS_RESET# HDA_SPKR
O
AG36 R32
SMB_DATA_RESUME AG32 SMBCLK SPKR PCH_GPIO45 R751 1 2 10KR2J-3-GP
DRAMRST_CNTRL_PCH AG35 SMBDATA D40 H_PWRGD
SMLINK0_CLK SMI0ALERT#/GPIO60 PROCPWRGD
C556
C557
AE32 R750 1 (R) 2 1KR2J-1-GP
SML0CLK
1
(R) (R) SMLINK0_DATA AE35
SML1ALERT_PCH SML0DATA CLK_PCIE_WLAN_REQ# R769 1
LAN-reserved
AJ39 2 10KR2J-3-GP
SMI1ALERT#/PCHHOT#/GPIO74
1
(R) (R) SML1_CLK AK36
PWR MANAGER
2
C553 C552 SML1_DATA AK33 SML1CLK/GPIO58/MGPIO11 R285 1 (R) 2 100R2J-2-GP
SML1DATA/GPIO75/MGPIO12
SC100P50V2JN-3GP
SC100P50V2JN-3GP
2
2
PCH_JTAG_RST
SC1U10V2ZY-N1-GP
SC1U10V2ZY-N1-GP
IOEC
JTAG(SUS)
2013/04/10 W37 R243 2 (R) 1 10KR2J-3-GP
7 FP_RST_DBR_N TP13
1
PCH_JTAG_TCK
.C
(R) (R) Rossi add DIMM RST CTRL Y40 1 TP23 TPAD28-1-GP-U
7,41 H_PWRGD JTAG_TCK PCH_JTAG_TDI
C564 C563 W39 1 TP25 TPAD28-1-GP-U
7 H_DRAMPWRGD JTAG_TDI PCH_JTAG_TDO
SC100P50V2JN-3GP
SC100P50V2JN-3GP
Y38 1 TP22 TPAD28-1-GP-U
2
JTAG_TDO W40 PCH_JTAG_TMS 1 TP28 TPAD28-1-GP-U SML1ALERT_PCH R245 1 2 10KR2J-3-GP
6,7,35,41 VCORE_PWRGD JTAG_TMS
LYNX-POINT-2-GP-U DRAMRST_CNTRL_PCH R734 1 2 2K2R2J-2-GP
20 PM_PWRBTN#
(KI.H8101.002) 2013/04/10
Rossi add DIMM RST CTRL
6,12,20 PWRGD_3V ME_CNTL R748 1 2 10KR2J-3-GP
C TLS_EN C
R730 2 14K7R2J-2-GP
20,21,25,35,36,38,40,41 PM_SLP_S3#
20,31,38 PM_SLP_S4#
AM
SML1_CLK
SIO SML1_DATA
4
3
1 RN7
2 SRN2K2J-1-GP
20
35
RSMRST#_SIO
SYS_PWROK
Fast Boot 3D3V_S5
Defensive Design 3D3V_S0 ME ENABLE/DISABLE Flash Descriptor Security Overide 3D3V_S5
Low = Default 2013/05/03
2
20,35 PWROK3_1_R HDA_SDOUT High = Debug mode 499 ohm vendor Suggest
1
1
DEFENSIVE DESIGN R177 SMLINK0_CLK R733 1 2 499R2F-2-GP
1
R45 C14 SMLINK0_DATA

(R)
22KR2J-GP SCD1U16V2KX-3GP
R296
10KR2J-3-GP MECLR1
1KR2J-1-GP LAN LANCLK_REQ_N
R731 1
R300 1
2 499R2F-2-GP
2 10KR2J-3-GP
2ME_CNTL2
1
(R) (R)
need resume GPIO
2
U4
1
2
2
1 5 HDA_SDOUT 1 R176 2 HDA_SDOUT_R 2
GPIO/MISC 13.06/10 Reserved avoid VR_READY LOW FB_A 2 NC#1
A
VCC SYS_PWROK R297 1 2 0R0402-PAD PCH_SYSPWROK
3D3V_S5
3
R174
FB_Y PCH_SYSPWROK
3/5V CTRL
3 4 1 (R) 2 1KR2J-1-GP
C
Q6 GND Y ME_CNTL 2 ME_CNTL1 PMBS3906-GP

(R) R27 100R2J-2-GP PIN-CON3-S-GP 1 1
7 H_SKTOCC_N VCORE_PWRGD 1 2Q51_B B SB Ryan add for debug Q19 SUSACK_N 1 4 RN13
R46 MMBT3904-4-GP
1
(R84.03904.L06)74LVC1G14GW -GP 1 (R) 2 PWRGD_3V C176 (84.T3906.E11) SUS_WARNB 2 3 SRN10KJ-11-GP-U
0R2J-2-GP
3
1KR2J-1-GP
1
T
C16 R28 249R2F-GP (R) SCD1U50V5KX-1GP
1
12 BOARD_ID_2
E
(R) (R) EV FOR FUTURE ENGINEERING HDA_SDOUT

R43
2
DEBUG ONLY HDA_SDOUT 2 1 R179
SC1U6D3V2KX-GP
1KR2J-1-GP (R)
12 BOARD_ID_1 10KR2J-3-GP
2
(R)
12 PCH_GP34_PU EDID_RDY R771 1 2 10KR2J-3-GP
2
16,18 HDA_SPKR
13.05/12 USB Wake to GPIO72 USB_WAKE_SLP R244 1 2 10KR2J-3-GP
LA
16 IGC_EN_N 13.07/09 wake change to EUP power, not support S5 state
16 DSWVRMEN
33
16 PCH_INTVRMEN
DRAMRST_CNTRL_PCH
3D3V_S0 RSMRST SEQUENCE PWROK SLP_WLAN_N
13.08/09 change P/H to 3D3V_S5, leakage
R248 1 2 10KR2J-3-GP
RN5
USB_WAKE_SLP
PCH_PWROK SRN2K2J-1-GP
SMB_DATA_RESUME 1 4
2
(R) SMB_CLK_RESUME
U3 2 3
R21 PM_RSMRST# R224 1 2 0R0402-PAD RSMRST#_SIO VCORE_PWRGD (R) PWRGD_3V
(R) 1KR2J-1-GP
1 6 FB_CT SIO VCORE 0R2J-2-GP
2 1
R709 PCH
1
C9 2 ENABLE CDELAY 5
FB_SENCE GND VCC FB_SEOUT (R) 2 PCH_SYSPWROK
3D3V_S0
3 4 1
SCD1U16V2KX-3GP
2 1
IN OUT R23 0R2J-2-GP

2
(R) (R) (R) 3D3V_S0
IX
1
1 2 PWRGD_3V
R20 MAX6895AAZT-T-GP
C11 R24 0R2J-2-GP PCH_SYSPWROK 13.05/14 Resreved P/H due to PCH internal P/H
(R)
1KR2J-1-GP
SC3300P50V2KX-1GP
3/5V CTRL (R)
2
PCH_SYSPWROK 1 (R) PWROK3_1_R LPC_FRAME#

PCH 2
SIO R659 1 2 10KR2J-3-GP
1
R295 0R2J-2-GP
LPC_DRQ0_N R648 1 (R) 2 10KR2J-3-GP
28 LANCLK_REQ_N
R220
LPC_DRQ1_N
2012/06/14 SC Ryan add for Intel MOW PM_RSMRST#
100KR2J-1-GP R674 1 (R) 2 10KR2J-3-GP
1 2
B FP_RST_PCH_N R761 1 2 2K2R2J-2-GP B
46 CLK_PCIE_WLAN_REQ#
(R)
LPC_AD0 R655 1 (R) 2 10KR2J-3-GP
.F LPC_AD1
LPC_AD2
R664 1
R651 1
(R)
(R)
2 10KR2J-3-GP
2 10KR2J-3-GP
21 EDID_RDY LPC_AD3 R671 1 (R) 2 10KR2J-3-GP
PCH_RTCX2
BUZZER PCH_GPIO32 R742 1 2 10KR2J-3-GP
XTAL
X3
1 4 PCH_RTCX1 3D3V_S0 3D3V_S0

W
TPM 2013/05/06 Board ID Mission Sawgrass
R186 1 (R) 2 1KR2J-1-GP SOP_ENABLE_GP33 PCH_GPIO0_TP R299 1 2 10KR2J-3-GP
Rossi Down size 3D3V_S0
1
2 3 20131128 Madrid SB Charles
2
BOARD_ID_0 0 0 R675 R279

20131022 Madrid Charles modify GPIO0 pull up to 3D3V_S0, Fix leakage
Madrid W/O TPM R189 BOARD_ID_1 0 10KR2J-3-GP 10KR2J-3-GP
0
XTAL-32D768KHZ-65-GP 0R0402-PAD
(82.30001.661) 20131010 Madrid Charles
2
BOARD_ID_2
cancel BUZ
1
R235 BOARD_ID_1
1 2
WAKE 10MR3J-L1-GP FP_RST_PCH_N R760 1 20R0402-PAD FP_RST_DBR_N
W
1
28 PCIE_WAKE_N_LOM 20140114 Madrid 1A Charles
1
46 PCIE_WAKE_N_WLAN change to 5P 0603 R681 R278

1
11 Wake#_LOM_EN
C163 RESERVE R542 FOR CRB 10KR2J-3-GP 10KR2J-3-GP
SC5P50V3CN C166 STUFF R542 FOR HSW(DEFAULT) (R) (R)
11 Wake#_WLAN_EN
2
SC5P50V3CN
2
2
SUSCLK R707 1 (R) 2 1K5R2J-3-GP
PCH_XDP_GP18 R247 1 2 10KR2J-3-GP
PCH_GP25_PD
SPI
R242 1 2 10KR2J-3-GP
3D3V_S5
HDA SYNC
2013/04/11
W
PCH_GP73_PD
WAKE SELECT
Michael 2011/01/16 Rossi add swift solution R736 1 2 10KR2J-3-GP
SMBUS
1
3D3V_S0
For EMI R699 1
R693
2
RN6
SRN2K2J-1-GP
HDA_CODEC_BITCLK 5V_S0 3D3V_S5 1 4
10KR2J-3-GP 0R2J-2-GP
2 3
G
2
1
(R) C135 D HDA_SYNC_R PCIE_WAKE_N_LOM S D

OTHERS
2
SC10P50V2JN-4GP
2
HDA_CODEC_SYNC S PLL ODVR VOLTAGE PCIEX1 Q67

R694
10KR2J-3-GP
Q20 Low = 1.8V (Default) 2N7002A-7-GP
G
2N7002K-2-GP HDA_SYNC (R84.2N702.J31) (R) SMB_DATA_RESUME 6 1 SMB_DATA

High = 1.5V
1
(84.2N702.J31) Wake#_LOM_EN
3D3V_S5 5 2
Q77
A Wake#_WLAN_EN PCIE_WAKE# A
(R) R305 PCH 2N7002KDW -GP

84.2N702.A3F
4 3
SPI_WP_R_N 1 2 Q66
HDA_SYNC: This strap is sampled on rising edge of RSMRST# and is used 2nd = 84.DM601.03F
2N7002A-7-GP
to
G
HDA_CODEC_BITCLK HDA_CODEC_SDOUT 10KR2J-3-GP (R84.2N702.J31) (75.27002.F7C) SMB_CLK

sample 1.5V VccVRM supply mode. 1K external pull-up resistor is required
2
SMB_CLK_RESUME
(R) EC3 (R) EC4
on this PCIE_WAKE_N_WLAN S D
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP unmount for nuSync power with R905 signal on the board. Signal may have leakage paths via powered off devices
1
for SPI_WP_R_N pull high (Audio

Codec) and hence contend with the external pull-up. A blocking FET is WLAN R682
10KR2J-3-GP R692
recommended in such a case to isolate HDA_SYNC from the Audio Codec 1 2
<Core Design>
device (R) 0R2J-2-GP
1
until after the Strap sampling is complete. R689

3D3V_S5 1 2 Wake#_WLAN_PCH Wistron Corporation
0R2J-2-GP 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Title
PCH(Audio/GPIO/SPI)
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
PCI CLOCK
50 CLK_PCI_LPC
11 CK_PCH_33M_FB
20 CLK_PCI_SIO
D D
PCIE CLOCK
7 CK_DPNS_R_DN
7 CK_DPNS_R_DP
7 CK_PE_100M_MCP_DN
7 CK_PE_100M_MCP_DP
4 CK_DP_DN
4 CK_DP_DP
M
25 CLK_PCIE_4_AspireLink#
25 CLK_PCIE_4_AspireLink
28 CK_PCIE_3_GLAN_DN 7 OF 11
PCH1G
28 CK_PCIE_3_GLAN_DP
O
G16 CK_CSI_PCH_IN_DN R649 1 2 10KR2J-3-GP
46 CLK_PCIE_WLAN CLKIN_GND0# F16 CK_CSI_PCH_IN_DP R647 1 2 10KR2J-3-GP
46 CLK_PCIE_WLAN# Empty when measure the PCI clock CLKIN_GND0_P
R2 CK_PE_100M_MCP_DN
CLK_PCI_LPC CK_33M_PCI0 CLKOUT_DMI# CK_PE_100M_MCP_DP
To LPC/TPM R160 1 2 22R2J-2-GP AV5
CLKOUT_33MHZ0 CLKOUT_DMI_P
T2 CLK OUT TO CPU for DMI
CK_DP_DN
.C
AV7 T3
48M CLOCK CLKOUT_33MHZ1 CLKOUT_DP#
CLKOUT_DP_P
T5 CK_DP_DP CLK OUT TO CPU
CK_PCH_33M_FB CK_33M_PCI2
20 CLK_48M_SIO LOOPBACK CLK R158 1 2 22R2J-2-GP AU2
CLKOUT_33MHZ2 W2 CK_DPNS_R_DN
CLK_PCI_SIO CK_33M_PCI3 CLKOUT_DPNS# CK_DPNS_R_DP
To SIO R156 1 2 22R2J-2-GP AN9
CLKOUT_33MHZ3 CLKOUT_DPNS_P
U2 CLK OUT TO CPU
AU5 U6 2013/04/15
CLKOUT_33MHZ4 CLKOUT_ITPXDP# U7
CLKOUT_ITPXDP_P Rossi delete XDP CLK
AM
C AA3 C
AV8 CLKOUT_PEG_A# AA2 CLK_PCIE_VGA# 51
CLK_48M_SIO CLKOUTFLEX0/GPIO64 CLKOUT_PEG_A_P CLK_PCIE_VGA 51
To SIO R634 1 2 22R2J-2-GP CLKOUTFLEX1 AT9
AV9 CLKOUTFLEX1/GPIO65 AE6
AU8 CLKOUTFLEX2/GPIO66 CLKOUT_PEG_B# AE7
CLKOUTFLEX3/GPIO67 CLKOUT_PEG_B_P
AE10
R641 1 2 7K5R2F-1-GP XCLK_RCOMP R11 CLKOUT_PCIE_N0 AE11
2013/04/08
1D5V_S0 DIFFCLK_BIASREF CLKOUT_PCIE_P0 Rossi delete Thunderbolt PCIE CLK
Rossi add for EMI R157 2 1 10KR2J-3-GP CK_14M_PCH AR7 AC6
REFCLK14IN CLKOUT_PCIE_N1 AC7
CLKOUT_PCIE_P1
CLK_48M_SIO AC11
T
CLKOUT_PCIE_N2 AC10
CLKOUT_PCIE_P2
1
(R) C490 W11 CK_PCIE_3_GLAN_DN 13.05/22 Change PCIE LAN to Port3

SC10P50V2JN-4GP CLKOUT_PCIE_N3 W10 CK_PCIE_3_GLAN_DP
CLK OUT TO PCIEX1 for LAN
2
CLKOUT_PCIE_P3
NOTE:The 1Mohm Damping Resistor
LA
Use 0603 and Can't change to 0402! Y4 CLK_PCIE_4_AspireLink#
CLKOUT_PCIE_N4 Y2 CLK_PCIE_4_AspireLink 13.11/01 add PCIE port 4 for AspireLink--Kai
CLKOUT_PCIE_P4 CLK OUT TO AspireLink
W7 CLK_PCIE_WLAN#
CLKOUT_PCIE_N5 W6 CLK_PCIE_WLAN
CLKOUT_PCIE_P5 CLK OUT TO MINIPCIEX1
AA7
CLKOUT_PCIE_N6 AA6
XTAL_25M_PCH_IN N7 CLKOUT_PCIE_P6
XTAL25_IN R6
CLKOUT_PCIE_N7
IX
R169 1 2 1MR3F-GP XTAL_25M_PCH_OUT N6 R7
XTAL25_OUT CLKOUT_PCIE_P7
X2
3 2
LYNX-POINT-2-GP-U
(KI.H8101.002)
2013/05/06 4 1
B
Rossi Down size
.F PCH_1D05V
B
XTAL-25MHZ-181-GP
XTAL_IN should be pulled to
1
GND via a 0-Ω resistor by

C127 C123 default.
Intel reliability concerns
1
SCD1U16V2ZY-2GP
SC15P50V2JN-2-GP SC15P50V2JN-2-GP C118
W
2

Vender update changeto 78.15034.1FL
2
When support FCIM need to stuff.
WHEN USING 25MHZ EXTERNAL REFERENCE FROM SINAI CMV:
W
REMOVE R383, X2, C322

Stitching Capacitors
REPLACE C321 WITH 50OHM RES 0402 PACKAGE for CK_PCIE_5
W
A A
<Core Design>
Wistron Corporation
Title
PCH Clock
C
Madrid SA
5 4 3 2 1
5 4 3 2 1
3D3V_S0
V_1P5_DAC_FB C497 1 2 SC1U6D3V2KX-GP
C492 1 2 SC1U6D3V2KX-GP
1D5V_S0 V_1P5_DAC_FB C499 1 2 SC1U6D3V2KX-GP
L3
D V_1P5_DAC_FB_N D
1 2 R1541 2 0R0402-PAD
3D3V_S0
FCM1608KFG-301T05-GP
1
(63.00000.00L) C126 C124 (R)
PCH CORE POWER DECOUPLING SC2D2U6D3V2MX-GP SC1U6D3V2KX-GP C505 1 2 SCD1U16V2ZY-2GP
V_1P05-FILTER CAPS: PLACE NEAR
2
ENDS OF POWER CORRIDOR (R) (R)
PCH_1D05V DEFENSIVE DESIGN FOR
VCCASEFLEX0_3P3 POWER
PCH_1D05V 13.07/09 Rossi add 2.2U for Noise
C98 1 2 SC10U10V5KX-2GP
3D3V_S0
C488 1 2 SC10U10V5KX-2GP
PCH1H 8 OF 11 C504 1 2 SCD1U16V2ZY-2GP
M
PCH_1D05V AA19 A19 1D5V_S0 C496 1 2 SCD1U16V2ZY-2GP
VCC_1 DMI_IREF
1
AA20 N11
C114 1 2 SC1U6D3V2KX-GP AB16 VCC_2 FDI_IREF N10 C500 (R)
AB17 VCC_3 CLK_IREF B13 SCD1U16V2ZY-2GP C493 1 2 SC1U6D3V2KX-GP
2
AB19 VCC_4 PCIE_IREF A33
O
C525 1 2 SCD1U16V2ZY-2GP AB20 VCC_5 SATA_IREF
AD16 VCC_6 B37 C494 1 2 SC1U6D3V2KX-GP
VCC_7 VCCVRM_1 1D5V_S0
V17 A38
C120 1 2 SCD1U16V2ZY-2GP V19 VCC_8 VCCVRM_2 K1
V20 B39
V22 A39
VCC_11 VCCVRM_5
.C
C526 1 2 SCD1U16V2ZY-2GP V23 A40
V25 VCC_12 VCCVRM_6 T14
VCC_13 VCCVRM 1D5V_S0
1
W17 C2
VCC_14 VCCVRM 1D5V_S0
W19 C1 C158
VCC_15 VCCVRM
W23 B4 1D5V_S0 SCD1U16V2ZY-2GP
PLACE C2 OF PCH EAST CORNER
2
W25 VCC_16 VCCVRM_7 A4
VCC_17 VCCVRM_8 AF2
VCCADAC V_1P5_DAC_FB
AC12
VCCIO_16 AE1 V_3P3_BG R178 1 2 0R0603-PAD-1-GP-U
AM
V_1P05_XCK_DCB_FB_R VCC3_3_0 3D3V_S0 V_CPU_VCCIO2PCH
C PCH_1D05V R150 1 2 0R0805-PAD-1-GP-U AB1 B6 C
VCC VCC3_3_5
1
U12 AW21 C502 C132
PCH_1D05V VCCCLK_1 VCC3_3_4
V14 SCD1U16V2ZY-2GP SC1U10V2KX-1GP
VCCCLK_2
1
(R) W14 AM7

3D3V_S0
2
C121 C111 AB2 VCCCLK VCCCLK3_3_1 AM9
PCH_1D05V SC1U6D3V2KX-GP SC10U10V5KX-2GP AA16 VCCCLK VCCCLK3_3_2 AP5
2
VCCCLK VCCCLK3_3_3
1
W16 AP7 C537 C539 C544
T16 VCCCLK VCCCLK3_3_4 AR4 SC1U6D3V2KX-GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C523 1 2 SC1U6D3V2KX-GP V16 VCCCLK VCCCLK3_3_5 AT5
2
VCCSSC VCCCLK3_3_6 AV4
P14 VCCCLK3_3_7 AW4
C514 1 2 SC1U6D3V2KX-GP P16 VCCIO_1 VCCCLK3_3_8 AW9
P17 VCCIO_2 VCCCLK3_3_9 AG12
T
P22 VCCIO_3 VCCCLK3_3_10 AK11
C512 1 2 SC1U6D3V2KX-GP P23 VCCIO_4 VCCCLK3_3_11 AV3
P25 VCCIO_5 VCCCLK3_3_12 AW3
P26 VCCIO_6 VCCCLK3_3_13 3D3V_S5
C511 1 2 SC1U6D3V2KX-GP P28 VCCIO_7 U30
LA
1D5V_S0 VCCIO_8 VCC3_3_1 3D3V_S0
T19 W30
T20 VCCIO_9 VCC3_3_2
(R) AF19 VCCIO_10 AF26 C516 1 2 SC1U6D3V2KX-GP
C510 1 2 SCD1U16V2ZY-2GP AF20 VCCIO_11 VCC3_3_3
PCH_1D05V AF22 VCCIO_12 AG1 C520 1 2 SC1U6D3V2KX-GP
AF23 VCCIO_13 VCCSUS3_3
VCCIO_14 20131015 Madrid SA
AP22 R41 H81 not support ME power state (Only M0; W/O M3) C521 1 2 SC1U6D3V2KX-GP
VCCUSBPLL VCCPSPI 3D3V_S5
C515 1 2 SC1U6D3V2KX-GP M14
VCCIO_15 AW26
PCH_1D05V VCCSUS3_3 3D3V_S5
1D05V_ME AA23
VCCASW_1
1
IX
C517 1 2 SC1U6D3V2KX-GP AA25 AM33 C543 C518
AA26 VCCASW_2 VCCPSUS3_3 AN33 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
C119 1 2 SCD1U16V2ZY-2GP AB22 VCCASW_3 VCCPSUS3_3
2
C522 1 2 SC1U6D3V2KX-GP AB23 VCCASW_4 AH18 3D3V_S5
VCCASW_5 VCCSUS3_3 20131015 Madrid SA
AB25 AH20 H81 not support ME power
VCCASW_6 VCCSUS3_3
STITCH CAP FOR GEN2 B AB26
VCCASW_7 VCCSUS3_3
AH22
ACKUP CLOCK ROUTE AD17 AJ20 C554 1 2 SC1U6D3V2KX-GP
AD19 VCCASW_8 VCCSUS3_3 AK20
VCCASW_9 VCCSUS3_3
B
.F
AD20
AD22
AD23
VCCASW_10
VCCASW_11
VCCSUS3_3
VCCRTC
P20
AP35 RTC_AUX_S5
B
W26 VCCASW_12 AV39
VCCASW_13 VCCDSW3_3 3D3V_S5
AD25 AW38 C533 1 2 SCD1U16V2ZY-2GP
VCCASW VCCDSW3_3
1
AF25 AW39 C542
1D05V_ME PCH_1D05V 1D05V_ME VCCASW VCCDSW3_3 AP33 SCD1U16V2ZY-2GP
VCCRTC RTC_AUX_S5
W
2
C39
V_PROC_IO V_CPU_VCCIO2PCH
C524 1 2 SC10U6D3V5MX-3GP
20131015 Madrid SA AU40 V_1P05_DSW_INT_R R703 1 2 5D11R3F-1-GP V_1P05_DSW_INT_C C540 1 2 SC1U6D3V2KX-GP
DCPSUSBYP AU41
H81 not support ME power DCPSUSBYP
C519 1 2 SC1U6D3V2KX-GP 0402
AJ22 TP_V_1P05_USBSUS_INT 1 TP125 TPAD28-1-GP-U
DCPSUS
AW35 V_1P5_RTC_INT
W
DCPRTC
AH28 V_1P5_STBY_INT
DCPSST
1
C536
1
AE30 TP_PCH_AE30 1 TP134 TPAD28-1-GP-U C527 SCD1U16V2ZY-2GP
DCPSUS SCD1U16V2ZY-2GP
2
P19 TP_PCH_P19 1 TP124 TPAD28-1-GP-U
2
DCPSUS
W
LYNX-POINT-2-GP-U
(KI.H8101.002)
A A
<Core Design>
Wistron Corporation
Title
PCH Power
C
Madrid SA
5 4 3 2 1
5 4 3 2 1
STRAP
7 HSW_STRAP_13
Straping Pin define
12 SATA1GP
12 SATA2GP HDA_SPKR
3D3V_S0 R738 1 (R) 2 1KR2J-1-GP
12 SATA3GP
13 DSWVRMEN
13 IGC_EN_N
13 PCH_INTVRMEN
P_GNT_N3 R672 1 (R) 2 1KR2J-1-GP
13,18 HDA_SPKR
11 P_GNT_N1 PCH_INTVRMEN
RTC_AUX_S5 R202 1 2 390KR2J-GP
11 P_GNT_N2
11 P_GNT_N3
R201 1 (R) 2 1KR2J-1-GP
D D
BOOT SELECT STRAPS

P_GNT_N1 R198 1 2 1KR2J-1-GP
(R) GNT1/ SATA1GP
BOOT DEVICE GPIO51 /GPIO19
3D3V_S0 R255 1 2 10KR2J-3-GP SATA1GP
LPC 0 0
R256 2 (R) 1 1KR2J-1-GP
SATA1GP/GPIO19 SPI 1 1
DESIGN NOTE:
WEAK INTERNAL PULLUPS ON GP51. DEFAULT SPI BOOT DEVICE.
P_GNT_N2 R195 1 (R) 2 1KR2J-1-GP
M
O
DESIGN NOTE:
3D3V_S0 R280 1 (R) 2 1KR2J-1-GP SATA2GP DMI RX TERMINATION
SATA2GP/GPIO36
R281 1 (R) 2 10KR2J-3-GP
DESIGN NOTE:
R272 1 2 1KR2J-1-GP SATA3GP LOW:TLS CIPHER SUITE WITH NO CONFIDENTIALITY.
SATA3GP/GPIO37 HIGH:TLS CIPHER SUITE WITH CONFIDENTIALITY.
R289 2 (R) 1 10KR2J-3-GP
.C
C C
DSWODVREN - On Die DSW VR Enable
HIGH Enabled (DEFAULT)
AM
LOW Disabled
PCH1J 10 OF 11 RTC_AUX_S5
AT1 U11 TP_PCH_U11 1 TP116 TPAD28-1-GP-U

AT41 VSS_NCTF_1 TP22 U10 TP_PCH_U10 1 TP115 TPAD28-1-GP-U R249 1 2 390KR2J-GP DSWVRMEN
AU1 VSS_NCTF_2 TP23 AJ14 TP_PCH_AJ14 1 TP120 TPAD28-1-GP-U
AV1 VSS_NCTF_3 TP21 AK14 TP_PCH_AK14 1 TP117 TPAD28-1-GP-U
AV2 VSS_NCTF_4 TP20 K34 TP_PCH_K34 1 TP137 TPAD28-1-GP-U R250 1 2 390KR2J-GP
AV40 VSS_NCTF_5 TP14 K33 TP_PCH_K33 1 TP138 TPAD28-1-GP-U
AV41 VSS_NCTF_6 TP15 AH24 TP_PCH_AH24 1 TP129 TPAD28-1-GP-U
VSS_NCTF_7 TP12 (R)
AW2
AW40 VSS_NCTF_8 L16 TP_PCH_L16 1 TP121 TPAD28-1-GP-U
B40 VSS_NCTF_9 TP10 K16 TP_PCH_K16 1 TP119 TPAD28-1-GP-U
B41 VSS_NCTF_10 TP11 AM34 TP_PCH_AM34 1 TP141 TPAD28-1-GP-U
VSS_NCTF_11 TP9
T
C41
D1 VSS_NCTF_12
D41 VSS_NCTF_13
VSS_NCTF_14 R12 TP_PCH_R12 1 TP122 TPAD28-1-GP-U
TP3 N12 TP_PCH_N12 1 TP118 TPAD28-1-GP-U
TP4 L22 TP_PCH_L22 1 TP126 TPAD28-1-GP-U
TP1 K22 TP_PCH_K22 1 TP127 TPAD28-1-GP-U
TP2
HASWELL Strap
LA
R4
TP5 K5 3D3V_S5
TP6 P5
TP7 L5
TP8
AC31
VSS
1
3D3V_S5
R321
10KR2J-3-GP
2
R264 QF2_2
B AF3 1KR2J-1-GP B
VSS AV21
IX
VSS QF1
2
1 6
LYNX-POINT-2-GP-U IGC_EN_N R275 1 2 0R0402-PAD PCH_GP8 R314 1 2 10KR2J-3-GP QF2_1 2
5
1
HSW_STRAP_13 3 4
(KI.H8101.002)
R726
1KR2J-1-GP
MBT3904DW1T1G-2-GP
2
.F
W
W
W
A A
<Core Design>
Wistron Corporation
Title
PCH(GND/STRAPS)
D
Madrid SA
5 4 3 2 1
5 4 3 2 1
PCH1I 9 OF 11 PCH1K 11 OF 11
D9 A12
E12 VSS_121 VSS_1 A16 D12 AN28
E3 VSS_122 VSS_2 A21 D13 VSS_100 VSS_62 AP4
E31 VSS_123 VSS_3 A35 D14 VSS_101 VSS_63 AP9
E35 VSS_124 VSS_4 AA10 D16 VSS_102 VSS_64 AR11
E5 VSS_127 VSS_7 AA14 D20 VSS_105 VSS_67 AT10
E7 VSS_128 VSS_8 AA17 D22 VSS_106 VSS_68 AT11
F18 VSS_129 VSS_9 AA22 D24 VSS_107 VSS_69 AT14
D F37 VSS_132 VSS_12 AA34 D27 VSS_110 VSS_72 AT18 D
G2 VSS_134 VSS_14 AA8 D31 VSS_112 VSS_74 AT21
H14 VSS_135 VSS_15 AB14 D32 VSS_113 VSS_75 AT23
H16 VSS_136 VSS_16 AB28 U4 VSS_114 VSS_76 AT24
H20 VSS_137 VSS_17 AB4 U8 VSS_182 VSS_77 AT28
H22 VSS_138 VSS_18 AC30 V26 VSS_183 VSS_78 AT29
H34 VSS_142 VSS_22 AC8 W12 VSS_187 VSS_82 AT7
H38 VSS_143 VSS_23 AD14 W20 VSS_188 VSS_83 AT8
H4 VSS_144 VSS_24 AD26 W22 VSS_189 VSS_84 AU3
H6 VSS_145 VSS_25 AD28 W28 VSS_190 VSS_85 AU39
H8 VSS_146 VSS_26 AE12 W3 VSS_191 VSS_86 AV12
H9 VSS_147 VSS_27 AE31 W5 VSS_192 VSS_87 AV17
J31 VSS_148 VSS_28 AE4 W8 VSS_193 VSS_88 AV33
J37 VSS_149 VSS_29 AE41 Y1 VSS_194 VSS_89 AW30
J5 VSS_150 VSS_30 AE8 Y41 VSS_195 VSS_90 AW7
K31 VSS_151 VSS_31 AF14 VSS_196 VSS_91 B25
K4 VSS_152 VSS_32 AF16 VSS_92 B3
K9 VSS_153 VSS_33 AF17 VSS_93 B30
L37 VSS_154 VSS_34 AF28 VSS_94 B33
L41 VSS_155 VSS_35 AG2 VSS_95 B38
M16 VSS_156 VSS_36 AG30 VSS_96 C25
M18 VSS_157 VSS_37 AG34 VSS_97 C37
M
M20 VSS_158 VSS_38 AG38 VSS_98 C6
M22 VSS_159 VSS_39 AG8 VSS_99 D34
M24 VSS_160 VSS_40 AH14 VSS_115 D37
M26 VSS_161 VSS_41 AH16 VSS_116 D4
M28 VSS_162 VSS_42 AJ1 VSS_117 D6
N31 VSS_163 VSS_43 AJ28 VSS_118 D7
N35 VSS_164 VSS_44 AK24 VSS_119 D8
N38 VSS_165 VSS_45 AK37 VSS_120
N4 VSS_166 VSS_46 AK9 LYNX-POINT-2-GP-U
N8 VSS_167 VSS_47 AL11
VSS_168 VSS_48
O
R1 AL37
VSS_169 VSS_49 (KI.H8101.002)
R10 AL5
R34 VSS_170 VSS_50 AM14
R8 VSS_171 VSS_51 AM16
T17 VSS_172 VSS_52 AM18
T22 VSS_173 VSS_53 AM20
T23 VSS_174 VSS_54 AM24
T25 VSS_175 VSS_55 AM26
T26 VSS_176 VSS_56 AM35
T28 VSS_177 VSS_57 AM38
VSS_178 VSS_58
.C
U1 AM4
U31 VSS_179 VSS_59 AM6
U32 VSS_180 VSS_60 AM8
VSS_181 VSS_61
C C
LYNX-POINT-2-GP-U
(KI.H8101.002)
T AM
LA
B B
IX
.F
W
W
W
A A
<Core Design>
Wistron Corporation
Title
PCH(GND/STRAPS)
D
Madrid SA
5 4 3 2 1
5 4 3 2 1
F_HPO_R
R527 2 1 0R0402-PAD-2-GP
F_HPO_L
Analog Moat Digital Moat
R469 2 1 0R0402-PAD-2-GP AGND MIC_VREFL
MIC_VREFR TP30 TPAD28

AGND
R531 2 1 0R0402-PAD-2-GP AGND MIC2_VREFL
MIC2_VREFL 19
closed to codec
SC2D2U10V3KX-1GP
AGND
C297 (78.10693.41L) down size/cost Charles 20121004
ADU_LDO_CAP 1 2
AGND
D R465 2 1 0R0402-PAD-2-GP R447 2 1 0R0402-PAD-2-GP SC10U16V5KX-GP-U V_5_CODEC D
1
C299 5V_S5
change 20131216
AGND AGND AUD_VREF C301 1 2SCD1U16V2KX-3GP
AGND
2
1 2
SC100P50V2JN-3GP
C300 1 2 (R) L25 FCM1608KFG-301T05-GP
(68.00335.091)
2
SC2D2U10V3KX-1GP V_5_CODEC
SCALAR_OUT_R C322 D14
19,21 SCALAR_OUT_R
AUD_CPVEE
(R) AZ5125-01H-R7G-GP
2
SCALAR_OUT_L V_5_CODEC (75.YSE05.077)
19,21 SCALAR_OUT_L
MainSource0822
1
C632 AGND C298 C305
CM 10/16 SC2D2U10V3KX-1GP (78.10693.41L) SCD1U16V2KX-3GP CM 10/17
1
C306 C318 2 1AUD_CBN SC10U16V5KX-GP-U change 20131216 MOUNT
M 2
2
CODEC_LINE_IN_SENSE (78.10693.41L) SCD1U16V2KX-3GP
1
21 CODEC_LINE_IN_SENSE SC10U16V5KX-GP-U change 20131216 AUD_CBP AGND
2
20110113EMI
36
35
34
33
32
31
30
29
28
27
26
25
AUDIO1 AGND 20140108 Madrid -1A Charles
AGND
Analog Moat Modify C302,C312 as 10uF 25V
VREF
CBP
CPVEE
LDO-CAP
CBN
HP-OUT-R
MIC1-VREFO-R
HP-OUT-L
MIC1-VREFO-L
MIC2-VREFO
AVSS1
AVDD1
5V_S0 AGND
O
C2916 close to codec PIN39 23" SPK Source (R)
LINE1_R* C294 1 2 SC1U16V3KX-2GP SCALAR_OUT_R
HD_LINK L63 SC10U10V5ZY-1GP 37 24 LINE1_R* C302 1 (A) 2 LINE1_R
1 2 AVSS2 LINE1-R SC10U25V5KX-GP LINE1_L* C321 1 2 SC1U16V3KX-2GP SCALAR_OUT_L
1
1
C635 FCM1608KFG-301T05-GP C644 C645 38 23 LINE1_L* C312 1 (A) 2 LINE1_L (R)
13 HDA_SDIN0 SC10U10V5ZY-1GP C633 (U) (U68.00335.141) (R) (U) AVDD2 LINE1-L SC10U25V5KX-GP
.C
13 HDA_CODEC_SDOUT AUD_PVDD_1 39 22 FM_R_CODEC
(U) SCD1U16V2ZY-2GP
PVDD1 MIC1-R
CM 10/16 Reserved
2
2
13,18,19 HDA_CODEC_RST#
13 HDA_CODEC_SYNC SPKR_L+ 40 21 FM_L_CODEC Front Combo MIC in Scalar line out to codec line in
13 HDA_CODEC_BITCLK SCD1U16V2ZY-2GP SPK-L+ MIC1-L
SPKR_L- 41 20
SPK-L- MONO-OUT R875 20KR2F-L-GP
2012/08/28_aPisa_SA 42 19 JDREF_1 1 2
C PVSS1 JDREF AGND C
AM
27 DMIC_DATA SENSE_B JD_LOT_R
27 DMIC_CLK
43 18 R887 1 2 39K2R2F-L-GP
PVSS2 SENSE_B R882 1 2 20KR2F-L-GP MIC_IN_JD
SPKR_R- 44 17 MIC2_R Real Line-in/MIC sense
SPK-R- MIC2-R MIC2_R 19
13,16 HDA_SPKR SPKR_R+ 45 16 MIC2_L Real MIC in
Close to codec PIN46 SPK-R+ MIC2-L MIC2_L 19
AUD_PVDD_2 46 15 LINE2_R*C339 1 0R0603-PAD-2-GP-U
2 LINE2_R
19 LINE2_R PVDD2 LINE2-R Real Line Out
19 LINE2_L
1
(R) C643 Combo Jack 47 14 LINE2_L* C344 1 0R0603-PAD-2-GP-U

2 LINE2_L 20121007 Charles Marge material
18,19 Combo Jack EAPD/COMBO_JACK LINE2-L
C642 (U) mount 0ohm to improve performance
19 LINE1_R 48 13 SENSE_A
SC10U10V5ZY-1GP 2012/08/28_aPisa_SA
19 LINE1_L SPDIFO SENSE_A
2
2012/08/19_aPisa_SA R895 1 2 39K2R2F-L-GP JD_HP_R
GPIO0/DMIC-DATA
T GPIO1/DMIC-CLK
2012/09/10_aPisa_SA SCD1U16V2ZY-2GP Delete SPDIF circuit 49 Front HP sense
GND R883 1 2 10KR2F-2-GP CODEC_LINE_IN_SENSE
19 SPKR_L+ Vendor suggest
20121007_aPisa Charles (S) 23" SPK Source(Line1-in) sense
SDATA-OUT
19 SPKR_L-
SDATA-IN
Only MIC1 con use combo function
DVDD-IO
PCBEEP
RESET#
BIT-CLK
DVDD1
Digital Moat
DVSS2
LA
19 SPKR_R-
SYNC
19 SPKR_R+
PD#
2012/08/28_aPisa_SA
10
11
12
MIC_VREFL ALC269Q-VC-GR-GP PCH_SPKR1 1 R1001 2 HDA_SPKR
19 MIC_VREFL
4K7R2J-2-GP
1
2
F_HPO_R C325 R1000
19 F_HPO_R F_HPO_L BZ_ON 20131122 Madrid SB Charles
SC100P50V2JN-3GP
L65 1 2 4K7R2J-2-GP
19 F_HPO_L 1 2 +AUD_DVDD_1 SC1U16V3KX-2GP C763 Add PCH Beep to CodeC
IX
3D3V_S0
1
FCM1608KFG-301T05-GP
2
1
1
FM_L_CODEC (68.00335.091) C650 C652
19 FM_L_CODEC
SCD1U16V2ZY-2GP +DVDD-IO 3D3V_S0
FM_R_CODEC
19 FM_R_CODEC
2
SC10U10V5ZY-1GP
1
C655
B SCD1U16V2ZY-2GP B
19 MIC_IN_JD
.F
2
HDA_SDIN0_C
19 JD_HP_R
20110113EMI C354 1 2 SC100P50V2JN-3GP
DMIC_DATA
Combo Jack DMIC_CLK HDA_CODEC_RST#
18,19 Combo Jack
C353 1 2 SC100P50V2JN-3GP
HDA_CODEC_SYNC
W
R529 1 HDA_SDIN0
2
from PCH1D
33R2J-2-GP
HDA_CODEC_BITCLK
3D3V_S5 HDA_CODEC_SDOUT
19 JD_LOT_R
W
2
R508 R522
20111214
1KR2J-1-GP 1KR2J-1-GP
Follow Bremen design
buzzer 20131010 Madrid Charles
W
20121011_aPisa_SB Charles (N) (N) cancel BUZ

PD#_C
Modify
1
3 1
PD 1 Q61
PMBS3904-1-GP R523
(N84.T3904.H11) 0R2J-2-GP
2
3
(A)
HDA_CODEC_RST# 2 R518 1 AUD_LINK_RST_N1 1 Q60
13,18,19 HDA_CODEC_RST#
1
PMBS3904-1-GP
10KR2J-3-GP
(N84.T3904.H11)
PD_N1 2
A A
(N)
<Core Design>
3
(R)
19,20 SIO_Audio_Mute
SIO_Audio_Mute 2
R417
1 SIO_Audio_Mute# 1 Q46 Wistron Corporation
PMBS3904-1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
10KR2J-3-GP
(N84.T3904.H11) Taipei Hsien 221, Taiwan, R.O.C.
2
Title
3D3V_S5 (N)
2 R415 1 AUDIO CODEC-ALC269Q
10KR2J-3-GP Size Document Number Rev
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
20140108 Madrid -1A Charles

R513 (A) C337 Modify C337 , C331 as 10uF 25V C676 2 1(R)
Scalar LOT/AMP SW
5V_S5_AMP P3P3V
P3P3V
SEL L:A1(LineOut)
H:A2(AMP)
5V_S5_AMP AMP_IN_L 1 (A) 2AMP_IN_LC
C1595
SC10U25V5KX-GP
1
100KR2F-L1-GP
2 SPKR_LINP_R 1 (A) 2 AMP_LP
SC10U25V5KX-GP AmpGNG Moat R932 1
SCD1U16V2ZY-2GP
(A) 2
5V_S5_AMP R506 (A) C331 0R2J-2-GP
1
AMP_IN_R 1 (A) 2AMP_IN_RC 1 2 SPKR_RINP_R 1 (A) 2 AMP_RP
PC_MONITOR_SW
1
SCA1 Pin 63(JD_LOT) C662 C663 C1594 100KR2F-L1-GP SC10U25V5KX-GP
R443 (A) R429 (A) SC1U10V2KX-1GP SCD1U16V2ZY-2GP SEL L:A1(MONITOR) H:A2(PC) SC10U25V5KX-GP AmpGND
JD_LOT: L --> SEL : L:A1(LineOut)
2
1
1
4K7R2J-2-GP 4K7R2J-2-GP (A) (A) RESERVED ESD D3004
R428 (R) JD_LOT: H --> SEL : H:A2(AMP) C661 20140110 Madrid -1A Charles R1 P3P3V 19V_AMP
2
1KR2J-1-GP SC1U10V2KX-1GP
C660 SCD1U16V2ZY-2GP Add C1594,C1595 as 10uF 25V
2
PC_MONITOR_SW2
SCD1U25V2KX-2-GP
AGND (A) (A) (A)R504 (A)R515
R2 100KR2F-L1-GP
SC1000P50V3JN-GP-U
100KR2F-L1-GP
1
20130430 RYAN U45 (A73.74157.CHH) C279 C283
MainSource0822 SCALAR_LO_AMP_R U43 (A73.74157.CHH) AGND 19V_AMP (A)R452 (A) (A) TC13 (A) TC15 (R)
Reserved for drive
1
6 1 MainSource0822 SC10U25V5KX-GP
SC10U25V5KX-GP
2
5 SEL A2 2 LINE1_R 1 6 100KR2J-1-GP
PC_MONITOR_SW1 PC_MONITOR_SW SCALAR_OUT_R VDD GND CodeC A2 SEL
D S 4 3 2 5
2
DA A1 GND VDD
1
SCALAR_LO_R SCALAR_LO_AMP_R 3 4 AMP_IN_R AmpGND AmpGND AMP1 (A)
A1 DA C672 2 1(R) (A)R521
AZAW1210C-R7G-GP SCD1U16V2ZY-2GP 10R2J-2-GP AMP_PDN# 1 28 AmpGND
20131027 Q50 SCALAR_LIN_AMP_SW1 AGND AZAW1210C-R7G-GP PC_MONITOR_SW1 R1||R2 = R3 1 2 AMP_FLAG 2 SD# LPVDD 27
2N7002-7F-GP AMP_LP FLAG# LPVDD SPKR_OUT_LP_R
Delete SMB for digital AMP U46 (A73.74157.CHH) AGND R928 1 (A) 2 R1,R2,R3 use 1% resister 0R2J-2-GP R476 3 26 C3411(A) 2SCD22U25V3KX-3-GP
2
(A84.2N702.J31) MainSource0822 SCALAR_LO_AMP_L U44 (A73.74157.CHH) 0R2J-2-GP (A63.10234.1DL) AMP_LN 4 LINP LBSP 25 SPKR_OUT_L+
6
SEL A2
1 MainSource0822 to avoide "Pop" issue AMP_GAIN0 5 LINN
GAIN0
LOUTP
PGND
24 AmpGND
5 2 LINE1_L 1 6 AMP_GAIN1 6 23 SCD22U25V3KX-3-GP
SCALAR_OUT_L 4 VDD GND 3 2 A2 SEL 5 AmpGND AMPAVDD 7 GAIN1 LOUTN 22 SPKR_OUT_LN_R C3431(A) 2 SPKR_OUT_L-
DA A1 SCALAR_LO_L SCALAR_LO_AMP_L 3 GND VDD 4 AMP_IN_L 8 AVDD LBSN 21 SPKR_OUT_RN_R C3461(A) 2
A1 DA AGND RBSN
1
D AMP_VCLAMP 9 20 SCD22U25V3KX-3-GP SPKR_OUT_R- D
AZAW1210C-R7G-GP R3 R485 (R) AMP_PLIMIT 10 VCLAMP ROUTN 19 AmpGND
1
5V_S5_AMP P3P3V AGND AZAW1210C-R7G-GP 1 2 SPKR_LINN_R C654 1 (A) 2 AMP_LN C280 10KR2J-3-GPAmpGND AMP_RN 11 PLIMT PGND 18
P3P3V AmpGND AMP_RP RINN ROUTP SPKR_OUT_RP_R SPKR_OUT_R+
SC1U25V3KX-1-GP
AGND SC10U25V5KX-GP (A) 12 17 C3471 2 19V_AMP
R894 (A)49K9R2F-L-GP 13 RINP RBSP 16 (A) SCD22U25V3KX-3-GP
2
NC#13 RPVDD
1
1 2 SPKR_RINN_R C651 1 (A) 2 AMP_RN 14 15
GND
AmpGND MONO RPVDD
SC1000P50V3JN-GP-U
SCD1U25V2KX-2-GP
R922 R923 (A) SC10U25V5KX-GP
1
4K7R2J-2-GP 4K7R2J-2-GP R889 (A)49K9R2F-L-GP
HP Out Switch Line Out Switch
1
20131211 Madrid SB Charles (A) R924 (R) C673 2 1(R) APA2619RI-GP C303 C311
29
1KR2J-1-GP LINE2_L (N) R453 1 2 LOT_L SCD1U16V2ZY-2GP (A) (A) TC14 (A) TC16 (R)
Delete Scalar I2S
2
SCALAR_LIN_AMP_SW2 P3P3V AmpGND AmpGND SC10U25V5KX-GP
SC10U25V5KX-GP
PC_MONITOR_SW 0R2J-2-GP
2
R929 1 (A) 2
2
LINE2_R (N) R446 1 2 LOT_R
L:Monitor H: PC SEL L:A1(MONITOR) H:A2(PC) 0R2J-2-GP
CM 10/15 20130430 RYAN
Reserved for drive RESERVED ESD D3004 0R2J-2-GP AmpGND
1
Vmin = Vin - 5.5V 5V_S5_AMP
C329 C335 AmpGND
SCALAR_LIN_AMP_SW1 SCALAR_LIN_AMP_SW SC1U10V2KX-1GP SCD1U16V2ZY-2GP
SC1U10V2KX-1GP
SCD1U16V2ZY-2GP
D S AmpGND
2
(A) (A) U29
1
C671 2 1(R)
(A84.2N702.J31) Q93 1 10 F_HPO_R C628 C625 SCD1U16V2ZY-2GP
2N7002-7F-GP (R) F_HPO_L 2 V+ NO2 9 F_HPO_R* (A) (A)
Close to AMP1 Pin9 Close to AMP1 Pin10
GND Moat
2
1 R1079 2 JD_LOT F_HPO_L* 3 NO1 COM2 8 SCALAR_HP_OUT_R_2 R927 1 (A) 2
SCALAR_HP_OUT_L_2 4 COM1 NC#8 7 U20 (A73.74157.CHH) R907 0R2J-2-GP
0R2J-2-GP PC_MONITOR_SW 5 NC#4 IN2 6 MainSource0822 AMP_VCLAMP 1 2 AMP_PLIMIT
20131224 Madrid -1A Charles IN1 GND LINE2_R 1 6 AGND 3D3V_S0 3D3V_S0 要要要SCALAR
A2 SEL
1
"SCALAR_LIN_AMP_SW" pull high to P3P3V 2 5 10KR2J-3-GP 做POWER ON/OFF AmpGND
M
"JD_LOT" pull high to P3P3V GND VDD
1
"SCALAR_LIN_AMP_SW1" pull high to 5V_S5_AMP TS5A22364DGSR-1-GP SCALAR_LO_R 3 4 CONTROL
A1 DA (A)
(A) AGND R906 C315 AMP_PDN#
1
LOT_R 3KR2F-GP SC1U10V2KX-1GP
Support iPhone ~ Mount R3018,R3020
2
AZAW1210C-R7G-GP PC_MONITOR_SW1 (R) R500 R450 (R) C307
HP Source SEL (A)
2
AGND SC1U10V2KX-1GP
unMount R3019,R3021 (A)
2
U23 (A73.74157.CHH) 100KR2J-1-GP 100KR2J-1-GP C674 2 1(R)
LOT_L (A)
Scalar Audio MainSource0822 SCD1U16V2ZY-2GP
2
(N) LINE2_L 1 6 AMP_GAIN0
F_HPO_L F_HPO_L* A2 SEL
18,21 SCALAR_OUT_R
SCALAR_OUT_R Support Nokia ~ Mount R3019,R3021 R517 1
0R2J-2-GP
2
SCALAR_LO_L
2
3 GND VDD
5
4 AMP_GAIN1
R930 1 (A) 2
0R2J-2-GP
AmpGND AmpGND
A1 DA
18,21 SCALAR_OUT_L
SCALAR_OUT_L
unMount R3018,R3020
O
1
1
(N)
F_HPO_R R512 1 2 F_HPO_R* AZAW1210C-R7G-GP R507 R451 AmpGND
21 SCALAR_HP_OUT_R_2 0R2J-2-GP AGND
0R2J-2-GP 0R2J-2-GP
21 SCALAR_HP_OUT_L_2 C675 2 1(R)
2
SCD1U16V2ZY-2GP
CM 10/16 Change to downsize bead R931 1 (A) 2

0R2J-2-GP
MIC_VREFL R872 2 1 MIC_IN_JACK SPKR_OUT_L+ L30 1 2 HCB2012KF-102T10-GP
.C
2K2R2J-2-GP (A) AmpGND
Control Combo Audio Jack modify FM_L_CODEC C636 1 2SC2D2U10V3KX-1GP L36 SPKR_L+ L35 1 2 MHC1608S221NBP-GP SPKR_OUT_L+_C
1
(63.00000.00L) (N)
JD_HP FM_R_CODEC C634 1 2 MIC2 R8731 2 1 2 C324 (78.33124.2FL) SPK1
21 JD_HP
SC2D2U10V3KX-1GP 1KR2J-1-GP FCM1608KFG-301T05-GP SC100P50V2JN-3GP
2
1
5
R916 (R) SPKR_OUT_L- L29 1 2 HCB2012KF-102T10-GP
18 JD_HP_R AmpGND
1
R871 SPKR_OUT_L+ C6561 2 SPKR_OUT_LP_R1 1 210R2J-2-GP (A) AmpGND
22KR2J-GP
18 MIC_IN_JD C332 (R) SC330P50V2KX-3GP 1
AUDS1 SPKR_L- SPKR_OUT_L-_C
(78.10224.2FL) R917 (R) L38 1 2 MHC1608S221NBP-GP
AmpGND
2
SC100P50V2JN-3GP SPKR_OUT_L- C6571 2 SPKR_OUT_LN_R1 1 210R2J-2-GP (N) 2
HP JD SEL P3P3V
1
C 19,21 PC_MONITOR_SW Combo Jack R530 1 2 NP2 (R) SC330P50V2KX-3GP 3 C
22KR2J-GP NP1 R918 (R) SPKR_OUT_R+ L28 1 2 HCB2012KF-102T10-GP C319 (78.33124.2FL) 4
AmpGND
1
AGND AGND SPKR_OUT_R- C6581 2 SPKR_OUT_RN_R1 1 210R2J-2-GP (A) SC100P50V2JN-3GP
AM
21 SCALAR_LIN_AMP_SW
2
SC10U6D3V3MX-GP
C345 Combo 7 (R) SC330P50V2KX-3GP
2
JD_HP 9 R919 (R) SPKR_R+ L39 1 2 MHC1608S221NBP-GP AmpGND SPKR_OUT_R+_C

AmpGND
6
R525 8 SPKR_OUT_R+ C6591 2 SPKR_OUT_RP_R1 1 210R2J-2-GP (N) ACES-CON4-35-GP-U
21 JD_LOT why need X level ? R503
1
10KR2J-3-GP F_HPO_R* 1 2 F_HPO_R_1 L32 1 2(68.00335.091) HP_OUT_R_CON 3 (R) SC330P50V2KX-3GP
P3P3V (S) AGND FCM1608KFG-301T05-GP C316 (78.33124.2FL)
75R2J-1-GP
SPKR_OUT_R- L33 1 2 HCB2012KF-102T10-GP SC100P50V2JN-3GP
18 JD_LOT_R R502
1
2
JD_HP_2 F_HPO_L* 1 2 F_HPO_L_1 L27 1 2(68.00335.091) HP_OUT_L_CON 2 (A) (20.F1819.004)
75R2J-1-GP FCM1608KFG-301T05-GP 1 AmpGND MainSource0822 C677 2 1(R)
2
SPKR_R- L41 1 2 MHC1608S221NBP-GP SPKR_OUT_R-_C AmpGND SCD1U16V2ZY-2GP

R514 (N)
1
10KR2J-3-GP Q57 AGND R933 1 (A) 2
PHONE-JK516-GP
6
(S) C328 (78.33124.2FL) 0R2J-2-GP

SC100P50V2JN-3GP
1
2
C317 C304
1
JD_HP AmpGND
SC100P50V2JN-3GP SC100P50V2JN-3GP AmpGND
1
2N7002KDW-GP (78.10224.2FL) (78.10224.2FL)
2
Enable Control (S75.27002.F7C)
JD_HP_R 2012/6/29_ROME SA
T
Low: Mute
High: no-MUTE AGND 20131023 Madrid SA Charles Add Line out Function
delet L22,L23,C290,C291
R497 1 (U) 2 20121014_aPisa_SB Charles AGND
SHDN_MUTE_AP_CTL 2010/06/09
Mount when UMA SKU 2012/08/19_aPisa_SA
LOT_R_2
21 SHDN_MUTE_AP_CTL
LOT_L_2
0R2J-2-GP
For 33Mhz TPM EMI issue
ADD Audio Jack (LOT OUT)
LA
R463 L20 LOT1
LOT_L TC11 1 2 LINE2_L_1 1 2 1 2 LOT_L_CON 2
E10U25VM-21-GP 75R2J-1-GP MHC1608S601LBP-GP JD_LOT 3 L
(09.10612.S8L) 4
19,21 PC_MONITOR_SW
EVGA_ON
C639 2
2
1 SCD1U16V2ZY-2GP
1 SCD1U16V2ZY-2GP
(R) ESD MIC_IN_R_JK 1
D26
Combo 1
D16
LOT_R TC12 1
E10U25VM-21-GP
2 LINE2_R_1 1
R475
75R2J-1-GP
2 1
L24
MHC1608S601LBP-GP
2 LOT_R_CON 5
1
R
SC100P50V2JN-3GP
C637 (R) (09.10612.S8L)
1
3 3 C308 C285 PHONE-JK416-GP
1
1 2 R454 R480 SC100P50V2JN-3GP (22.10270.R51)
R432 0R0402-PAD-2-GP MIC_IN_L_JK 2 JD_HP 2 22KR2F-GP 22KR2F-GP
18 LINE2_R
for Mute function modify; (63.22334.1DL) (63.22334.1DL) AGND
2
18 LINE2_L “SCLA_AMP_PDN” on SB change as P3P3V
2
AGND 20131202 Madrid SB Charles AZ2025-02S-R7G-GP AZ2025-02S-R7G-GP
18
18
LINE1_R
LINE1_L
Change Part to (75.05125.07D) (75.05125.07D)
D27
(75.05125.07D)
D12
“SCLA_Audio_Mute” on 1A
2
IX
C278 2 1 SCD1U16V2ZY-2GP (R) LOT_R_CON 1 HP_OUT_R_CON 1
1 2 R498 AGND
C276 1 2 0R0402-PAD-2-GP R462 0R0402-PAD-2-GP 3 3 10KR2J-3-GP
(63.R0034.1DL) 1 2 P3P3V (S)
C272 2 1 SC2200P50V2KX-2GP (R) R495 0R0402-PAD-2-GP LOT_L_CON 2 HP_OUT_L_CON 2
1
FM_L_CODEC JD_LOT_2
18 FM_L_CODEC
2
FM_R_CODEC AGND AZ2025-02S-R7G-GP AZ2025-02S-R7G-GP
18 FM_R_CODEC
AGND (75.05125.07D) 20131122 Madrid SB Charles (75.05125.07D) R505
Change form AGND to Digital GND 10KR2J-3-GP AGND
4
(S)
B B
1
Q56
JD_LOT
18 MIC_VREFL
MIC_VREFL
Audio Mute Control
.F (S75.27002.F7C)
3
2N7002KDW-GP
MUTE
De-POP Circuit
F_HPO_R
18 F_HPO_R F_HPO_L JD_LOT_R
18 F_HPO_L Control by software driver and CODEC GPIO.
GPIO driving low at: AGND
HDA_CODEC_RST# R516 1 (U) 2
13,18 HDA_CODEC_RST# 1).Initial state 20121014_aPisa_SB Charles
2).Suspend to S1 0R2J-2-GP Mount when UMA SKU
3).Resume from S1. Reserved when Audio mute canceled
Amp mute can control by Scalar when JD_LOT in
Amp mute can control by EC when HDA_RST#
ANALOG
W
P3P3V MUTE_2
AMP_PDN# AMP_PDN#
DIGITAL
P3P3V 3D3V_S0 AMP_IN_L
0R2J-2-GP
0R2J-2-GP
(R) (R) R445 (S)

18 SPKR_L+
20140108 Madrid -1A Charles 20140108 Madrid -1A Charles
2
R1091 R1093 MUTE 2 1

18 SPKR_L- AMP_IN_R
R938 R421 0R0603-PAD-2-GP
-1A unmount Add for Amp PD# pop
2
10KR2J-3-GP 10KR2J-3-GP R430 Q51

18 SPKR_R- MUTE_RR MUTE_R
(S) (S) R437 R436 1 (S) 2 1 (S84.T3906.E11)
18 SPKR_R+
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP PMBS3906-GP
1
6
SCLA_AMP_Mute (S) (R) R925 AMP_LP AMP_RP
SCD1U16V2ZY-2GP
2
2
Q49 C274 C273 1 (R) 2 LINE1_L_2* 5 2 Q94

SC4D7U6D3V3KX-GP
R431
1
MIC2_VREFL Q89 3.3_POP_1 1 (S) (S) AMP_LN AMP_RN

18 MIC2_VREFL
2N7002-7F-GP 1 2 1KR2J-1-GP MMDT3904-7-F-1-GP
W
D
MIC2_L
(S84.T3906.E11)
PMBS3906-GP
(S84.2N702.J31) 220KR2J-L2-GP (R84.01C03.01F)

18 MIC2_L
3
(S)C275 (S63.10434.1DL)
E
2
6
MIC2_R R420 (s) Q90 Q48 1 2 R1095 R1097
18 MIC2_R SCLA_Audio_Mute
20121116 AMP_LP* AMP_RP*
G 1 2 AZRST 1 B 1 (S) 2 5 2 Q101 1 (S) 2 5 2 Q102
Mount
1
Combo Jack 1KR2J-1-GP SCD1U16V2ZY-2GP

18 Combo Jack
(S84.T3906.E11)
PMBS3906-GP
(S84.T3906.E11)
MMBT3906-4-GP
R438 R435 R926 AmpGND AmpGND 1KR2J-1-GP MMDT3904-7-F-1-GP 1KR2J-1-GP MMDT3904-7-F-1-GP

S
1
P3P3V 0R2J-2-GP 1 (R) 2 LINE1_R_2* (S84.01C03.01F) (S84.01C03.01F)
2012/08/28_aPisa_SA 0R2J-2-GP
(S) (R)
Audio
1
Control circuit
1KR2J-1-GP 20121116 20121116
2
2
2
0R0402-PAD-2-GP
R468
Mount Mount
Mute R1089
10KR2J-3-GP P3P3V 3D3V_S5
(S)
R1094 AmpGND AmpGND R1096 AmpGND AmpGND
AMP CTRL (S) LOT_L_2 1 (S) 2 AMP_LN* 1 (S) 2 AMP_RN*
W
2
20131031 Madrid SA Charles R419 (S)

1
Add AMP control to Scalar SIO_Audio_Mute 1 2 SIO_Audio_Mute_2 LOT_R_2 1KR2J-1-GP 1KR2J-1-GP

1KR2J-1-GP 20121116
3.3_POP_1
R449 Q52
AMP_GAIN0 1 (S) 2 LINE2_L_2* 5 2
21 AMP_GAIN0
AMP_GAIN1 P3P3V 20121117 aPisa -1 Charles 1KR2J-1-GP
21 AMP_GAIN1
AMP PD# If (U) need Mute Circuit
4
MMDT3904-7-F-1-GP
(S) R1086 I. R3049 ,R3035,R520 : set as (U) (S84.01C03.01F) MIC2_VREFL
2
II. Q3025,Q3016,Q3021,C3044,C3045,C3046,R3050, 20121116

10KR2J-3-GP control R3051,R3014,R518,R3052,R3053,Q3023,Q3024 : Mount
3
Audio Mute Control AMP Mute set as Always mount R448 AGND AGND D25
1 (S) 2 LINE2_R_2* BAT54A-11-GP
1
AMP_PDN# (75.00054.R7D)
1KR2J-1-GP
A SCLA_Audio_Mute A
21 SCLA_Audio_Mute
2
D8207.1 D8207.2
SIO_Audio_Mute
18,20 SIO_Audio_Mute
E
2
R1087 (S) Q100 Q99 R1088 (S) SHDN_MUTE_AP_CTL
AMP_PDN# JD_LOT 1 2JD_LOT_amp_mut
B B3.3_POP_1_1
1 2 R876 R881
18,20 AMP_PDN# 20101229
1KR2J-1-GP 1KR2J-1-GP When the PC mode and Monitor 3D3V_S5 5V_S5 L: PC MODE 2K2R2J-2-GP 2K2R2J-2-GP
Vendor suggest
MMBT3906-4-GP
(S84.T3906.E11)
(S84.T3906.E11)
MMBT3906-4-GP
Scalar or EC
F_HPO_L*
F_HPO_R*
mode are being switched

C
change from 4.7k to 2.2k

JD_LOT has Pull High to P3P3V control Amp PD# low H: Monitor Mode
1
R509
2
MUTE_AP_CTL should be low C334 SC10U6D3V3MX-GP 1KR2J-1-GP L37 MIC1

R386 R379 MIC2_L 1 2 FM_L_CODEC_1 1 2 FM_L_CODEC_I 1 2 MIC_IN_L_JK 2
[aPisa] -1M 20130107 Charles
in order to avoid the
noise
1KR2J-1-GP 1KR2J-1-GP Change F_HPO_L / F_HPO_R to Q53 FCM1608KFG-301T05-GP MIC_IN_JD 3 L
(R) (R) F_HPO_L* / F_HPO_R* MMDT3904-7-F-1-GP (68.00335.091) 4
(S84.01C03.01F) C327 SC10U6D3V3MX-GP L34
R
1
R474 MIC2_R 1 2 FM_R_CODEC_1 1 2 FM_R_CODEC_I 1 2 MIC_IN_R_JK 5

HP_MUTE_1 HP_MUTE_1 1 (S) 2HP_L_2* 5 2 FCM1608KFG-301T05-GP 1
MUTE_AP_CTL also control when <Core Design>
R501 (68.00335.091)
select MUTE in the PC mode or 1KR2J-1-GP 1KR2J-1-GP PHONE-JK416-GP
Monitor mode
4
1
C326 C336 (22.10270.R51)
20131231 Madrid -1A Charles SC100P50V2JN-3GP SC100P50V2JN-3GP block color Wistron Corporation
20121116 (78.10224.2FL) (78.10224.2FL) AGND 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Mute function modify;
2
Mount AGND AGND
EC mute by HDA_RST# MUTE_AP_CTL also control when
system wake from S3 to S0 20121007_aPisa Charles Title
1 R496 HP_R_2*
Scalar mute by Pannel off control 2
20121025 Charles ALC269 Only MIC1 con use combo function AUDIO AMP
(S)1KR2J-1-GP
un-mount to diable Q3024 AGND Size Document Number Rev
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
3D3V_S5
SIO_VREF SIO_VREF SIO_VREF

PCHTMP
HW Monitor Michael 2011/12/15 CPUVRD GPUVRD
2
For 5VSB Monitor R175 R4 R22
10KR2F-2-GP 10KR2F-2-GP 10KR2F-2-GP
SIO_PSON_N R668 2 1 4K7R2J-2-GP
AMP R216
17K8R2F-GP
5V_S5 (G)
1
REMOTE1+ DIMM_TMPIN2 GPU_PIN3
SIO_VIN3 1 2 20131027 CM
1
Delete 24Mhz OSC
1
Charles 1018 RT3 RT1 C10 RT2 (G) R792 0R0402-PAD-2-GP
1
AMP_PDN# C154 R215 C128 C5 (G) SUSLED_R_N 1 2 SUSLED_N
19 AMP_PDN# NTC-10K-27-GP-U NTC-10K-27-GP-U NTC-10K-27-GP-U
SCD1U16V2ZY-2GP 10KR2F-2-GP
2
2
2
Add DIMMpower for H/W monitor SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
Layout Note: place it Layout Note: place it Layout Note: place it 1024 3D3V_S5
20131027 Madrid SA near CPU VORE MOS near PCH near GPU
D Delete SMB for digital AMP SIO_AGND SIO_AGND SIO_AGND D
1D5V_S3 VCC_CORE RN4
R229 3D3V_S0 RSMRST#_SIO 1 4
PWROK3_2_R 2 3
6K49R2F-1-GP
SIO_VIN4 1 2 Thermal Resistance SRN10KJ-5-GP
1
Layout Description SB EC Board ID Description
1
LPC G2
REMINE LAYOUT modify BD ID
1
13,50 LPC_AD0 COPPER-CLOSE-GP-U C157 R230 2012/09/14_aPisa_SA
SCD1U16V2ZY-2GP
13,50 LPC_AD1 10KR2F-2-GP
R222 Sensor EC H/W LPC_PME# 2 R920 1
13,50 LPC_AD2 ID2 ID1
2
13,50 LPC_AD3
1 2 Layout Monitor bit1 bit0 (GP33) bit1(GP34) bit0(GP35)
2
SIO_DEBUG_TX 10KR2J-3-GP
13,50 LPC_FRAME# HM_VCCP 50 SIO_DEBUG_TX
0R0402-PAD-2-GP
PCHTMP TMPIN1
1
R228 5V_S0 3D3V_A 3D3V_A 3D3V_A
11,21 LPC_PME# SIO_AGND 17K8R2F-GP SIO_AGND R749 SA 0 0 20131027 CM
CPUVRD TMPIN2
1
1
R1031 R666 SIO_VIN5 1 2
10KR2J-3-GP
GPUVRD TMPIN3 SB 0 1 ID3 ID2 ID1
1
Power Manager 10KR2F-2-GP 10KR2F-2-GP
2
1
R788 (S) R268 R271
1
C159 R227 H_PECI R715 1 2 0R0402-PAD-2-GP PECI_SIO_R SIO_DEBUG_RX 10KR2J-3-GP 10KR2J-3-GP (R) 10KR2J-3-GP
7,11,50 PLT_RST# 50 SIO_DEBUG_RX -1A 1 0
2
2
SCD1U16V2ZY-2GP 10KR2F-2-GP
1
SIO_VIN1 HM_VCCP_R
2
PLTRST_LAN_N 2 1 R712
28 PLTRST_LAN_N
100KR2J-1-GP R759
SM Bus PH -1 1 1
2
10KR2J-3-GP
PLT_WLAN_RST# 3D3V_A
46 PLT_WLAN_RST# SMB_DATA/CLK
1
1
C780 C528 SIO_BOARD_ID3 SIO_BOARD_ID2 SIO_BOARD_ID1
-2 0 0 RN15
2
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SIO_AGND R766 2 1 10KR2J-3-GP SIO_K8PWR_EN
3D3V_S0
1
R217 12V_S0 PCIRST2# 1 4
2
2
56KR2F-GP R787 (U) R269 R270 PCIRST1# 2 (R) 3
M
Reset signals 10KR2J-3-GP (R) 10KR2J-3-GP 10KR2J-3-GP
SIO_VIN2 1 2 ID3 SRN10KJ-5-GP
SIO_AGND SIO_AGND
34,35 S0_PWR_GOOD
W/ Scalar
2
1
PLT_RST# 2 1 33R2J-2-GP PLTRST*_SIO
R276
COM port Print port 1
1
C161 R218 ITE_DEB 2 R1083 1
SCD1U16V2ZY-2GP 20131224 Madrid -1A Charles
13,20,21,25,35,36,38,40,41
13,31,38
PM_SLP_S3#
PM_SLP_S4#
10KR2F-2-GP
PLT_WLAN_RST# R798 2 1 33R2J-2-GP PCIRST2# W/O Scalar 0 10KR2J-3-GP Add GP74 Pull High to 3D3D_A
2
5V_S5
2
49 PWRBTN_IN 20121011 Jerry 20121011_aPisa_SB Charles 20121023_aPisa_SB Charles RN11
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
PLTRST_GPU# R794 2 1 33R2J-2-GP
13 PM_PWRBTN#
Add GPU RST# Add Board 3 define ID3 SRN10KJ-6-GP
U31 MCLK 1 8
SIO_AGND MDAT 2 7
13.11/01 add
RI1#
DCD1#
DTR1#
SIN1/D_RX1
SOUT1/D_TX1
DSR1#
RTS1#
FAN_CTL4
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
STB#
AFD#
ERR#
INIT#
SLIN#
ACK#
SLCT
BUSY
PE
HSCK
PLTRST_AspireLink# R983 2 1 33R2J-2-GP KBCLK 3 6
O
PLTRST_AspireLink#--Kai 1005 KDAT 4 5
SIO_AVCC3
PLTRST_LAN_N R782 1 2 33R2J-2-GP PCIRST1# (68.00335.141)
L50
1 102 1 2
CLOCK EC_EUP 2 CTS1# HMOSI 101 MHC1608S181NBP-GP
3D3V_A
SIO_PCIRSTIN# 3 5VSB_CTRL#/CIRRX2/GP16 HMISO 100
14 CLK_48M_SIO 20131211 Madrid SB Charles PCIRSTIN#/CIRTX2/GP15/CPU_PG HSCE# For Power monitor function
1
SPI_WP_R_N need pull hig when DCin 4 99 C530 C529
14 CLK_PCI_SIO 3D3V_A 3VSB A3VSB HM_VCCP_R
LDRQ# 5 98 20131126 Madrid SB Charles SC1U10V2KX-1GP SC1U16V3KX-2GP
6 LDRQ# VIN0/VCORE_0D8V 97 SIO_VIN1 Add DIMMpower for H/W monitor (78.10520.5FL)
2
SLP_SUS#/VLDT_EN/GP63 VIN1/VDIMMSTR_1D2V
1
3D3V_A C572 7 96 SIO_VIN2
For AC OFF SEQUENCE SCD1U16V2ZY-2GP CPU_FANTACH1 8 GNDD VIN2 95 SIO_VIN3
modify to 78.10521.5BL due to cost down 20131209 Madrid SB Charles 20131211 Madrid SB Charles
.C
CPU_FANCTL1 9 FAN_TAC1 VIN3 94 SIO_VIN4
SIO_DAT_DB / SIO_CLK_DB Add SMBUS pull High
2
FAN_CTL1 VIN4/VLDT_12
1
EC_SMI# 10 93 SIO_VIN5 R223 1 2 1KR2J-1-GP
FAN_TAC2/GP52 VIN5/5VDUAL 3D3V_S0 change to 3D3V_S5 (follow Florence)
DCBATOUT 3D3V_S0 2012/09/10_aPisa_SA R905 20131224 Madrid -1A Charles 20131212 Madrid SB Charles SUSLED_R_N_PWM 11 92 SIO_MAIN_VCC3
3D3V_S5 change Sus LED control Pin to pin23 modify GPIO PLTRST*_SIO_R 12 FAN_CTL2/GP51 VCC3 91 SIO_VREF C156 1 2 SC1U10V2KX-1GP 3D3V_S5 3D3V_S5
10KR2F-2-GP Pin 11 is default PWMout, reserve for breath LED FAN_TAC3/GP37 VREF SIO_AGND
R802 1 2 4K7R2F-GP PWRGD_PS_L1 USB_PWR_EUP 13 90
SMBUS 27 USB_PWR_EUP FAN_CTL3/GP36 TMPIN1
REMOTE1+ (78.10520.5FL)
1
2
(R) SIO_BOARD_ID1 14 89 DIMM_TMPIN2
Note
2
R801 R784 SPI_WP_R_N SPI_WP_R_N_EC 1 R1084 2 SIO_BOARD_ID2 15 FAN_TAC4/GP35 TMPIN2 88 GPU_PIN3 R737
(63.47234.1DL) 13,29 SPI_WP_R_N SIO_BOARD_ID3 SUSWARN#/GP34 TMPIN3 VREF follow Moussy SIO_DAT_DB SMB_DATA_SIO
100KR2J-1-GP 0R2J-2-GP 20140103 Madrid -1A Charles 16 87 2 R745 1 2 1R1046
10KR2F-2-GP SUSACK#/GP33 TSD- SIO_AGND 20121123 aPisa -1A Charles
6
C HDA_CODEC_RST# to GP31/Pin18 SPI_WP_R_N_EC SIO_CLK_DB 10KR2J-3-GP 2 SMB_CLK_SIO10KR2J-3-GP 2 C

17 86 1 1R1047
13 SML1_CLK (63.10334.1DL) for Mute function modify HDA_CODEC_RST# DPWROK/GP32 GNDA ICH_RSMRST_N_R R210 Michael RSMRST# report to modify
Q80 R785 18 85 1 2 0R0402-PAD-2-GP RSMRST#_SIO 10KR2J-3-GP 10KR2J-3-GP
13 SML1_DATA 13,18,19 HDA_CODEC_RST#
2
1
PWRGD_PS_L (75.27002.F7C) PWRGD_PS_L2 1 2 SIO_ATXPG CPU_FANTACH1 SIO_ATXPG 19 PWMOUT/GP31 RSMRST#/CIRRX1/GP55 84 EC_Audio_Mute 1 (R) 2 AMP_PDN# RSMRST#_SIO 13
2N7002KDW-GP 0R0402-PAD-2-GP SUSLED_R_N SIO_UART1_RX 20 ATXPG/GP30 PCIRST3#/GP10 83 MCLK R1090 0R2J-2-GP
20,21 SIO_UART1_RX SIN2/GP27 MCLK/GP56
1
1
C571 SIO_UART1_TX 21 82 MDAT 1 2 SIO_Audio_Mute
20,21 SIO_UART1_TX SIO_Audio_Mute 18,19
1
R800 C576 SC100P50V2JN-3GP 22 SOUT2/GP26 MDAT/GP57 81 KBCLK R1092 0R2J-2-GP 20140106 Madrid -1A Charles
1 R1085 2 SUSLED_R_N_1 23 DSR2#/GP25 KCLK/GP60 80 KDAT 20131202 Madrid SB Charles Reserved 0 ohm to PD control, DSW_RSMRST
20KR2J-L2-GP SCD1U16V2ZY-2GP Change SIO_Audio_Mute to GP10 Default Low
AM
1
2
SIO_SI 24 RTS2#/GP24 KDAT/GP61 79 PWR_ID2 Add EC control pin for CNVBD2
PECI 7,12 H_PECI
(R) 0R2J-2-GP
SIO_SCK R776 2 1 33R2J-2-GP SIO_SCK_R 25 SI/GP23 3VSBSW#/GP40 78 PWROK3_2 R208 1 (R) 2 0R2J-2-GP PWROK3_2_R
2
BKLT_EN 26 SCK/GP22 PWROK2/GP41 77 PM_SLP_S4_N R667 1 2 0R0402-PAD-2-GP PM_SLP_S4#

3D3V_S0 PANEL_SW_EC 27 DCD2#/GP21 SUSC#/GP53 76 SIO_PSON_N
49 PANEL_SW_EC PCH_GPIO6 CTS2#/GP20 PSON#/GP42 PB_IN_N_1 3D3V_A
28 75
2 R793 1EC_DTR2#_PH 29 RI2#/GP17 PANSWH#/GP43 74
For OSD communication 10KR2J-3-GP
20140106 Madrid -1A Charles SIO_CE_N 30 DTR2# GNDD 73 LPC_PME# RN12
SML1_CLK_R
Add PCH SMI to thermal SHD output Pin 31 CE_N/CIRTX1 PME#/GP54 72 SW_ON_N_SIO C153 1 2 SC1U10V2KX-1GP SMBCLK2_SIO 1 4
PWROK3_1_R 1 2 33R2J-2-GP PWROK3_1 32 PCH_C1/GP14/VCORE_EN PWRON#/GP44 71 PM_SLP_S3# SMBDAT2_SIO 2 3
OTHERS R361
PCIRST1# 33 PWROK1/GP13 SUSB# 70 SYS_3VSB 1 R213 2
(78.10520.5FL)
PCIRST2# 34 PCIRST1#/GP12 SYS_3VSB 69 VBAT_SIO 100R2F-L1-GP-U

3D3V_S5
R207 1 2 0R0402-PAD-2-GP
RTC_AUX_S5
Case Open Detection SRN10KJ-5-GP
35 PCIRST2#/GP11 VBAT 68 SIO_COPEN# R211 1 2 1KR2J-1-GP Note: COPEN# should be connected to GND
12 H_RCIN# SPI Interface 3D3V_A
CLK_48M_SIO
SIO_VCORE 36
37
3VSB
VCORE
COPEN#
3VSB
67
66 SMBCLK2_SIO 3D3V_A when this function is not be used. CM 10/16
12 EC_SMI# CLKIN D_RX0/SMCLK2/GP46
1
C570 38 65 SMBDAT2_SIO
GNDD D_TX0/SMDAT2/GP47 20131204 Madrid SB Charles
1
12 INT_SERIRQ 20131209 Madrid SB Charles SCD1U16V2ZY-2GP C574 (R) 20131027 CM C531 modify to 78.10521.5BL due to cost down
R781 / R778 / R775 / R779 / R780 / R267 SCD1U16V2ZY-2GP C575 20131126 Madrid SB Charles C532 SC1U16V3KX-2GP
PCH_D1/SST/AMDTSI_D
2
IO_SCI#/GP85/SMDAT0
3D3V_A SC2D2U10V3KX-1GP Add EC control pin for CNVBD2 SCD1U16V2ZY-2GP
Change to 10K ohm ( follow Florence)
2
for EUP Note:
*Place C869,C883 close to IT8732
PECI/AMDTSI_C
GP72/KSO0/JP1
Note: 20131127 Madrid SB Charles *Recommended net "V_3P3_A" minimum trace width 12mils.
GP86/SMCLK0
20,49 SUSLED_N unmount C575 avoid resumrest error/boot fail
*Place C570, C574,C575 close to IT8732 3D3V_A
KRST#/GP62
GP77/KSO5
GP76/KSO4
GP75/KSO3
GP74/KSO2
GP73/KSO1
GP71/KSI1
GP70/KSI0
LFRAME#
LRESET#
T SO/GP50
2
1
SMDAT1
SMCLK1
SERIRQ
20121203 aPisa -1 Charles
PCICLK
WRST#
R781 R778 R775 R779 R780 R267 R799
GA20
20121016 aPisa SB Charles delet R8002 & P3P3V pull high
LAD0
LAD1
LAD2
LAD3
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 3D3V_A 20131202 Madrid SB Charles 0R0603-PAD-2-GP-U --> it's wrong power plane
Mount panel on/off EC control only W/O Scalar delete "PANEL_CTRL" Net, Madrid useless
IT8732F-CX-GP Delete RN14 --> SIO_UART1_TX no need pull high
1
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
2
U34 03/14 from PIN63 to PIN17_Ryan R1033 SCALAR_SIO_PU
SIO_PCIRSTIN# 1 210KR2J-3-GP
SIO_PSON_N
SIO_CE_N
SIO_SO
1
CE# VCC
8
SIO_HOLD#
SIO_SMDAT0
SIO_SMCLK0 SIO_SMDAT0 22
Delete Q72,R721,R705,R708 caus Madrid no use SIO_UART1_TX P3P3V 3D3V_A
2 7
35 SIO_PSON_N SIO_WP# SO HOLD# SIO_SCK SIO_SMCLK0 22 change GP75/pin57 LVDS_BL_EN_1 as PWR_ID SIO_UART1_RX
R1034
LA
3 6 1 210KR2J-3-GP
WP# SCK
1
4 5 SIO_SI INT_SERIRQ 3D3V_A
GND SIO LPC_FRAME# R1048 1 2 0R2J-2-GP GPU_SMDAT0 LVDS_BL_EN* R686 R685 (63.10234.1DL)
LPC_AD0 GPU_SMDAT0 54
R1049 1 2 0R2J-2-GP GPU_SMCLK0 10KR2F-2-GP 10KR2F-2-GP
LPC_AD1 GPU_SMCLK0 54
PM25LD010C-SCE-GP (R)
1
(72.25010.R01) C568 LPC_AD2 DET_HDMI

LPC I/F
2
LPC_AD3 SCALAR_EN EUP_DSW_SEL
change to 1Mbit SCD1U16V2ZY-2GP (R)
H_RCIN# EUP_DSW_SEL SIO_PANEL_ON 1
R697
210KR2J-3-GP
2
1. layout trace is as far as possible short contract issue, H_A20GATE SIO_PANEL_ON

CLK_PCI_SIO ITE_DEB SIO_PANEL_ON 21 2013/05/09 VENDOR CHANGE 1KOHM_RYAN
and change P/N need check SIO_SO
3D3V_A 20131212 Madrid SB Charles PWR_ID1 20131202 Madrid SB Charles 20131224 Madrid -1A Charles 20131121 Madrid SB Charles
SIO_UART1_RX 2. Pull-up resistor 1Kohm near SPI Flash PLTRST*_SIO modify GPIO PWR_ID0 Add EC control pin for CNVBD2 Add R1083 Pull High to 3D3D_A
20,21 SIO_UART1_RX SIO_UART1_TX SIO_WRST# SIO_WRST# PECI_SIO_R
delet SIO_PANEL_OFF net pull high JP1=1 EUP
R241 1 2 JP1=0 DSW
20,21 SIO_UART1_TX SMB_CLK_SIO 2 SIO_CLK_DB
10R0402-PAD-2-GP PLT_WLAN_RST#_A 3D3V_S0
R752
SMB_CLK_SIO SMB_DATA_SIO 2 SIO_DAT_DB
1 0R0402-PAD-2-GP SML1_DATA_R
100KR2J-1-GP R722
SMB_DATA_SIO
1
C550 LVDS_BL_EN_1 R265
21,43 DET_HDMI# 1 2
SC1U16V3KX-2GP PCHD1 SMB LDRQ#
SCALAR_EN
2
30 SCALAR_EN 10KR2J-3-GP
20121029 Madrid SB Charles 20121016 aPisa SB Charles
IX
For EC domain,
12V_HDD
reset after power up GP75 or GP74 must pullhigh To 3D3V_A
R628
1 2 12V_S0_FAN ITE 8732 workaround PS8625_BKLT_EN
B 12V_S0_FAN FAN CTRL (prevent enter LPT debug mode
22,23 PS8625_BKLT_EN
LBN
3D3V_A 3D3V_S0 RN3 B
0R3J-0-U-GP SRN2K2J-1-GP
system will boot fail ) 1 4
1
20130429 if cost down 12V, unmount R7979, mount R8001 1kohm and R7980 20kohm_Ryan 2 3
CPU_5V_FANCTL1 C487 (S) 3D3V_S0
R1042 SC10U16V5ZY-GP SCALAR_EN R676 1 2 10KR2J-3-GP
2
1 2 (78.10622.51L) 12V_S0
20131027 CM (R) 0R3J-0-U-GP R234 1 (R) 20R2J-2-GP
5V OPA Fan CTRL
1
H_A20GATE
12 H_A20GATE
R136
3D3V_S0
4K7R2J-2-GP
R137
.F EUP Control for 3D3V_S5 & 5V_S5 Disable / Enable
SML1_CLK 6
5
1
2
SML1_CLK_R
2
5V Bead CPU_FANTACH1_1
20KR2J-L2-GP
1 2 CPU_FANTACH1
Q22
4 3
0.4A 2N7002KDW-GP To ECIO
1
EC_EUP_EN#
20,35 EC_EUP_EN# 84.2N702.A3F
K
R144 D18 FANC1 3D3V_A PCHD1 SMB 2nd = 84.DM601.03F

1
2K2R2J-2-GP 1N4148WS-7-F-GP 12V_S0_FAN 5 C787 3D3V_A

1 (75.27002.F7C) SML1_DATA_R
(R) 8K2R2F-1-GP SC100P50V2JN-3GP
HDMI IN DET Connect High
2
1
R141
Normal Low
2
PLTRST_AspireLink# 2 R804 R660 SML1_DATA

25 PLTRST_AspireLink#
2
A
3 3D3V_A 10KR2J-3-GP 100KR2J-1-GP

CPU_FANCTL1 1 2 CPU_FANCTL1_CONN 4 (S)
W
R142 6 3D3V_A R251 1 (R) 2 0R2J-2-GP
PWRBT Signal
1
2
PLTRST_GPU# 100R2F-L1-GP-U DET_HDMI
51,54 PLTRST_GPU# EC_EUP_EN# 20,35
1
C486 CLX-CON4-9-GP 20130504 ADD ISOLATION_Ryan
1
SC1U25V5ZY-4GP R783
PWROK3_1_R (R) PB_IN_N_1 C150 2 1 SCD1U16V2ZY-2GP R212
10KR2J-3-GP
D
13,35 PWROK3_1_R
2
10KR2J-3-GP
D
Q79 (S)
1
SUSLED_N R786 2N7002 1 2 PWRBTN_IN

20,49 SUSLED_N
2
EC_EUP 1 2 EC_EUP_EN G SOT-23 0R0402-PAD-2-GP
2
0R0402-PAD-2-GP (84.2N702.J31) R214 DET_HDMI# G (S84.2N702.J31)
S
R205 (R) Connect Low Q21

2013/4/29 Delete_Ryan
S
1
(R) 0R2J-2-GP 2N7002-7F-GP

C573 R219
Normal High
1
SCD1U16V2ZY-2GP SW_ON_N_SIO 1 2 PM_PWRBTN#
W
34 CPU_FANCTL1
2
0R0402-PAD-2-GP HDMI_IN_DET#_R
20121114 aPisa -1A Charles
1
LCD ID fix HDMI IN detect
3D3V_A R650 20121115 aPisa -1A Charles
100KR2J-1-GP Add 4148 to prevent leckeg
PWR_ID0 (S63.10234.1DL)
23 PWR_ID0 (EC)TP_IO_SCI =>(PCH) PM_SLP_S3#
2
PWR_ID1
23 PWR_ID1
2
PWR_ID2 R665
23 PWR_ID2
10KR2F-2-GP
0.8VCC3-> S0_PWR_GOOD (R)
BKLT_EN 20131127 Madrid SB Charles
23 BKLT_EN
1
HDMI_IN_DET# Delete D19,R662 caus Madrid no use
3D3V_S0 SIO delay:
Power Good 3V 23h<3:2>
CONVERTOR SMB michael 2012/2/16 SB
W
HDMI_5V Q64
00b 01b 10b
4
3D3V_A (R)
23 SMBCLK2_SIO 3D3V_A 1KR2J-1-GP
23 SMBDAT2_SIO 2013/06/26 Change time sequence for PCH_PWRGD Ryan 400ms / 15ms / 200ms PM_SLP_S3# TP_IO_SCI
R360
reserve for iRST circuit 13,20,21,25,35,36,38,40,41 PM_SLP_S3#
2
2
20131023 Madrid SA Charles 2N7002KDW-GP
2
according to customer's request R732 check list modify ; R645
3
2
10KR2J-3-GP cancel 1.05VTT_PWRGD 4K7R2J-2-GP

R253 PWROK3_1_R 1 2 PWRGD_3V (R)
20131126 Madrid SB Charles PWRGD_3V 6,12,13
Add EC control pin for CNVBD2 10KR2J-3-GP (R) R350 0R2J-2-GP Connect High
1
1
(R) 3D3V_S5 HDMI_PWR_IN
A PLTRST*_SIO_PU PLT_WLAN_RST#_PU Normal Low A
1
R351
6
3D3V_A 1KR2J-1-GP
6
3D3V_A 3D3V_S0
BATTERY CHARGER Q76 (R)
(R) Q74
2
2
2012/08/18_sPisa_SA 2N7002KDW-GP (R) PWRGD_3V_B_1 C203 R356

2
Delete Battery Charger 2N7002KDW-GP R719 SC100P50V2JN-3GP 20KR2J-L2-GP

1
R231 R716 10KR2J-3-GP

1
10KR2J-3-GP 10KR2J-3-GP (R)

6
(R) (R)
1
Q36
1
PWROK3_2_R RSMRST*_R
Thermal shuntdown
R232 (R) R720 (R) R209 1 2 1KR2J-1-GP (R)
PLTRST*_SIO PLTRST*_SIO_C 2 1 PLTRST*_SIO_R PLT_WLAN_RST#_A PLT_WLAN_RST#_C 2 1 PLT_WLAN_RST# 2N7002KDW-GP
PCH_GPIO6 (R)
20 PCH_GPIO6
1
33R2J-2-GP 33R2J-2-GP
<Core Design>
Wistron Corporation
Title
ITE-8732
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
SSID = Scalar
PCIE
Main EEPROM Michael 2011/11/30
MTK_USB_SW Remove EEPROM for OSD from GPU
46 MTK_USB_SW
BEAD 要 30ohm@100MHz(1A) EEPROM for OSD
PVCC_3V3 PVCC_3V3
MTK_SHARE 2009/12/08
46 MTK_SHARE
1
R818
1
2013/05/07 ADD_Ryan 10KR2J-3-GP
(R)
(S)
C197 PVCC_3V3
Audio Out AVCC DVCC SCD1U16V2ZY-2GP
2
P3P3V PVCC_3V3 TMDS_3V3 P3P3V PVCC_3V3_SDRAM P1P2V VCCK_1V2 ADC_1V2 U37
Shielding
2
L55 L8 L54 L17 L10
(S) R809 72.24C16.S01, ST LCD ON/OFF Michael 2011/12/02
8
7
6
5
CE R791 1 2 22R2J-2-GP CE#_1 1 8 22R2J-2-GP (S)
18,19 SCALAR_OUT_R
1 2 1 2 1 2 1 2 1 2 SDOUT R819 1(S) 2 22R2J-2-GP SO_1 2 CE# VCC 7 (S)
72.24C16.U01, ATMEL RN8
18,19 SCALAR_OUT_L FLASH_WP WP#_1 SO HOLD# CLK_1
1 2 3 6 1 2
(S68.00335.141) (S68.00335.141) (S68.00335.141) (S68.00335.141)
MHC1608S181NBP-GP
(S68.00335.141)
R817 0R0402-PAD-2-GP 4 WP# SCK 5
CLK
U8 PVCC_3V3
SRN4K7J-10-GP Need check the Panel power later
MHC1608S181NBP-GP MHC1608S181NBP-GP GND SIO
1
MHC1608S181NBP-GP MHC1608S181NBP-GP (S) SB Modify
SDIN_1 1 2 1 8
LVDS-OUT C222 (S) C605 C224 (S) R816 SDIN
1
2
3
4
SC4D7U6D3V3KX-GP SCD1U16V2ZY-2GP SC4D7U6D3V3KX-GP 10KR2J-3-GP PM25LD020C-SCE-GP 2 NC#1 VCC 7 WP_PRO PVCC_3V3 PVCC_3V3
2
TXE3+ (S) (S) R808 3 NC#2 WC# 6 EESCL
22,23 TXE3+ 4 NC#3 SCL 5
TXE3-
Need Check 22R2J-2-GP EESDA
2
D 22,23 TXE3- TXEC+ VSS SDA D
22,23 TXEC+ (S)
2
TXEC- (S)
22,23 TXEC- TXE2+ M24C16-WMN6TP-3-GP R376
22,23 TXE2+
1
22,23 TXE2-
TXE2-
TXE1+
如如如如如 OD，
，建建建建建建 10uF(MLCC) (S72.02416.B01) (S)
C234
10KR2J-3-GP
22,23 TXE1+ TXE1- SCD1U16V2ZY-2GP
SCALAR_VDD_EN 23
1
22,23 TXE1- TXE0+ MainSource0822
22,23 TXE0+
22,23 TXE0-
TXE0- Michael 2012/2/6 LCDVDD_EN1
22,23 TXO0-
22,23 TXO0+
TXO0-
TXO0+ Pin55
TXO1-
22,23 TXO1- TXO1+
22,23 TXO1+ TXO2-
22,23 TXO2- TXO2+
22,23 TXO2+ TXOC-
22,23 TXOC- TXOC+
22,23 TXOC+ TXO3-
22,23 TXO3- TXO3+
22,23 TXO3+
Pin 118 PVCC_3V3
功功功功:
PW ON Latch功
M
DHMI-IN Internal MCU :Pull High
C198 [aPisa] -1M 20130107 Charles Michael
External MCU :Pull Low 20131027 CM (S)
43 HDMI_HDCP_READY Swap ODD and EVEN bus 1 2
Change R1406 and R1407 from short pad to
10u 0603 (78.10610.5BL) 2012/4/11 -1
43 HDMI1_SDA 20131027 CM
SCD1U16V2ZY-2GP
43 HDMI1_SCL PVCC_3V3 TXE3+ TXO0-
43 DDC_WP DPD_AUXN_S DPD_AUXN_C
C179 1 2 SCD1U10V2KX-5GP TXE3- TXO0+ R842 (S78.10522.5BL)
2
DPD_AUXP_S C180 1 2 SCD1U10V2KX-5GP DPD_AUXP_C TXEC+ TXO1- SCALAR_HP_OUT_R 1 2 SCALAR_HP_OUT_R_2
43 HDMI1_D0-
R790
4K7R2J-2-GP DPD_LANE0N_S C587 1 2 SCD1U10V2KX-5GP DPD_LANE0N_C EVEN TXEC-
TXE2+
TXO1+
TXO2- ODD SC10U6D3V3MX-GP
PVCC_3V3
O
(S) DPD_LANE0P_S C586 1 2 SCD1U10V2KX-5GP DPD_LANE0P_C TXE2- TXO2+ R841 (S78.10522.5BL)
43 HDMI1_D0+ DPD_LANE1N_S DPD_LANE1N_C SCALAR_HP_OUT_L SCALAR_HP_OUT_L_2
C589 1 2 SCD1U10V2KX-5GP TXE1+ TXOC- 1 2
43 HDMI1_D1-
1
CE DPD_LANE1P_S C588 1 2 SCD1U10V2KX-5GP DPD_LANE1P_C TXE1- TXOC+ SC10U6D3V3MX-GP

43 HDMI1_D1+
20131027 Madrid SA Charles TXE0+ TXO3-
43 HDMI1_D2-
1
(R) Swap Back to previous version of 1025 TXE0- TXO3+

43 HDMI1_D2+
1
R807
43 HDMI1_CK+ 10KR2J-3-GP 2012/09/30_aPisa_SB
C223 R520 R524
43 HDMI1_CK- VCCK_1V2 Change to 0603 short PAD
SCD1U16V2ZY-2GP 1KR2J-1-GP 1KR2J-1-GP
(R) (R)
20,43 DET_HDMI#
2
1 2
2
.C
(S)
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
R830
R796
R317
R921
R813
eDP-IN 20131029 Madrid SA Charles 20131211 Madrid SB Charles
Delete Scalar I2S
12 DPD_AUXN_S Colay Pin Vender review : pin 101 & 102 (R) (R) (R) (R) (S)
1
12 DPD_AUXP_S only can be controled when LCD on AGND
CM 10/15
102
101
100
PANEL_ON
eDP-IN- Afert serial capacity SCA1 (S)
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
4 DPD_LANE0N_S
4 DPD_LANE0P_S DPD_AUXN_C PANEL_OFF
HDMI_5V
GPIO/PWM0/SD3/SPDIF3
GPIO/PWM5
GPIO/PWM4
GPIO/PWM3#99
GPIO/PWM2
GPIO/PWM1
GPIO/PWM0
TXE0-_8B
TXE0+_8B
TXE1-_8B
TXE1+_8B
TXE2-_8B
TXE2+_8B
TXEC-_8B
TXEC+_8B
TXE3-_8B
TXE3+_8B
PGND
PVCC
GPIO/TXO0-_8B
GPIO/TXO0+_8B
GPIO/TXO1-_8B
GPIO/TXO1+_8B
GPIO/TXO2-_8B/IIS_WS/SPDIF3
GPIO/TXO2+_8B/IIS_SCK/SPDIF2
GPIO/TXOC-_8B
GPIO/TXOC+_8B
GPIO/TXO3-_8B/IIS_MCK/SPDIF1
GPIO/TXO3+_8B/IIS_SD0/SPDIF0
VCCK
GPIO/PWM3#72
GPIO/SPDIF3/SD3/PWM1/PWM5
GPIO/SPDIF2/SD2/IICSDA
GPIO/SPDIF1/SD1/IICSCL
GPIO/SPDIF0/SD0
GPIO/MCK
GPIO/SCK
GPIO/PWM1/T2EX/WS
4 DPD_LANE1N_S 22 DPD_AUXN_C DPD_AUXP_C
4 DPD_LANE1P_S RTD2486HXD-CG-GP
22 DPD_AUXP_C
1
DPD_LANE0N_C R837
22 DPD_LANE0N_C DPD_LANE0P_C SCALAR_LIN_AMP_SW 19,21
10KR2J-3-GP
22 DPD_LANE0P_C DPD_LANE1N_C (S)
AM
22 DPD_LANE1N_C DPD_LANE1P_C PC_MONITOR_SW 19,21
C CONRTOL 22 DPD_LANE1P_C
C
2
DPD_HPD
22 DPD_HPD HDMI_DET1 BLON_EN# 21,23
21,23 SCALAR_BKLT_CTRL PVCC_3V3
22 TMDS_3V3 SHDN_MUTE_AP_CTL 21
1
21,23 BLON_EN#
R838
2
20KR2J-L2-GP
21 SHDN_MUTE_AP_CTL
(R) (S)
R814
2
4K7R2J-2-GP
CM 10/16 20140107 Madrid -1A Charles
1
20121018 Ryan modify mute sch
CODEC_LINE_IN_SENSE delete HP_MUTE
18 CODEC_LINE_IN_SENSE
DPD_HPD 21,23 SCALAR_BKLT_CTRL 103 64 2012/09/30_aPisa_SB
PC_MONITOR_SW 104 GPIO/PWM1/SD2/SPDIF2/IICSCL/DVI_CTRL_OUT2 INT1/T2/SD0/SPDIF0/PWM0/PWM3/GPIO 63 JD_LOT Modify JD_LOT to Pin63 C604 2 (S) 1 SCD1U16V2ZY-2GP
AMP_GAIN0 105 GPIO/SD1/SPDIF1/IRQ#/IICSDA DVI_CTRL_OUT1/INT0/PWM2/GPIO 62
GPIO/SD0/SPDIF0/AUX_TXDATA PVCC PVCC_3V3_SDRAM
T
106 61 C233 2 (S) 1 SCD1U16V2ZY-2GP
CM 10/15 PVCC_3V3_SDRAM PVCC PGND
1
(S) 2 1 107 60 VCCK_1V2

R857 FLASH_WP C582 SCD1U16V2ZY-2GP 108 PGND VCCK 59 SIO_UART1_RX_R R840 1 SIO_UART1_RX
2 0R0402-PAD-2-GP
AMP_GAIN1 GPIO/MCK/AUX_OE TXD/DDCSDA1/GPIO SIO_UART1_TX_R SIO_UART1_TX
100KR3J-L-GP 109 58 R839 1 2 0R0402-PAD-2-GP short pad
DPD_HPD 110 GPIO/PWM2/INT0/SCK/AUX_D1 RXD/DDCSCL1/GPIO 57 EESDA
20131211 Madrid SB Charles GPIO/INT1/WS/SD1 IICSDA/GPIO CODEC_LINE_IN_SENSE
111 56
Delete Scalar I2S EESCL
Michael 2012/2/15 SB R393 (S)
2
PANEL_ON 112 GPIO/T0/SD0/SPDIF0 IICSCL/GPIO 55 LCDVDD_EN1 CODEC_LINE_IN_SENSE_R 1 2 CODEC_LINE_IN_1

SCLA_Audio_Mute 113 GPIO/T1/SD1/WS/SPDIF1 PWM1/PWM5/GPIO_USB 54 PWM_SW_EN
GPIO/SD2/SCK/SPDIF2/AUX_D2 PWM4/GPIO Add R9553 and R9555
LA
HDMI_HDCP_READY 114 53 HDMI_DET1 2009/12/13 10KR2J-3-GP
GPIO/PWM4/SD3/MCK/SPDIF3 USB_DDCSDA1/A_ADC3/GPIO PANEL_SW_SC
20121018 Ryan
CLK 115 52
SDIN 116 SPI_SCLK/SDIO USB_DDCSCL1/A_ADC2/GPIO 51 SCALAR_LIN_AMP_SW
SDOUT 117 SI/MCU_SCLK A_ADC1/GPIO 50 CODEC_LINE_IN_SENSE_R
SO/SCS# A_ADC0/GPIO
3
CE 118 49 [aPisa] -1M 20130107 Charles PVCC_3V3
VCCK_1V2 C581 2 1 SCD1U16V2ZY-2GP RTD_PIN119 119 CE#/IRQ# LS_ADC_VDD 48 SCALAR_HP_OUT_R
DPD_AUXP_C
(S)
RTD_PIN121
120 GPO/PWM1/PWM5/SPDIF1
VCCK
PWM0/AUDIO_HOUTR/GPIO
AUDIO_HOUTL/SD0/GPIO
47 SCALAR_HP_OUT_L
S_46 C277
Add 10u 0603 cap (78.10610.5BL) through Pin45 and Pin46
SCALAR_OUT_R
To Line Out 2N7002KDW-GP
Q45
eDPin R316 1 2 0R0402-PAD-2-GP 121 46 1 2(S78.10522.5BL) SC10U6D3V3MX-GP (S75.27002.F7C)
GPIO/DDCSCL3/AUX_CH_P1 AUDIO_SOUTR/MCK/GPIO
1
DPD_AUXN_C 1 RTD_PIN122
2 0R0402-PAD-2-GP 122 45 S_45 C293 1 2(S78.10522.5BL) SC10U6D3V3MX-GP SCALAR_OUT_L
9,10,13,22,46,54 SMB_CLK
R315
To AMP C231
4
HDMI1_SDA 1 RTD_PIN123
2 0R0402-PAD-2-GP 123 GPIO/DDCSDA3/AUX_CH_N1 AUDIO_SOUTL/SCK/GPIO 44 RTD2482_VREF 3D3V_S0
9,10,13,22,46,54 SMB_DATA
HDMI1_SCL
R805
R327 1 RTD_PIN124
2 0R0402-PAD-2-GP 124 GPIO/DDCSDA2/AUX_CH_N0 PWM5/AUDIO_REF/SPDIF3/WS/GPIO 43
1A 20121007
SCD1U16V2ZY-2GP
(S) CM 10/16
2
RTD_RESETB 125 GPIO/DDCSCL2/AUX_CH_P0 IICSDA/LINE_INR/GPIO 42
RESET# IICSCL/LINE_INL/GPIO
Charles R395 (S)
1
21,23 BLON_EN# 126 41 EDID_RDY C608 (S) 1 2 CODEC_LINE_IN_2
SMBUS_ISP 14MHZ_OUT_SCALAR GPIO/PWM0/PWM1/SPDIF2/CEC GPIO#41 WP_PRO
Marge material
XO 127 40 SC1U25V3KX-1-GP
12 SMBUS_ISP XO GPIO#40
DP_GND/TMDS_GND
DDC_WP
DP_VDD/TMDS_VDD
XI 128 39 10KR2J-3-GP
2
XI GPIO#39
Vef power
LANE3N/RXCN_0
LANE3N/RXCN_1
LANE3P/RXCP_0
LANE3P/RXCP_1
LANE0N/RX2N_0
LANE1N/RX1N_0
LANE2N/RX0N_0
LANE0N/RX2N_1
LANE1N/RX1N_1
LANE2N/RX0N_1
LANE0P/RX2P_0
LANE1P/RX1P_0
LANE2P/RX0P_0
LANE0P/RX2P_1
LANE1P/RX1P_1
LANE2P/RX0P_1
IX
TMDS_VCC1_2
michael 2012/3/19 1A
TMDS_REXT
ADC_VDD33
Michael 2012/2/15 SB
ADC_GND
GPIO#31
GPIO#32
GPIO#33
GPIO#34
GPIO#35
GPIO#36
GPIO#37
remove R9552 and R9546 for TP
OSD
SOG0
change EDID_RDY connction
AHS0
AVS0
G0+
R0+
B0+
G0-
R0-
B0-
R815
49 PANEL_SW_SC
PANEL_SW_SC PVCC_3V3 1 1MR2J-1-GP
2 14MHZ_IN_SCALAR from pin35 to pin41 SHDN_MUTE_AP_CTL
(R)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SIO_UART1_RX
20 SIO_UART1_RX
2
SIO_UART1_TX
20 SIO_UART1_TX Michael 2011/12/01
1
X5
19,21 SCALAR_LIN_AMP_SW R323
4K7R2J-2-GP 3 2
XTAL from 27M to 14.318M R831
10KR2J-3-GP
19,21 PC_MONITOR_SW
(S)
Follow Vendor comment
.F (S)
1
2
DPD_LANE0P_C
DPD_LANE1P_C
DPD_LANE0N_C
DPD_LANE1N_C
B RTD_RESETB B
4 1 Monitor mode
C583 (R)
Michael 2011/12/28
1
PC_MONITOR_SW SC10U10V5KX-2GP (S78.15034.1FL) R337

1 2
C184
XTAL-14D31818MHZ-37-GP
SC33P50V2JN-3GP
Pull down to 10 for depop when AC ON
According to the IR decode or side key (R)
2
C584 (S) TMDS_3V3 6K2R2J-1-GP

value to switch the satus of monitor mode Monitor DET_HDMI# SCALAR_EN Panel EN/PWM/CTRL
HDMI1_CK+
HDMI1_D0+
HDMI1_D1+
HDMI1_D2+
(S78.15034.1FL)
HDMI1_CK-
HDMI1_D0-
HDMI1_D1-
HDMI1_D2-
and PC mode SC33P50V2JN-3GP R319 0 1 Active

R331 SIO_PANEL_ON
W
20 SIO_PANEL_ON
1 2
PVCC_3V3 1 2 RTD_PIN2 DET_HDMI#
EDID_RDY SHDN_MUTE_AP_CTL 10KR2J-3-GP
13 EDID_RDY JD_HP
6K2R2F-GP eDPin R370 (U) DET_HDMI# : connect to SIO and Scalar
(S) PM_SLP_S3#_R 1 2 PM_SLP_S3#
2
TMDS_3V3 PANEL_ ID0_S 0R0402-PAD-2-GP R812 PANEL_ON3 2 R318 1 LPC_PME#

PANEL_ ID1_S PANEL_ON PANEL_ON1
To SIO: make scalar workable -> Scalar_EN 1(From SIO)
R806 1 2
Panel On Off CTRL 4K7R2J-2-GP 20130417 Follow Dallas_ Ryan PANEL_ ID2_S
0ohm short pad 0R0402-PAD-2-GP To Scalar: Let scalar know HDMI IN, and make related signal
(S)
2013/03/05 Reserved_Ryan ADC_1V2
10KR2J-3-GP
(S)
active, Panel and AMP
11,20 LPC_PME#
1
C185 C188 C207
3
RTD_PIN119 SC10U6D3V3MX-GP (S) S)
W
SCD1U16V2ZY-2GP(
(S)
2
SCD1U16V2ZY-2GP
2N7002KDW-GP
1
PTD_PIN119 C209
1
Pull Up--> Normal Mode 2010/02/24 Q31
Pull Down-> Scan Mode
Michael 2011/11/30 (S)
SCD1U16V2ZY-2GP
C212 (S)
SC4D7U6D3V3KX-GP (75.27002.F7C)
4
3D3V_S0
HDMI side: Remove VGA input
2
HDMI0 => RX2 pair 1
R333
2 PANEL_ON2
HDMI1 => RX1 pair 10KR2J-3-GP
HDMI2 => RX0 pair
13,20,25,35,36,38,40,41 PM_SLP_S3#
HDMICK => RC pair
W
JD_HP
19 JD_HP
19 SCALAR_HP_OUT_R_2
19 SCALAR_HP_OUT_L_2
JD_LOT
19 JD_LOT
20131104 Madrid SA Charles Panel ID Selectiong
Firmware update by SMBUS
AMP CTRL delete PANEL_ON_OFF_PCH
Add AMP control to Scalar SMBUS_ISP SMBUS_ISP PVCC_3V3 PVCC_3V3 PVCC_3V3
Michael 2011/12/01 ISP_CLK1 SMB_DATA ISP_CLK1 PCH_DVI_DATA
1
SCLA_Audio_Mute PVCC_3V3
21 SCLA_Audio_Mute ， DVI如
PC Mode，如如建 S0，
，考考如如 3D3V_S0 (S) (S) (S)
5V_S0 R828 R829 R365
4
AMP_GAIN0 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
19 AMP_GAIN0
2
A DPD_HPD 3D3V_S0 3D3V_S0 Q82 Q81 A

4K7R2J-2-GP
AMP_GAIN1
R843
19 AMP_GAIN1 2N7002KDW-GP 2N7002KDW-GP
2
1
(S75.27002.F7C) (S75.27002.F7C) PANEL_ ID2_S PANEL_ ID1_S PANEL_ ID0_S

G
R844
D
3
1
PVCC_3V3 (S) 10KR2J-3-GP R334

1
Q87 R332 10KR2J-3-GP

EDP_BKLTCTL S D BKLT_CTRL_1 D S SCALAR_BKLT_CTRL 2N7002 (R) 10KR2J-3-GP (R) SMB_CLK ISP_DAT1 PCH_DVI_CLK ISP_DAT1
12,22,23 EDP_BKLTCTL
2
Q87_G G SOT-23 (S) SMBUS_ISP SMBUS_ISP

2
2
(84.2N702.J31) PCH_DVI_CLK R329 1 2 47R2J-2-GP HDMI1_SCL

2
1
R845
Q88 Q86
S
10KR2J-3-GP R826
2N7002A-7-GP 2N7002A-7-GP (S) (S) 10KR2J-3-GP
(S) EDP_HPD_N PCH_DVI_DATA HDMI1_SDA 3D3V_S0 3D3V_S0 3D3V_S0
(S84.2N702.J31) (S84.2N702.J31) R820 1 2 47R2J-2-GP
12 EDP_HPD_N
1
2
PWM_SW_EN PWM_SW_EN
20121015 Ryan
20131105 Madrid SA Charles <Core Design>
1
(S)
1
delete PANEL off relay circuit SMBUS_ISP H ：Simutaneous Mode Michael 2012/3/8 -A
R825
10KR2J-3-GP
(S)
R822
R823
4K7R2J-2-GP
SMBUS_ISP L ：Isolate Mode 4K7R2J-2-GP Wistron Corporation
R3205 is add for tune 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
equal length
2
SMBUS_ISP ISP_CLK1 ISP_DAT1
Title
Scalar-RTD2586HD
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR

P_1.2V_EDP
PS8625_LCD_PW_EN
23 PS8625_LCD_PW_EN
1
PS8625_BKLT_PWM C205 (U78.47520.5BL) C210 C194 C200
23 PS8625_BKLT_PWM
SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD01U50V2KX-1GP SCD01U50V2KX-1GP
D (U78.10491.4FL) (U) (U) D
2
12,21,23 EDP_BKLTCTL PS8625_BKLT_EN 23
Closed to Closed to
PS8625_INI_SDA_R
PS8625_INI_SCL_R
Closed to
PS8625_BKLT_EN
RTD2136 RTD2136 TXE0-
RTD2136 pin 15 pin 11 pin 43 TXE0+
MODE_CFG1
MODE_CFG0
P_1.2V_EDP
TXE1-
TXE1+
TXE2-
TXE2+
20131027 Madrid SA Charles TXO0-

21,23 TXO0-
Mapping to Scalar LVDS output pin net TXO0+
Colay Pin RTD2136 HOT PLUG (U)
21,23 TXO0+
TXO1-
49
48
47
46
45
44
43
42
41
40
39
38
37
Swap Back to previous version of 1025 21,23 TXO1-
H:RTD2136 ready to take input U38
21,23 TXO1+
TXO1+
TXO2-
GND
BL_EN
TXO0+
TXO1+
TXO2+
MIICSDA
VCCK
L: RTD2136 not ready
MODE_CFG1
MODE_CFG0
MIICSCL
TXO0-
TXO1-
TXO2-
21,23 TXO2-
Mapping eDP-IN pin net 21,23 TXO2+
TXO2+
TXOC-
Colay the serial Capacity 21,23 TXOC-
M
TXOC+
DPD_AUXN_C 21,23 TXOC+
TXO3-
21 DPD_AUXN_C DPD_AUXP_C 21,23 TXO3-
(U) TXO3+
21 DPD_AUXP_C R348 DPD_HPD 21,23 TXO3+
1 36 TXEC-
DPD_LANE0N_C 2 1 TEST_MODE 2 HPD TXOC- 35 TXEC+ TXE0-
21 DPD_LANE0N_C DPD_LANE0P_C DPD_AUXN_C 3 TEST TXOC+ 34 21,23 TXE0-
TXE3- TXE0+
21 DPD_LANE0P_C DPD_LANE1N_C TMDS_3V3 DPD_AUXP_C 4 AUX_N TXO3- 33 21,23 TXE0+
TXE3+ TXE1-
21 DPD_LANE1N_C DPD_LANE1P_C 100KR2J-1-GP AUX_P TXO3+ 21,23 TXE1-
5 32 TXO0- TXE1+
21 DPD_LANE1P_C DPD_HPD DP_V33 TXE0- 21,23 TXE1+
6 31 TXO0+ TXE2-
21 DPD_HPD DPD_LANE0P_C DP_GND TXE0+ 21,23 TXE2-
O
7 30 TXO1- TXE2+
DPD_LANE0N_C 8 LANE0_P TXE1- 29 21,23 TXE2+
TXO1+ TXEC-
DPD_LANE1P_C 9 LANE0_N TXE1+ 28 21,23 TXEC-
TXO2- TXEC+
P_1.2V_EDP DPD_LANE1N_C LANE1_P TXE2- 21,23 TXEC+
Colay power pin net 10
LANE1_N TXE2+
27 TXO2+
21,23 TXE3-
TXE3-
11 26 TXOC- TXE3+
Difference Power source DP_REXT 12 DP_V12 TXEC- 25 TXOC+
21,23 TXE3+
Individual power Capacity DP_REXT TXEC+
PANEL_VCC
SWR_VCCK
1
PWM_OUT
SWR_GND
SWR_VDD
.C
SWR_LX
TMDS_3V3
Mapping to Scalar eDP input pin net
PWM_IN
CIICSDA
CIICSCL
R352 (U)
21 TMDS_3V3
TXE3+
TXE3-
PVCC
12KR2F-L-GP
TMDS_3V3
2
RTD2136R-CGT-GP
Replace
13
14
15
16
17
18
19
20
21
22
23
24
P_3.3V_EDP_VDDIO TXO3-
PS8625_LCD_PW_EN
P_3.3V_EDP_VDDIOX
P_3.3V_EDP_VDDIOX
PS8625_BKLT_PWM
TXO3+
PS8625_ROM2_DAT
PS8625_ROM2_CLK
EDP_BKLTCTL
AM
C C
PS8625_SW
3D3V_S0 3D3V_S5
1
2
L11 R303 R302
3D3V_USB TMDS_3V3 COIL-4D7UH-21-GP R363 4K7R2J-2-GP 4K7R2J-2-GP
(R68.4R71G.10M) 0R0603-PAD-2-GP-U
20131031 Madrid SA Charles AVCC
2
SIO_SMCLK0_2
This two Bead must be (U)
1
1
(U) R292
0R3J-0-U-GP to seperate 3D3V_USB & P3P3V
G
T
P_1.2V_EDP
L4
2
MHC1608S600QBP-GP SIO_SMCLK0_1 S D SIO_SMCLK0

SIO_SMCLK0 20
(U63.00000.00L)
EDP_VDDIO 1 2
Q25 20131209 Madrid SB Charles
1
1
C199 (U78.47520.5BL) C202 C196 SIO_SMCLK0 / SIO_SMDAT0
LA
C172 SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP 2N7002-7F-GP
SCD1U16V2ZY-2GP
change to 3D3V_S5 (follow Florence)
(U78.10491.4FL) (U78.10491.4FL) (84.2N702.J31)
2
2
(U)
3D3V_S0 3D3V_S5
Closed to
RTD2136
1
L5 pin 5 DVCC R240 R239
MHC1608S600QBP-GP P_3.3V_EDP_VDDIOX 4K7R2J-2-GP 4K7R2J-2-GP
(U63.00000.00L)
1 2
2
SIO_SMDAT0_2
1
1
C174 C181 C175 C206 C208
IX
SC10U6D3V3MX-GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP C204
(U78.47520.5BL) (U78.10491.4FL) (U78.10491.4FL) (U78.10491.4FL) (U78.10491.4FL) SC22U6D3V3MX-1-GP
G
2
2
(78.10610.5BL)
SIO_SMDAT0_1 S D SIO_SMDAT0
SIO_SMDAT0 20
Closed to Closed to
RTD2136 RTD2136 Q23
pin 22 pin 18 2N7002-7F-GP
B
.F (84.2N702.J31)
B
Need check power

W
TMDS_3V3
PS8625_INI_SDA_R R347 1 (U)

2012/10/14 David
2 4K7R2J-2-GP
reserved slave address 0x94 & 0x6A
1
R274 R273
W
4K7R2J-2-GP 4K7R2J-2-GP
TMDS_3V3 Form CPU

2
2
R237 1 (R) 2 0R2J-2-GP
MODE_CFG0 SMB_CLK 9,10,13,21,46,54
R345 1 (U) 2 4K7R2J-2-GP R236 1 (R) 2 0R2J-2-GP SMB_DATA 9,10,13,21,46,54
R338 1 (R) 2 4K7R2J-2-GP
PS8625_ROM2_CLK R260 1 2 0R0402-PAD-2-GP SIO_SMCLK0_1 Form EC
PS8625_ROM2_DAT R259 1 2 0R0402-PAD-2-GP SIO_SMDAT0_1
W
20130728 aPisa2 -1A Charles

delete R657, R658 to short trace
TMDS_3V3 2012/10/24 David

Reserve the EEPROM (72.24C64.E01) for SA usage.
MODE_CFG1 R341 1 (R) 2 4K7R2J-2-GP Once the panel is work normally, can remove EEPROM,
and transfer the initial job to EC
R339 1 (U) 2 4K7R2J-2-GP
TMDS_3V3
TMDS_3V3
2013/06/11 RYAN
1

modify net if external EEPROM no use (use EC or BIOS), R754 R755
A
PS8625_BKLT_PWM 1
R353
2 EDP_BKLTCTL 1 R860 2
un-mount R660/R676, mount R899/R662 4K7R2J-2-GP
(U)
4K7R2J-2-GP
(R) U32 (R72.24C64.R01)
A
100KR2J-L-GP 100KR2J-L-GP
2
(R63.10434.1DL) (R63.10434.1DL) 8 1
7 VCC E0 2
PS8625_INI_SCL_R R757 1 (R) 2 0R2J-2-GP PS8625_INI_SCL 6 WC# E1 3
PS8625_INI_SDA_R R756 1 (R) 2 0R2J-2-GP PS8625_INI_SDA 5 SCL E2 4
R774
PS8625_LCD_PW_EN 1 2 PS8625_BKLT_EN 1 R346 2 SDA VSS
100KR2J-L-GP 100KR2J-L-GP
(63.10434.1DL) (63.10434.1DL) M24C64-WMN6TP-1GP
<Core Design>
2013/04/24 Vendor suggest mount R665 R671 _ Ryan
C565
1 2 Wistron Corporation
SC4D7U6D3V2MX-GP-U Taipei Hsien 221, Taiwan, R.O.C.
Title
RTD2136R eDP to LVDS
Custom
Madrid SA
5 4 3 2 1
For UMA EDP_BKLTEN 1 (R) 2 22R2J-2-GP
R869 P3P3V 3D3V_S0 20131126 Madrid SB Charles
SSID = VIDEO Low: Disable
20KR2J-L2-GP
20KR2J-L2-GP
High: Enable PS8625_BKLT_EN
CNVBD1 Co-Layout with CNVBD2 Follow Seattl, Add convertor BD solution
R867
R870
1 (U) 2
LCD_BOOST_VOUT
1
1
R868
22R2J-2-GP CNV_GND 2 1
(S) (R) C764
P3P3V close to CNVBD1 as much as possible. SC100P50V2JN-3-LL-GP
CNV_GND
(78.10134.1FL)
2
(R)
ISEN1
ISEN2
BKLT_EN L61 1 2 BKLT_EN*
ISW
1
(S) MHC1608S601LBP-GP change back to old PN
R464 L60 1 2 BKLT_ADJ*
20KR2J-L2-GP (R) MHC1608S601LBP-GP PWR_ID_2 20140106 Madrid -1A Charles
21
20
19
18
17
16
BKLT_ADJ
1
C629 (R) 20121206 Charles (R) (R) PWR_ID_1 Delete CNVBD1 U59
Fix the shortage issue when
1
PWR_ID_0
Add EMI solution
GND
ISW
VLED
GNDP
ISEN1
ISEN2
2
SC100P50V2JN-3GP
SC100P50V2JN-3GP
C626
(S) C627 C769 (78.47523.5BL) CNV_GND
2
BLON_EN# R459 2 BLON_EN
SC100P50V2JN-3GP
1 G Q91 SC4D7U10V3KX-LL-GP
74.00554.073
2
22R2J-2-GP 2N7002A-7-GP CNV_GND LDR 1 15
(S84.2N702.J31) 1 2 VREF 2 DRV GNDA 14 ISEN3 R1005
OZ554_EMA VREF ISEN3
For Scalar 3 13 ISEN4 10KR2F-2-GP
S
1 2 OZ554_VIN 4 ENA ISEN4 12 ISET 1 2
Low: Enable DCBATOUT_CON OZ554_PWM 5 VIN ISET 11 SSTCMP
LCD ID High: Disable PWM SSTCMP
STATUS
R1004 C770
1
10R2F-L-GP SCD01U50V3KX-4LLGP
SDA
SCL
LPF
PWR_ID0 (78.10324.2BL) R1002 CNV_GND
RT
20 PWR_ID0 PWR_ID1 100R2F-L1-GP-U
20 PWR_ID1
2
PWR_ID2 OZ554LN-GP
20 PWR_ID2
6
7
STATUS 8
9
10
2
BKLT_EN P3P3V SMBCLK2_SIO
SSTCMP_1
20 BKLT_EN SMBDAT2_SIO
LPF
RT
modify power from 3D3V_S5 to P3P3V CNV_GND
1
R461 (S)
CONVERTOR SMB 1KR2J-1-GP R1007 C765(78.47422.5BL)
(S64.10005.6DL) 1KR2F-3-GP SCD47U25V3KX-1LLGP
20 SMBCLK2_SIO
2
1
1
R456
20 SMBDAT2_SIO
1
SCALAR_BKLT_CTRL 2 1 100R2J-2-GP C767(R) R1003 CNV_GND
SCD1U25V2KX-LL-GP 100KR2F-L1-GP
(U64.10005.6DL)
2
R457
+19V_S5_INV Power
2
PS8625_BKLT_PWM 2 1 100R2J-2-GP
M
C768(R) C766 (78.10422.5FL)
SCD1U25V2KX-LL-GP SCD1U25V2KX-LL-GP
(R)
R455 68.00216.191
EDP_BKLTCTL 2 1 100R2J-2-GP Z=80 ohm,Rdc=0.02 ohm
I=5A ,0805 Roger modify 2013/2/4
12 EDP_VDDEN
DCBATOUT
NB team cost review CNV_GND ground moat CNV_GND
R1006
was not necessary 0R1206-PAD-1-GP
O
12 EDP_BKLTEN
F7 1 2
1 2 DCBATOUT_CON
12,21,22 EDP_BKLTCTL
2013/03/07 POLYSW-1D1A24V-GP-U
CNV_GND
Add Ctrl trace of eDP _Ryan
.C
Michael 2012/02/13
Colay Pin add F4901 in SB R1010 R1011
10KR2F-2-GP 10KR2F-2-GP
OZ554_PWM 1 2 BKLT_ADJ OZ554_EMA 1 2 BKLT_EN
LVDS from Scalar
TXO0-
21,22 TXO0-
TXO0+
21,22 TXO0+
AM
TXO1-
21,22 TXO1-
1
TXO1+
21,22 TXO1+
1
TXO2- R1013 R1012 C775(78.10324.2BL)
21,22 TXO2- 300KR2F-GP 300KR2F-GP SCD01U50V3KX-4LLGP
TXO2+ C323(78.10224.2BL)
2012/06/22 SA
21,22 TXO2+
CNVBD1 Co-Layout with CNVBD2
2
TXOC- SC1000P50V3KX-LL-GP
21,22 TXOC-
2
TXOC+
21,22 TXOC+
2
TXO3-
21,22 TXO3-
TXO3+
Change LVDS connector
21,22 TXO3+
21,22 TXE0-
TXE0-
TXE0+
21,22
21,22
TXE0+
TXE1-
TXE1-
TXE1+ ACES-CONN60G-1-GP
Follow Seattl, Add convertor BD solution CNV_GND CNV_GND
21,22 TXE1+ 30A 30B
TXE2- TXO0-
21,22 TXE2-
TXE2+ TXO0+ 29A 29B 20131213 Madrid SB Charles
21,22 TXE2+
TXEC- TXO1- 28A 28B modify L66 (68.33010.20J)
21,22 TXEC-
T
TXEC+ TXO1+ 27A 27B Q96 downsize Main : 084.PA010.0037 (Niko)
21,22 TXEC+
TXE3- TXO2- 26A 26B CNVBD2
21,22 TXE3- 25A 25B 14
2nd : 084.04286.0037
TXE3+ TXO2+
21,22 TXE3+
24A 24B
TXOC- 23A 23B ISEN1 R1021 2 0R2J-2-GP1 RTN1 12 19V boost to 50V 1st source: 83.3R010.08M
TXOC+ 22A 22B ISEN2 R1022 2 0R2J-2-GP1 RTN2 11
TXO3- 21A 21B ISEN3 1 R1018 2 LCD_BOOST_VOUT 10 DCBATOUT_CON L66 IND-33UH-65-GP D30
2rd source: 83.3R010.A8M
LA
TXO3+ 20A 20B 0R2J-2-GP 9
SCALAR_BKLT_CTRL TXE0- 19A 19B BKLT_EN* 8 1 2 LX A K LCD_BOOST_VOUT
21 SCALAR_BKLT_CTRL TXE0+ 18A 18B BKLT_ADJ* 7
SCALAR_VDD_EN 17A 17B (R) 1 R1017 2 0R2J-2-GP PWR_ID_2 6 C772 C776 C779 C771 C774
21 SCALAR_VDD_EN
1
PWR_ID_1
(78.10525.22L)
(78.10525.22L)
(78.10525.22L)
(78.10525.22L)
SC1U100V6KX-LL-GP
SC1U100V6KX-LL-GP
SC1U100V6KX-LL-GP
SC1U100V6KX-LL-GP
SC1U100V6KX-LL-GP
TXE1- 16A 16B ISEN4 1 R1023 2 (R) 1 R1019 2 0R2J-2-GP 5 BX310-GP (R)
TXE1+ 15A 15B 0R2J-2-GP (R) 1 R1020 2 0R2J-2-GP PWR_ID_0 4
1
BLON_EN# 14A 14B 3 (83.3R010.C8M)
21 BLON_EN#
2
TXE2- 13A 13B DCBATOUT_CON 2 C777 C778
(78.10622.52L)
(78.10622.52L)
SC10U25V6KX-1-LL-GP
SC10U25V6KX-1-LL-GP
TXE2+ 12A 12B Q96
2
SIO_BKLT_CTRL TXEC- 11A 11B PWR_ID0 1 R1024 2 0R2J-2-GP 1
SIO_BKLT_CTRL
8
7
6
5
TXEC+ 10A 10B PWR_ID1 1 R1025 2 0R2J-2-GP PA010BV-GP
EC LCD ID GPIO PWR_ID2
D
D
D
D
TXE3- 9A 9B 1 R1027 2 0R2J-2-GP 13
TXE3+ 8A 8B
7A 7B 3D3V_A
IX
ACES-CON12-28-GP R1014
1
2012/08/23_aPisa_SA 6A 6B 1 R1026 210KR2J-3-GP 0R5J-5-GP
5A 5B 1 R1028 210KR2J-3-GP R1009 (R) 4 LDR_1 1 2 LDR
G
4A 4B 1 R1029 210KR2J-3-GP 1R5J-2-GP
S
S
S
3A 3B VCC5_PANEL
1
2
3
2A 2B
LVDS from Scalar or transmmiter
2
20131202 Madrid SB Charles R1015
1A 1B 200R5J-GP
Modify Pull High to 3D3V_A ISW_1 1 2 ISW
1
C177 C178
LVDS1 (R)
.F
SC1U10V2KX-1GP
SCD1U16V2ZY-2GP
20131006 Madrid SA Charles SNB

2
Change Net as Scalar LVDS out (20.K0631.030)

because colay RTD2486 & RTD2136
1
PS8625_BKLT_PWM
22 PS8625_BKLT_PWM
1
C773(R) R1016 R1008
SC330P100V3JN-GP
PS8625_LCD_PW_EN
22 PS8625_LCD_PW_EN
2
W
D33R6F-GP D33R6F-GP
PS8625_BKLT_EN
22 PS8625_BKLT_EN
2
5V_CHARGER
W
U35
1 D D 6
L53
2 D D 5
1
3 G S 4 V_5_LCD1 1 2 V_5_LCD2
C566 MHC1608S800QBP-GP
DCBATOUT Q24 SC1U10V2KX-1GP AO6402A-GP
2
PMBS3906-GP Main: 84.06402.B3D

R286 (84.T3906.E11) Alt: 84.00655.B3D R307 Cable Spec
1 2 LCD_5V_EN1 2 3 LCD_5V_EN 470R2J-2-GP
47KR2J-2-GP (64.51005.6DL)
W 1
2
1
R287 R291 R290 Panel Model ID0 ID1 ID2 Vout

5V_S5_LCD_DOWN
1
1 2 LCD_5V_EN2 47KR2J-2-GP 1KR2J-1-GP C173

2013/03/07 Co-lay_Ryan 330KR2J-L1-GP SCD1U25V2KX-2-GP High: Enable
2
(R) change 20131025

Low: Disable
2
R773 AUO 3,4 Vout

1
EDP_VDDEN 1 2
M215HTN01.1 0 0 0 1,2,5,6 RTN
R304
LCD_5V_EN4
4K7R2J-2-GP 100KR2J-1-GP Q30

D
2N7002A-7-GP
(U) LG 3,4 Vout
2
R294 0 0 1
PS8625_LCD_PW_EN 1 2 LCD_5V_EN3 G LM215WF4-TLG1 1,6 RTN
4K7R2J-2-GP (84.2N702.J31)
CMO 3,4 Vout
S
(S) 0 1 0
R301 M200FGE-L20 1,2,5,6 RTN
6
SCALAR_VDD_EN 1 2 SCALAR_VDD_EN1
Q26
2
4K7R2J-2-GP 2N7002KDW-GP Samsung 1 Vout

R293 VCC5_PANEL
LTM200KT10 1 0 0 2,3,4 RTN
10KR2J-3-GP (75.27002.F7C)
1
(63.10434.1DL)
de-rating0822 V_5_LCD2 <Core Design>
1
AUO 3,4 Vout

M240HTN01.2 1 1 0 1,2,5,6 RTN Wistron Corporation
CMI 3,4 Vout
1 1 1 Title
M236HGE-L20 1,2,5,6 RTN
LCD CONN / CVR
Custom
Madrid SA
5 4 3 2 1

(MS/SD/MMC)
follow Florance
modify USB port follow Superb (66.R0036.04L)
(63.R0034.1DL)
CR_SP5 R803 2 1 22R2J-2-GP SP5
FILTER-4P-137-GP
11 USB_PN8 USB_PN8 4 3 USB_PN8_R
11 USB_PP8
1
USB_PP8 1 2 USB_PP8_R (R) C577
D D
SC5P50V2CN-2GP
2
L52
20131027 CM
SP10
SP9
SP7
20131028 Madrid SA Charles ;
Swap
24
23
22
21
20
19
U36
NC#24
SP10
SP9
SP8
SP7
SP6
M
5V_S5
C567 2 1 SC1U10V3ZY-6GP V_1P8_CR 1 18 CR_SP5
R767 2 1 6K2R2F-GP CR_REF_C 2 AV18 SP5 17
USB_PN8_R 3 RREF SP4 16 CR_SDREG C578 1 2 SC1U10V3ZY-6GP
USB_PP8_R 4 DM SDREG 15
O
C559 1 2 SCD1U16V2ZY-2GP CR_A3V3 5 DP MS_INS# 14
6 A3V3 SP3 13 SP2
5V_IN SP2
CARD_3V3
SD_DAT1
SD_CD#
.C
D3V3
GPIO
1
SP1
C560 25
SCD1U16V2ZY-2GP
C558 GND
C C
SC4D7U6D3V3KX-GP
RTS5143-GRT-GP
7
8
9
10
11
12
AM CR_D3V3
SD_DATA1
SD_CD#
SP1
V_3_CARD
C579 1 2 SCD1U16V2ZY-2GP
2IN1 (SD/MMC) Combo Net
T
SP1 SD_WP
LA
SP2 SD_DATA0
20130910 Ryan
SP5 SD_CLK
IX
B B
V_3_CARD .F 2IN1 CONN (SD/MMC) SP7 SD_CMD
CRS1
20MILS 4 10 SD_CD# SP9 SD_DATA3
VDD CARD_DETECT 11 SD_WP
WRITE_PROTECT SP10 SD_DATA2
1
SD_DATA0 7 NP1
W
C216 C218 C580 R364 C217 SD_DATA1 8 DAT0 NP1 NP2
DAT1 NP2
100KR2F-L1-GP
SD_DATA2 9
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
SD_DATA3 1 DAT2 3
SCD1U16V2ZY-2GP
(R) (R) CD/DAT3 VSS 6

2
VSS
SD_CMD
W
2 12
SD_CLK 5 CMD GND 13
CLK GND
CARDBUS11P-SKT-GP
<Variant Name>
(62.10051.H51)
W
A 20131027 CM A
Wistron Corporation
Title
RTS5143 (CARD READER)

B
Madrid SA
5 4 3 2 1
5 4 3 2 1
AspireLink USB 3.0

Micro-B
WH90 (L) Place caps close to PCIE port Conector ASPK1 (L)
20140114 Madrid 1A Charles EECS# 53
EEWRDATA 51 EE_CS# 13 PCIE_RXP4_C (L)C7021 2SCD1U10V2KX-5GP PCIE_RXP4 ASPK_VBUS 1 4
change to 8.2P 0402 EE_DI PCIEX_PETP VBUS ID
2
XTAL-30MHZ-4-GP EERDDATA 55 14 PCIE_RXN4_C (L)C7031 2SCD1U10V2KX-5GP PCIE_RXN4
EE_DO PCIEX_PETN
1
1 2 EECLK 54 9 PCIE_TXP4 (L)R995 6 USBA30_TN1_RO_CL
(L) C705(L) EE_SK PCIEX_PERP 10 PCIE_TXN4 20KR2F-L-GP HSDmL 2 MICB_SSTX- 7 USBA30_TP1_RO_CL
11 PCIE_RXN4 PCIEX_PERN D- MICB_SSTX+
2
C704 4 3 SC8P250V2CC-GP XIN 48 (L) 20131105 Madrid SB Charles D29 HSDpL 3
11 PCIE_RXP4
2
SC8P250V2CC-GP XOUT 49 XTAL_IN 77 USBA30_TP1 SCD1U10V2KX-5GP
1 2C706USBA30_TP1_RI D+ 9 USBA30_RN1_R*L
11 PCIE_TXN4 modify Net nameASPK_VBUS3V
1
(L) XTAL_OUT USB_TXP 76 USBA30_TN1 1 2 USBA30_TN1_RI 11 MICB_SSRX- 10 USBA30_RP1_R*L
11 PCIE_TXP4 CLK_PCIE_4_AspireLink USB_TXM USBA30_RP1 SCD1U10V2KX-5GP 11 MICB_SSRX+
(L75.YSE05.077)
AZ5125-01H-R7G-GP
X6 36 81 C707 12
PCIEX_REFCLKP USB_RXP 12
1
CLK_PCIE_4_AspireLink# USBA30_RN1
connector
Close to
37 80 (L) Place caps close to WH90 USB3_TX port 13
PCIEX_REFCLKN USB_RXM 14 13 8
14 CLK_PCIE_4_AspireLink# PLTRST_AspireLink# 14 GND_DRAIN
24 7 HSDp (L) R997 15
14 CLK_PCIE_4_AspireLink PCIEX_PERST# USB_DP 15
PWRONRST# 21 5 HSDm 33KR2F-GP 16 5
PLTRST_AspireLink# PWRON_RST# USB_DM 2 URREF 16 GND
20 PLTRST_AspireLink# USB_RREF
1
1
(L)R941 2
4K7R2J-2-GP
TESTMODE0 44 88 ASPK_VBUS3V
D STRAP_TESTMODE0 USB_VBUS D
1
(L)R943 2
4K7R2J-2-GP
TESTMODE1 45 SKT-USB16-3-GP-U
STRAP_TESTMODE1
1
1
(L)R944 2
4K7R2J-2-GP
TESTMODE2 46 30
1
(L)R945 2
4K7R2J-2-GP
TESTMODE3 47 STRAP_TESTMODE2 RESERVED#30 31 R946(L)
AVCC_3D3VA STRAP_TESTMODE3 RESERVED#31 1K6R2F-GP
AVCC_3D3VA 20131129 Madrid SB Charles 22 28
65 STRAP_DEBUG_SEL# LANE_GOOD# 20 AVCC_3D3VA
modify reserve pull down
2
56 STRAP_PLL_BYPASS# GPIO1 83
default pull low STRAP_SERDES_MODE_EN# GPIO2
1
19 27 AVCC_3D3VA AVCC_3D3VA
RC_MODE_Strap 57 STRAP_PROBE_MODE# GPIO3
R947 (R)
0R2J-2-GP 58 STRAP_RC_MODE 23 Serial
SCD1U10V2KX-5GP
0R2J-2-GP STRAP_PORTCFG MFG_AMC EEPROM
2
1 2 LEGACY 66 26
STRAP_LEGACY MFG_TAPEN (Optional)
2
R948 (R) 64 84 C708(L) R949 (L)
2
RC_MODE_Strap 38 STRAP_SSC_CENTER# MFG_TMC1 87 R955 (L)

STRAP_UPCFG_TIMER_EN# MFG_TMC2 10KR2F-2-GP
10KR2F-2-GP U48 (L)
1
2
68 33 Alink_pin33 R950(R) 1 2 0R2J-2-GP

AVCC_1V
1
R999 PROCMON RESERVED#33 35 Alink_pin35 R951(L) 1 2 2KR2F-3-GP EECS# 1 8
1
1
(L)R952 2
4K7R2J-2-GP PCIE_WAKE#_Alink 86 RESERVED#35 2 R953 1EERDDATA 2 CS# VCC 7
0R2J-2-GP AVCC_3D3VA WAKE# SO/SIO1 HOLD#
(L) 61 15 AVCC_1V EEWP# 3 6 EECLK
1 2 CPU_RXD_Alink 60 CPU_TXD PCIEX_VDDD0_P0 71 4 WP# SCLK 5
M
AVCC_3D3VA (L)R954 10KR2F-2-GP 10KR2F-2-GP EEWRDATA
CPU_RXD PCIEX_VDDD0_P2 GND SI/SIO0
1
2
12 (L)
18 PCIEX_VDDD1_P0 75 R956 (L)
3D3V_S5 DVCC_1V VAUX_CORE USB_VDDD0
72 78 10KR2F-2-GP MX25L1006EMI-10G-GP
VAUX_CORE USB_VDDD1
25 17
3D3V_S0 VAUX_IO PCIEX_VDDA_P0 AVCC_3D3VA
1
34 69
85 VDD_IO PCIEX_VDDA_P2 73
VAUX_IO USB_VDDA
1
1
USB_AVDD33
O
R985 DVCC_1V 39
41 VDD_CORE 42
10KR2J-3-GP VDD_CORE PLL_AVDD AVCC_1V
(R) 52 20140106 Madrid -1A Charles COIL-50OHM-GP
62 VDD_CORE 43 Resreve EMI solution
2
67 VDD_CORE PLL_AGND 3 USBA30_TN1_RO_C 1 2 USBA30_TN1_RO_CL

PLTRST_AspireLink# 1 2 R984 PWRONRST# VDD_CORE USB_AVSS 4
40 USB_PVSS 16 FILTER-4P-137-GP USBA30_TP1_RO_C 4 3 USBA30_TP1_RO_CL
3D3V_S0 VDD_IO PCIEX_VSSA_P0
0R2J-2-GP 50 70 HSDm 3 4 HSDmL
59 VDD_IO PCIEX_VSSA_P2 74 (L66.R0036.04L)
.C
(L) VDD_IO USB_VSSA TR24
2
63 11 HSDp 2 1 HSDpL
C755 6 VDD_IO PCIEX_VSSD0_P0 8
USB_VDD33 PCIEX_VSSD1_P0 79 TR23
SCD1U10V2KX-5GP L67 (L66.R0036.04L) (L66.R0036.04L)
USB_VSSD0
1
29 82 USBA30_RP1_R* 4 3 USBA30_RP1_R*L
(R) 32 VSS USB_VSSD1
VSS 89 USBA30_RN1_R* 1 2 USBA30_RN1_R*L
GND
WH90-GP
COIL-50OHM-GP
AM
C C
D32 (R)
D33 (R)
3D3V_S0 USBA30_TN1_RO_CL 1
USBA30_TP1_RO_CL 2 3 HSDmL 1
USBA30_RN1_R*L 4 8 HSDpL 2 3
USBA30_RP1_R*L 5 4 8
1
C732 C733 5
(L) (L) USB3.0 Redriver 6 9
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
7 10 6 9
A channel is RX , B channel is TX
2
7 10
SP3010-04UTG-GP
SP3010-04UTG-GP
3D3V_S0
USBA30_TP1_RI USBA30_TP1_RO
T
U50 (R)
USBA30_TN1_RI USBA30_TN1_RO
1 9 USBA30_TP1_RI
13 VDD B_INP 8 USBA30_TN1_RI
USBA30_RP1_R* USBA30_RP1_RO VDD B_INN 3D3V_S0 AVCC_3D3VA
USBA30_RN1_R* USBA30_RN1_RO
USBA30_RP1_R* B_OUTP
22 USBA30_TP1_RO
USBA30_TN1_RO USBA30_TP1_RO USBA30_TP1_RO_C
102mA 20131121 Madrid SB Charles
modify symblo to fix footprint mismatch
19 23 1 2 1 2
LA
USBA30_RN1_R* 20 A_INP B_OUTN C757 SCD1U10V2KX-5GP R988(L) 0R2J-2-GP
A_INN
1
3 B_DE0 C725 C739 C726 C740 C729 (L) C738 C735 C758
B_DE0/I2C_ADDR0 (L63.R0034.1DL)
USBA30_RP1 USBA30_RP1_RO USBA30_RP1_RO B_DE1
SC10U6D3V3MX-GP
1 2 12 6 (L) (L) (L) (L) (L) (L) (L)
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C713 SCD1U10V2KX-5GP USBA30_RN1_RO 11 A_OUTP B_DE1/NC#6 2 B_EQ0 USBA30_TN1_RO 1 2 USBA30_TN1_RO_C 20131105 Madrid SA Charles
2
A_OUTN B_EQ0/NC#2 4 B_EQ1 C756 SCD1U10V2KX-5GP
(L63.R0034.1DL)
A_DE0 B_EQ1/I2C_ADDR1 reserve 1V power
16
A_DE1 A_DE0/SCL_CTL (L63.R0034.1DL) Cancel (U49)GS7136 , Replace by APL5930
18 7 REXT
A_DE1/NC#18 REXT
1
USBA30_RN1 1 2 USBA30_RN1_RO A_EQ0 17 14 TEST Place caps close to USB3.0 Redriver RX port
C723 SCD1U10V2KX-5GP A_EQ1 15 A_EQ0/NC#17 TEST/NC#14 R963(L)
A_EQ1/SDA_CTL 4K99R2F-L-GP
(L63.R0034.1DL)
PD# 5 10
Place caps close to USB3.0 Redriver RX port PD# GND 21
500mA
2
GND
1
24 25 PCH_1D05V DVCC_1V AVCC_1V
IX
(L)R965 I2C_EN GND
4K7R2J-2-GP R957 1 2 1 2
PS8713BTQFN24GTR2-A0-1-GP (L) R986(L) 0R2J-2-GP
modify symblo to fix footprint mismatch

UnMount for SB 0R3J-0-U-GP
2
1
DVCC_1V_LDO
change C759 to 4.7uF 78.47520.5BL

Charles 20131019 (L) C714 C717 C720 C719 C721 C722 C715 (L)C759 C761 C760 C762
SC10U6D3V3MX-GP
SC4D7U6D3V3KX-GP
(L) (L) (L) (L) (L) (L) (L) (L) (L)
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
2
2
R987 1 2
(R) 0R3J-0-U-GP
3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0 3D3V_S0

3D3V_S0
.F B
1
R962(L)
1
4K7R2J-2-GP
R966(L) R967(L) R968(L) R969(L) R970(L) R971(L) R972(L) R973(L)
4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP
2
W
TEST
2
A_EQ1 A_EQ0 B_EQ1 B_EQ0 A_DE1 A_DE0 B_DE1 B_DE0

1
3D3V_S0
R974(L) R975(L) R976(L) R977(L) R978(L) R979(L) R980(L) R981(L)
4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP 4K7R2J-2-GP
1
R964(L)
2
4K7R2J-2-GP
W 2
REXT
20140104 Madrid 1A Charles

PCH_1D05V is ok for AspireLink
Power Solution (Reserve) 1V_S0 unmount 1V_S0 solution,
W
follow Seattle 11/18 Jimmy SWAP PR583/PR584

check if PCH_1D05V is ok for AspireLink, unmount All when DVT
PR583 (R)
PD=(1.5-1.0)*0.5=0.25 25K5R2F-GP
PR583 change to 64.25525.6DL and PR584 change to 64.10035.6DL
1 2 7175_FB_M
R1
Iomax=0.5A
Vo(cal.)=1.5096V
PC575 2 1
DVCC_1V_LDO 1D0V (R) SC100P50V2JN-3GP
Vo=0.8*(1+(R1/R2))
1
R2 PR584 (R)
1D5V_1v_S0
100KR2F-L1-GP 11/12 Derek change to EN from SLP_S3_N for Aspire Link S0 power
A PU12 (R) A
2
PR582 (R) 1 9 PR585 (R) 2012/10/19 David

0R0603-PAD 2 GND VIN#9 8 1V_S0_EN 2 1
FB EN PM_SLP_S3# 13,20,21,35,36,38,40,41 Removed 1D5V_S5_GD
2 1 3 7 1V_S0_GD 0R0402-PAD 2 PR586 1
PC573 (R) PC574 (R) 4 VOUT#3 POK 6 (R)
VOUT#4 VCNTL 5V_S5
1
5
SC1U10V2KX-1GP
SC1U10V3ZY-6GP SC10U6D3V3MX-GP 10KR2F-2-GP

VIN#5
1
2
APL5930KAI-TRG-1-GP (R) PC576

1D5V_S3 1D5V_1v_S0 <Core Design>
2

1 2 modify symbol to APL5930 Wistron Corporation
1
0R0805-PAD 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

PR587 (R)PC577 Taipei Hsien 221, Taiwan, R.O.C.
(R) SC10U6D3V3MX-GP
2
Title
AspireLink
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
EMI_USB 20131016 Madrid SA charles

modify change 20131025
USB30_TP0 C541 1 2SCD1U25V2KX-2-GP USB30_TP0_CL USB30_TP1 C263 1 2SCD1U25V2KX-2-GP USB30_TP1_CL
USB30_TN0 C545 1 2SCD1U25V2KX-2-GP USB30_TN0_CL USB30_TN1 C261 1 2SCD1U25V2KX-2-GP USB30_TN1_CL

(66.R0036.04L)
USB2.0 COIL-50OHM-GP TR11
(66.R0036.04L)
11 USB_PN1 USB30_TP0_CL USB30_TP0_C USB30_TP1_CL USB30_TP1_C
D
1 2 4 3 D
11 USB_PP1
11 USB_PN0 USB30_TN0_CL 4 3 USB30_TN0_C USB30_TN1_CL 1 2 USB30_TN1_C
11 USB_PP0
(66.R0036.04L)
TR21 COIL-50OHM-GP
USB3.0 20131027 CM
COIL-50OHM-GP TR12
(66.R0036.04L)
11 USB30_RN1 USB30_RP0 1 2 USB30_RP0_C USB30_RP1 4 3 USB30_RP1_C
11 USB30_RP1
11 USB30_TN1 USB30_RN0 4 3 USB30_RN0_C USB30_RN1 1 2 USB30_RN1_C
11 USB30_TP1
(66.R0036.04L)
11 USB30_RN0 TR22 COIL-50OHM-GP
11 USB30_RP0
11 USB30_TP0
M
11 USB30_TN0 L51 L18
USB_PN0 2 1 USB_PN0_C USB_PN1 2 1 USB_PN1_C
USB_PP0 3 4 USB_PP0_C USB_PP1 3 4 USB_PP1_C
FILTER-4P-137-GP 20131028 Madrid SA Charles ; FILTER-4P-137-GP
O
change 20131025 change 20131025
Swap
Modify the USB2R1 as USB3R1
ESD_USB
.C
REAR USB3.0
C C

Modify the USB2R1 as USB3R1
AM
USB_PWR_3
USB3R1
USB_PWR_3
1 5 USB30_RN0_C D21 (R) D22 (R)
VBUS STDA_SSR- 6 USB30_RP0_C
STDA_SSR+ USB30_RN0_C 1 USB_PP0_C 1 6 USB_PN0_C
USB_PN0_C 2 8 USB30_TN0_C USB30_RP0_C 2 3 I/O1 I/O4
USB_PP0_C 3 D- STDA_SST- 9 USB30_TP0_C USB30_TN0_C 4 8 2 5
D+ STDA_SST+ USB30_TP0_C 5 GND VDD
T
10 3 4
11 10 4 6 9 I/O2 I/O3
12 11 GND 7 10
13 12 7 PJSRV05W-4W6-R1-00001-GP
13 GND_DRAIN
LA
SP3010-04UTG-GP
SKT-USB13-27-GP
(22.10341.H31)
MainSource0822
B B
IX
D10 (R) D28 (R)
Side IO USB3 connector modify for madrid 0926 USB30_RN1_C

USB30_RP1_C
1
2 3
USB_PP1_C
USB_PN1_C
1
2 3
delet R390
follow london2 USB30_TN1_C
USB30_TP1_C
4
5
8 4
5
8
USB_PWR_2
USB3S2
.F 6
7
9
10
6
7
9
10
10
USB30_TP1_C 9 SP3010-04UTG-GP SP3010-04UTG-GP
1
W
USB30_TN1_C 8
USB_PN1_C 2
7
USB_PP1_C 3
USB30_RP1_C 6
4
1
USB30_RN1_C 5
W
TC3 11
E220U16VM-25-GP
2
20131127 Madrid SB Charles SKT-USB11-37-GP

TC3 change to 09.2271D.X8L
A
201311025
(22.10254.791)
USB Power Arrangement A
09.2271D.0YL
201311025
SM016M221E07T014P25R
09.2271D.0YL USB_PWR_1:USB3S1+USBRF1 = 1400mA (原USB30_VCCA)
W
--> 7mm height

SM016M221E07T014P25R
--> 7mm height USB_PWR_2:SD+ USB3S2 + USB2R3 = 1900mA
USB_PWR_3: USB2R2+USB2R1+Touch = 1400mA Title
<Title>

CustomMadrid SA

5 4 3 2 1
5 4 3 2 1
near to CAM1 two side
SSID =USB2.0 DCBATOUT

WEB CAM [ USB Port11 ] USB Power Arrangement
USB_PWR_1:USB3S1+USBRF1 = 1400mA (原USB30_VCCA)
1
USB_PWR_2:SD+ USB3S2 + USB2R3 = 1900mA
SC100P50V2JN-3GP
EC22
SC100P50V2JN-3GP
EC20
USB_PN11_C
USB_PWR_3: USB2R2+USB2R1+Touch = 1400mA
2
1
CAM1
9 20131013 Madrid SA Charles R1 VCC5_USB_23; VCC5_USB_45
1 (R) 300R2J-4-GP
USB_PP11_C
modify WebCAM/DMIC follow flaoance
D 2 D
2
3 USB_PN11_C USB_PN11_R
4
VCC5_CAM USB20 Pwr SW1
1
5 (63.00000.00L) (R)
6 DMIC_CLK_D R3 1 2 DMIC_CLK C3
7 DMIC_CLK 18 SC10P50V2JN-4GP
MHC1608S601LBP-GP
2
8 DMIC_DATA_D R2 1 2 DMIC_DATA
10 DMIC_DATA 18
MHC1608S601LBP-GP
JWT-CON8-7-GP
(63.00000.00L)
Why ?? 20130519 Reserve _Ryan USB20 Pwr SW2
(20.F0765.008)
3D3V_S5
USB_PWR_2
DMIC Connector
1
close to CAM1 as much as possible. U14
R1038 5V_CHARGER
10KR2J-3-GP 1 8
VCC5_CAM 2 GND VOUT#8 7
2012/09/07 3 VIN VOUT#7 6
2
VIN VOUT#6
20131028 Madrid SA Charles Modify DMICN1 to 1R5P 20,27 USB_PWR_EUP
USB_PWR_EUP 1 R1037 2 0R2J-2-GP 4
EN OC#
5
M
cancel 5V PWR reserve D17 C610
1
USB_EN (R) 1 R1032 2 USB_EN_1
Delete L42 ,R532 27,31 USB_EN
0R2J-2-GP UP7534PRA8-20-GP
SCD1U16V2ZY-2GP
1
1
C351 C350 DMIC_CLK 1 1 2 (74.02311.A79) (R)
3D3V_S5
2
20131121 Madrid SB delet USB_PN2/PP2 20131204 Madrid SB Charles MainSource0822 TC9
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
3 Colay USB pwr2 control R394 E220U10VM-21-GP
11 USB_PN3
2
20131128 Madrid SB Charles 10KR2J-3-GP (R09.2271D.X8L)
11 USB_PP3 DMIC_DATA 2 USB_OC_23_N
3D3V_USB NB team cost review
11 USB_PN4
O
11 USB_PP4 L43
1
F8 20131121 Madrid SB Charles
1 2 VCC5_CAM_bL 1 2 AZ5125-02S-R7G-GP C259 unmount TC9 ; confirm to delet before DVT
SCD1U16V2ZY-2GP
11 USB_PN5
2
C C
11 USB_PP5 POLYSW-1D1A6V-9-GP-U MHC1608S601LBP-GP
11 USB_PN10 20131022 Madrid SA Charles Delete DMIC1
.C
11 USB_PP10
11 USB_PN11 webcam use 3v ; Add 1.1A Fuse
11 USB_PP11
11 USB_OC_23_N 3D3V_S5
USB20 Pwr SW3
11 USB_OC_45_N Supply 4 USB2.0 USB_PWR_3
TOUCH Connector
1
AM
U15
R1045
10KR2J-3-GP 5V_CHARGER 1 8
VCC5_TOU 2 GND VOUT#8 7
Share USB20 Pwr SW3 3 VIN VOUT#7 6
2
TOUCH1 USB_PWR_EUP 1 R1044 2 0R2J-2-GP 4 VIN VOUT#6 5
7 20,27 USB_PWR_EUP EN OC# C265
1
1 USB_EN (R) 1 R1043 2 USB_EN_2
VCC5_TOU 27,31 USB_EN
20131027 CM USB_PWR_3 0R2J-2-GP UP7534PRA8-20-GP
SCD1U16V2ZY-2GP
1
USB_PN10_C 2 1 2 (74.02311.A79) (R)
R410 3D3V_S5
2
L16 USB_PP10_C 3 20131209 Madrid SB Charles MainSource0822 TC10
1 2 4 Colay USB pwr2 control R401 E220U10VM-21-GP
(66.R0036.04L)
2
5 10KR2J-3-GP (09.2271D.X8L)
FILTER-4P-137-GP 2010/06/09 6 USB_OC_45_N
S3 Resume issue 0R5J-5-GP
T
1
USB_PN10 4 3 USB_PN10_C C266 C269
1
ACES-CON5-22-GP
SCD1U16V2ZY-2GP
USB_PP10 USB_PP10_C
SC10U10V5ZY-1GP
1 2 C264
2
SCD1U16V2ZY-2GP
2
L1 modify Touch1 as right angle
LA
B B
FILTER-4P-137-GP
USB_PN11 4 3 USB_PN11_C
USB_PP11 1 2 USB_PP11_C
USB_PN3 1 2 USB_PN3_C
20131121 Madrid SB Charles REAR USB2.0 RF Dongle USB2.0
IX
FILTER-4P-137-GP
delet the USB2R1 Modify to USB3R1 USB2R2
USB_PWR_2
5
USB2R3
USB_PWR_2 USBRF1
L14 USB_PWR_3 5 1 6
USB_PWR_3 1 1
USB_PN2 USB_PN2_C USB_PN4_C 2
USB_PN3_C 2 USB_PP4_C 3 USB_PN5_C 2
USB_PP2 USB_PP2_C USB_PN2_C USB_PP3_C 3 2010/06/09 4 USB_PP5_C 3
USB_PP2_C 4 S3 Resume issue 6 4
.F 6
SKT-USB6-127-GP
5
SKT-USB6-127-GP (22.10339.V61) SKT-USB6-44-GP

20131028 Madrid SA Charles ; (22.10339.V61) MainSource0822 (22.10254.211)
Swap MainSource0822 Madrid
PC3 MainSource1106
1
SC10U10V5KX-2GP
L15
USB_PN4 1 2 USB_PN4_C MainSource0822
W
2
USB_PP4 4 3 USB_PP4_C (78.10693.41L)
FILTER-4P-137-GP
13/11/02 Add restore USB2R1--Kai
A A
L2 D8 D9 D1
USB_PN5 1 2 USB_PN5_C <Core Design>
1 6 USB_PN4_C 1 6 USB_PP4_C 1 6
W
USB_PWR_3 USB_PWR_2 USB_PWR_2

2 5 2 5 2 5 Wistron Corporation
FILTER-4P-137-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
USB_PP3_C 3 4 USB_PN3_C 3 4 USB_PP5_C 3 4 USB_PN5_C Taipei Hsien 221, Taiwan, R.O.C.
1
1
(R) (R) (R)
Title
IP4223CZ6-1-GP IP4223CZ6-1-GP IP4223CZ6-1-GP Rear USB/TOU/Dongle/Web Cam
2
2
(R) (R) (R)
C614 C258 C4 Size Document Number Rev
W
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP Custom

Madrid SA
5 4 3 2 1
5 4 3 2 1
LAN_XTAL1 LAN_EESK R383 1 2 300R2J-4-GP LINK*_ACTIVITY_L

LAN_XTAL2 SPEED_100*_L
LAN_EEDO R382 2 1 0R0402-PAD-2-GP SPEED_1000*_L
V_3P3_LAN LAN_RSET +1.05V_LAN
R387 1 2 2K49R2F-GP Mount for RTL8111G ONLY
Colse to the AVDD33 pin location
R378 1 2 0R5J-5-GP
1
(R)
1
D C215 change 20131216 C235 C241 C213 D
CLOCK SCD1U16V2KX-3GP SCD1U16V2KX-3GP

SC4D7U10V3KX-GP SC4D7U10V3KX-GP
2
(R78.47520.5BL) (R78.47520.5BL) L12 1 2 XF1
32
31
30
29
28
27
26
25
2
2
14 CK_PCIE_3_GLAN_DP LAN1 IND-4D7UH-210-GP 24
MDI3- 23 1:1 2 MDI3-_C
14 CK_PCIE_3_GLAN_DN
AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPO
LED2
1
33 C226 C593
GND SC4D7U6D3V3KX-GP SCD1U16V2KX-3GP
change 20131216
2
1 MCT4
Net name follow superb
+1.05V_LAN P_1.05VLAN_OUT Mount for RTL8111GS/RTL8111GA ONLY
1 24
PCI-E Colse to the AVDD10 pin location
MDI0+
MDI0- 2 MDIP0 REGOUT 23
MDIN0 VDDREG V_3P3_LAN_REG
3 22 +1.05V_LAN RJ1
MDI1+ 4 AVDD10 DVDD10 21 PCIE_WAKE_N_LOM MDI3+ 22 3 MDI3+_C SPEED_1000*_L1 9 GREEN
change 20131216 5 MDIP1 LANWAKE# 20 RTL_ISOLATE_N SPEED_100*_L1 10 + 1 MDI0+_R
MDI1-
MDIN1 ISOLATE# -
1
1
C596 C597 C594 C598 MDI2+ 6 19 PLTRST_LAN_N 21
SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP MDI2- 7 MDIP2 PERST# 18 MDI2- 20 1:1 5 MDI2-_C 2 MDI0-_R
13 LANCLK_REQ_N MDIN2 HSON MDI1+_R
8 17 3
2
2
AVDD10 HSOP 13 4 MDI2+_R
change 20131025 5 MDI2-_R
REFCLK_N
REFCLK_P
PCIE_RXN_LAN_C C220 1 2 SCD1U10V2KX-5GP HSI_DN3 4 MCT3 6 MDI1-_R
CLKREQ#
MDI3+_R
AVDD33
11 HSI_DP3
7
MDIN3
MDIP3
PCIE_RXP_LAN_C C221 1 2 SCD1U10V2KX-5GP HSI_DP3 LAN_LED_ACT 11 8 MDI3-_R
HSIN
HSIP
11 HSI_DN3 LINK*_ACTIVITY_L +
11 HSO_C_DP3 12
+1.05V_LAN -
M
Colse to the pin22 Close to LAN chipset
11 HSO_C_DN3 YELLOW
(71.08111.Y03) MDI2+ 19 6 MDI2+_C
SKT-JACK-361-GP
9
10
11
12
13
14
15
16
18 (62.10044.891)
change 20131025 MDI1- 17 1:1 8 MDI1-_C
LANCLK_REQ_N_R
1
1
C600 C599 MDI3+
LAN SC1U10V2KX-1GP
(78.10520.5FL)
SCD1U16V2KX-3GP MDI3-
2
PLTRST_LAN_N Reserve for Reserve for 7 MCT2

20 PLTRST_LAN_N RTL8111G/GS/GA RTL8111GA V_3P3_LAN
2013/06/06 Stuff 0ohm_Ryan
O
13 PCIE_WAKE_N_LOM LANCLK_REQ_N MDI1+_C
R362 1 20R2J-2-GP MDI1+ 16 9
HSO_C_DP3
2
HSO_C_DN3 XRF_TDC1 15
CK_PCIE_3_GLAN_DP MDI0- 14 1:1 11 MDI0-_C D3 (R)
2
CK_PCIE_3_GLAN_DN
0R0402-PAD-2-GP
AZ5125-01H-R7G-GP
R425
R426 R427 C595
1
R) R) (R)
330R2J-3-GP(
330R2J-3-GP(
10 MCT1
SCD1U16V2ZY-2GP
2
2010/09/20
Madrid W/O SMB indeed
.C
LAN surage solution
1
1
change 20131025
C229 MDI0+ 13 12 MDI0+_C
SCD1U25V2KX-2-GP LAN_LED_ACT
2
XFORM-24P-27-GP
XRF_TDC1
(68.89241.30A) R424
SPEED_1000*_L1 2 1 SPEED_1000*_L
2013/03/01 change LAN1 from RTL8111FA to RTL8111GA_Ryan Michael 2012/2/15 R423

330R2J-3-GP
SPEED_100*_L1 2 1 SPEED_100*_L
2
330R2J-3-GP
C601 SB XF1 horizontal and swap
SC1KP50V2JN-2GP pair for layout routing 2011/06/26
1
AM
(R)
C C
MCT3
MCT4
MCT1
MCT2
MDI0+
MDI1+
MDI2+
MDI3+
MDI0-
MDI1-
MDI2-
MDI3-
Link Act
1
R850 R851 R848 R849
75R3J-L-GP
75R3J-L-GP
75R3J-L-GP
75R3J-L-GP
EC18 EC17 EC15 EC14 EC13 EC12 EC10 EC9 Giga 100 10
1
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
SC6D8P50V2CN-GP
X
2
Link Orange Green
PCB
T
MCT_R
Act Blink Blink Blink
LAN_XTAL1
1
C615
X4 SC1KP2KV6KX-GP
2
3 2
LA
LAN_XTAL2
4 1
20140114 Madrid 1A Charles
1
3D3V_S5 XTAL-25MHZ-181-GP
change C606=27pF,C607=22pF
C607 C606
2
SC22P50V2JN-4GP SC27P50V2JN-2-GP

modify symblo to SMD type
1
R366
0R0805-PAD-2-GP-U
IX
2
V_3P3_LAN
V_3P3_LAN_REG
.F V_3P3_LAN
MCT1
MCT2
MCT3
MCT4
Lan Surge 1
R833
2
B B
1
0R0603-PAD-2-GP-U
1
2013/06/05 delete LAN switch_Ryan C239 C237 C214 C242 C225 C592
C603 C602
2
SC4D7U10V3KX-GP
SC4D7U10V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U10V3KX-GP
2
1
1
GDT1 GDT2 GDT3 GDT4 (78.47520.5BL)
GT1206-200ASMD-GP
GT1206-200ASMD-GP
GT1206-200ASMD-GP
GT1206-200ASMD-GP
(78.47520.5BL)
(78.47520.5BL)
(R) (R) (R) (R)
W
2
2
(R) (R) (R) (R)
Reserve EMI
CMM Choke 2013/04/22 follow FAE design_Ryan
W
V_3P3_LAN
L59 L57 L58 L56 3D3V_S0
MDI3-_C 2 1 MDI3-_R MDI2-_C 2 1 MDI2-_R MDI1-_C 2 1 MDI1-_R MDI0-_C 2 1 MDI0-_R
MDI3+_C 3 4 MDI3+_R MDI2+_C 3 4 MDI2+_R MDI1+_C 3 4 MDI1+_R MDI0+_C 3 4 MDI0+_R
1
U11 (R)TVLST2304AD0-1-GP
U10 (R)TVLST2304AD0-1-GP 5V_S5 5 R358 PCIE_WAKE_N_LOM 1 2 (R)
W
FILTER-4P-137-GP FILTER-4P-137-GP FILTER-4P-137-GP FILTER-4P-137-GP 5 1KR2J-1-GP R369

5V_S5 10KR2J-3-GP
(66.R0036.04L) (66.R0036.04L) (66.R0036.04L) (66.R0036.04L)
2
RTL_ISOLATE_N
1
20131027 CM 2
2 R359
15KR2F-GP
1
6
1
2
MDI0-
MDI2-
MDI3+
MDI1+
MDI1- 2013/03/01 Delete Trace LAN_EEDI/LAN_EECS_Ryan
MDI3- MDI0+
MDI2+
A A
<Core Design>
Wistron Corporation
Title
LAN RTL8111GA
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
SPI FLASH ROM (4M byte) for PCH

SSID = Flash.ROM 3D3V_S5 SPI ROM Equal length need to less than 500mil
2N7002-11-GP Q27
(84.2N702.J31) SPI ROM Equal length need to less than 500mil
D S (R)
1
C195 C191
SC10U6D3V5KX-1GP SCD1U16V2KX-3GP
SPI_WP#_R
change 20131216
2
G
SPI_W P_R_N
need check SPI_W P_R_N 13,20 2012/09/10_aPisa_SA
for chrome
D D
1
R325 3D3V_S5 SYSTEM SB 3D3V_SPI,改改 3D3V_S5,
0R0402-PAD-2-GP
SPI ROM 3D3V_S5
2
1
3D3V_S5
1
SPI_W P# 20131023 Madrid SA Charles R322
check List 1KR2J-1-GP R340
unMount for Madrid 1A 20140114 Charles 1KR2J-1-GP
CSO direct connect to PCH
no need pull high
M
SPI1
2
SPI_CS0#_R 1 8 R821
13 SPI_CS0#_R
R326 1 2 15R2J-GP SPI_SO 2 7 SPI_HOLD_R 1 (R) 215R2J-GP
13 SPI_MISO SPI_HOLD 13
R324 1 2 15R2J-GP SPI_W P# 3 (R) 6 SPI_CLK_R
13 SPI_W PI SPI_CLK_R 13
(R) 4 5 SPI_SI_R
SPI_SI_R 13
O
1
1
SC4D7P50V2CN-1GP
EC6 SKT-G6179-GP-U (R)
SC4D7P50V2CN-1GP (R) EC7 EC8
62.10076.011
2
(R) SC4D7P50V2CN-1GP
.C
U6
1 8
2 CS# VCC 7
3 SO/SIO1 HOLD# 6
AM
C 4 WP# SCLK 5 C
GND SI/SIO0
MX25L6406EM2I-12G-GP
(72.25Q64.G01) MainSource0822
72.25Q64.G01 not support QualIO
T
LA
IX
B
.F 2012/01/03 B
+RTC_VCC
RTC_AUX_S5 Q18
R143 Connector Modify Done Done
1KR2J-1-GP
W
2 RTC_PW R 1 2
1
+
3 Width=20mils
13D3V_AUX_S5_C 2013/04/25 Ryan BTT1
SSID = RBATT BAT-T15-0013-BA10-0-GP

2
2
C101 3D3V_A
SC1U6D3V2KX-GP (R) BAS40C-GP
1
(75.00040.C7D) R145
MainSource0822 1 2
-1 for RTC Leakage
0R0402-PAD-2-GP
W
Clear CMOS CMOS1

1
RTC_RST#
RTC_RST# 13
2011/9/30
R146 1 2 20KR2F-L-GP RTC_RST# 2
RTC_AUX_S5
PCH_RTCRST_DOW N 3
<Core Design>
PIN-CON3-S-GP
1
Add CLR CMOS circuit

A C107 A
1 NC SC1U6D3V2KX-GP R147
4K7R2J-2-GP Wistron Corporation
2
2 RTC_RST 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

2
3 GND
Title
SPI/RTC
A3
Madrid SA
5 4 3 2 1
5 4 3 2 1
AO3418 NMOS 3.1A, 60mohm,Vgs=10V Michael 2011/12/01

SSID = SDIO NMOS H: Enable L:Disable change 5V_S5 to 5V_Charger
3.1A 60 mohm(10V)
3D3V_A
(Vds 30V,Vgs 12V)
D
DCBATOUT (S84.T3906.E11)
D Q44 Q28 D
PMBS3906-GP AO3418L-GP
1 2 SCALAR_PC_SW1 2 3 SCALAR_PC_SW3 G (S84.03052.031)
47KR2J-2-GP 20121007 Charles MainSource0822
1
R402 (S) (S) Marge material
S
1
R388 R381 P3P3V
Scalar Spec Table
1
1 2 SCALAR_PC_SW2 47KR2J-2-GP 1KR2J-1-GP C186
1
330KR2J-L1-GP (S) SC1U10V2KX-1GP
2
5V_Charger
R403 C253 (S) 20121022 Charles
2
Add softstart
SCD1U25V2KX-2-GP
(S)
2
1
SCALAR_PC_SW5
change 20131025
R380 20140114 Madrid 1A Charles 20131224 Madrid -1A Charles GPI input From High Low Default
1
100KR2J-1-GP (A) Fix to reserved cost down Q29
unMount for 1A
(S) R1082
D
3D3V_S5 0R2J-2-GP PM_SLP_S3# 13,20,21,25,35,36,38,40,41
2
SCALAR_PC_SW4
Q29
AO3418L-GP GPI-1 PC Power ON SB PC Monitor Monitor
Pin69
2
SC1U10V2KX-1GP
C187
G (R84.03052.031)
1
MainSource0822
1
R375 (R)
M
S
5V_S5_AMP
10KR2F-2-GP
6
(R) (A63.47334.1DL)[aPisa] -1M 20130107 Charles

GPI-2 Mode change/
2
Q42 R320 add R9566( 47K ) to GND for power discharge Pin109 PC: PC (PC->HDMI)
2
20 SCALAR_EN 2N7002KDW-GP
(S75.27002.F7C)
1
47R2J-2-GP
2 Panel OnOff SW Normal Touch Monitor: HDMI, VGA (HDMI)
1
3
1
O
R866 reserve R1082 ,check EUP to save Q29
C 10KR2F-2-GP DCBATOUT 20121014 Charles C
(R) 20140104 Madrid 1A Charles Modify AMP power As 19V
SCALAR_EN_4 (need 8~26 V)
PCH_1D05V is ok for AspireLink
2
1
unmount 1V_S0 solution, (R) R886 20131220 Madrid SB Charles
.C
(R) R877 100KR2J-1-GP mount for SB, test to short 19V & 19v AMP
S
100KR2J-1-GP R908
1 2 SCALAR_EN_1 G Q92 0R3J-0-U-GP
2
DMP3098L-GP
SCALAR_EN_2
(R)
GPO output
2
20131027 CM
1
(R) (R) 19V_AMP
U41
D
1
SCALAR_EN_3
C641 (R)
PC: ON
change 20131025
G C648
Pin55 Scalar ON OFF
SCD1U25V2KX-2-GP
GPO-2 Panel On/OFF
AM
2 SCALAR_VDD_EN 21,23
SCD1U50V3KX-GP Monitor: Detect Signal
2
D R888 (A)
S
1 2
PC: PC,
100KR2J-1-GP
Pin104 GPO-3 PC/Monitor PC_MONITOR_SW 19,21 Scalar PC Monitor Monitor: HDMI, VGA
2N7002K-2-GP
[aPisa] -1M 20130107 Charles
add R9608 (100k ) to GND for power discharge Pin101 GPO-5 Video BLON_EN# 21,23 Scalar Disable Enable Disable
T
Pin72 GPO-6 Audio Mute SHDN_MUTE_AP_CTL 21 Scalar on-Mute MUTE MUTE
B Scalar IC Power P1P2V
B
P3P3V
3D3V_S5
LA
P3P3V
435mA
600mA
1
1
(S) (S)
C270 C267
1
3
2
1
(S) (S) SC10U10V5ZY-1GP SCD1U16V2ZY-2GP

2
C623 C624
VIN
GND
VOUT
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP
2
IX
(S)
U40
LD1117AG-12-AA3-A-R-GP

modify to smaller/cheaper 74.D1117.G3C
.F
A <Core Design> A
W
Wistron Corporation
Title
SCALAR POWER (RTD2483AD)
W

Custom
Madrid
Tuesday, January 21, 2014
SA
Date: Sheet 30 of 68
5 4 3 2 1
W
5 4 3 2 1
SSID = USB
D D
3D3V_S5
VCC5_USB
M
D
1
DCBATOUT Q41
PMBS3906-GP Q40 R371
R372 (84.T3906.E11) AO3418L-GP 0R5J-5-GP
1 2 USB_EN1 2 3 USB_EN3 G
O
(84.03052.031) (R)
47KR2J-2-GP MainSource0822 3D3V_USB
2
1
S
R374 R373 R832
1
1 2 USB_EN2 1KR2J-1-GP
.C
47KR2J-2-GP
1
330KR2J-L1-GP
C230change 20131025
2
SCD1U25V2KX-2-GP
2
1
R377
AM
C C
100KR2J-1-GP
2
USB_EN4
USB_EN5
20121112 aPisa -1A Charles
mount R6106,R6108,Q6104 to fix USBpower
T
LA
6
4
3D3V_S5
Q85
1
2N7002KDW-GP
R391
(75.27002.F7C) 10KR2J-3-GP
1
IX
2
R834 USB_EN_R
1 2 USB_EN6
13,20,38 PM_SLP_S4#
D
4K7R2J-2-GP
B
.F Q43 B
2N7002-7F-GP
G
(84.2N702.J31)
W
S
W
USB_EN 27
1
R396
100KR2J-1-GP
W
2
<Core Design>
A
Wistron Corporation A

Title
USB2.0 Power SW
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
D D
M
O
.C
C C
AM
2012/08/18_aPisa_SA
Delete Battery Charger
T
LA
IX
B B
.F
W
W
W
A A
<Core Design>
Wistron Corporation
Title
Battery Charger
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
Close to CPU
S3 Power Reduction Circuit Processor VREF_DQ Implementation
D D
20121012 Jerry
Delete
M
5 S3 Power Reduction X01 20091111 JE40 HR modify 驗R3710上
上上
O
.C
AM
C C
2013/03/11 Delete_Ryan
T
LA
IX
Close to CPU
S3 Power Reduction Circuit SM_DRAMPWROK
.F 1D5V_S3
1
B R631 (R) B
1KR2J-1-GP
R633
2
1 2
W
0R0402-PAD-2-GP S3 Power Reduction Circuit
20121204 aPisa -1 Charles SM_DRAMRST#
0ohm short pad
5 SM_DRAMRST# S
R632
W
D SM_DRAMRST#_D 1 2 DDR3_DRAMRST# 9,10

0R0402-PAD-2-GP
1
G 20121204 aPisa -1 Charles
(R) C491 0ohm short pad
Q63 (R) SC100P50V2JN-3GP
2
2ND = 84.2N702.031 SB to -1
W
84.2N702.J31
DRAMRST_CNTRL_PCH 13
2N7002K-2-GP
20121016 aPisa SB Charles

Don’t support DS3 C498 (R)
DRAM reset 2 1DRAMRST_CNTRL_PCH
SCD047U16V2KX-1-GP
A <Core Design> A
2013/03/05 NO USED_Ryan
Wistron Corporation
Title
ADAPTER OCP / S3 reduction

A3
Madrid SA
5 4 3 2 1
5 4 3 2 1
ANNIE solution
AD_JK_S_R DCBATOUT
90W 135W Co-Lay PU7
1 S D 8
2 S D 7
3 S D 6
PWR_AD+_2 4 G D 5
1
AD_JK_S DCIN2
DCIN1 AO4407AL-GP PR77 PR72
2
1 3 (84.04407.G37) 20KR2J-L2-GP 20KR2J-L2-GP
1
D D
2 PR169 PC49 (63.10434.1DL) (R63.10334.1DL)
3 2 200KR2F-L-GP SC1U25V3KX-1-GP
2
2
PC48 4
2
SCD1U50V3KX-GP
5 1 CM 10/17
1
D11 NP1 NP1 DEL PU3804
1
P6SMBJ24A-H-GP NP2 NP2
change 20131025 NP3
DC-JACK285-GP 20140114 Madrid 1A Charles
1
DC-JACK310-GP (R) Change to 100K
(G) PR170
100KR2J-1-GP
Michael 2011/2/15
2
AD_JK_S_R
change the P/N of PU3802 and PU3804
M
SIZE 2512
0.01OHM 2W GAIN1= VO/(V2-V1)=R2/R1
PR73 (O) PC99 1 2 SC100P50V2JN-3GP
AD_JK_S 1 2 (O)
O
D01R2512F-3-GP
PR174
1 2 OCP_2
R439 1 2
0R5J-5-GP (R)
R2
1MR2F-GP 20121114 aPisa -1A Charles
.C
Add 6pcs 100pF 0402 for 19V EMI issue
R441 1 2 (O) DCBATOUT
0R5J-5-GP (R) 20121119 aPisa -1A Charles
BOM Review
R862 1 2 AD_JK_S_R
0R5J-5-GP (R)
Mount Only for w/o OCP manual
GAIN2= 1+R2/R1
1
R440 1 2
SC100P50V2JN-3GP
EC21
SC100P50V2JN-3GP
EC16
SC100P50V2JN-3GP
EC19
SC100P50V2JN-3GP
EC25
SC100P50V2JN-3GP
EC2
SC100P50V2JN-3GP
EC5
C 0R5J-5-GP (R)
V1 C
AM
4
(O) (O74.00358.X11)
2
8
1 PR172 2 OCP_0 2 - LM358DR2G-GP
1 5 U42B
100KR2F-L1-GP
1 PR171 2
(O)
OCP_1 3 +
OCP_4
+
7 VO
100KR2F-L1-GP U42A 6 -
LM358DR2G-GP
RH Vc 10%
8
V2 (O74.00358.X11)
4
135W: 6.04k 5V ~121W
20131127 Madrid SB Charles 90W: 6.04k 3.3V ~81W
delet R865,R863 for CNVBD2 layout
R1 R1
2
PR175 65W: 0 3.3V ~60W

1
2
PR173
1 2 OCP_5
R2 1MR2F-GP PC98 (O) PR176
T
SCD1U25V2KX-GP 100KR2F-L1-GP
(O)
2

(O)
R2
1
1MR2F-GP
follow seattl OPC control
1
AD_JK_S_R (O)
LA
PR588 PR178 AD_JK_S_R
6K04R2F-GP 8K2R2F-1-GP
(O) (R64.33015.6DL)
RH
2
(O74.00358.X11)
8
OCP_3 LM358DR2G-GP
(R) 5 U28B
+ ADP_OCP
R893 7
1
5V_S5
2 5V_cmp
1 0R2J-2-GP 6 -
PR177
RL
IX 1
15KR2F-GP 3D3V_S5 1 2 3V3_cmp
H_PROCHOT_N 7,41
4
1
1
PC100 (O) (O) R892 0R2J-2-GP PC50
1
SCD1U16V2KX-3GP (O) (R) (O)
Vc
2
2
R528 SCD1U16V2KX-3GP PR78 (O)
2
100KR2F-L1-GP 15KR2F-GP
D
2
B
.F 20121112 aPisa -1A Charles
Add a pull low resistor for 65W
OCP_7 G
Q58
2N7002A-7-GP
(O84.2N702.J31)
B
S
PR76 (O)
15KR2F-GP
W
AD_JK_S_R
2
1
3D3V_VGA_S0
PR74 (O)
100KR2F-L1-GP
2
W
DC Fan Control R13 (R)
2
OCP_6 10KR2J-3-GP
3D3V_S0 20131204 Madrid SB Charles 5V_HDD
1
follow seattl Add DC Fan control
1
GPIO17_THERMAL_INT 1 2GPIO9_ALERT#
GPIO9_ALERT# 54,60
1
PR75 (O) R14 (R) 0R2J-2-GP

R854 100KR2F-L1-GP
2
2K2R2F-GP R865
D
W
2
15KR2F-GP
Q3
R1041
2
4
(R) 2N7002A-7-GP
S
1 2 CPU_FANCTL1_A- 2 - R1040 Q54 G (R84.2N702.J31)

20 CPU_FANCTL1
1
1 CPU_FAN_O2 1 CPU_FAN_O_1 G 2N7002KDW-GP

15KR2F-GP 3 + U28A 10KR2F-2-GP (O75.27002.F7C)
1
C786 LM358DR2G-GP PA102FMG-GP-U
S
1
SC22U6D3V5MX-2GP (O74.00358.X11) Q98

8
(R) C785
0.4A
2
AD_JK_S_R SCD1U16V2KX-3GP 2013/04/24 change GPU OCP (low active)_Ryan

2
CPU_5V_FANCTL1
R863 35 S0_PWR_GOOD
CPU_FANCTL1_A+ 1 2
A A
4K7R2F-GP
2
C330
R859 SC22U10V5MX-GP
10KR2F-2-GP
<Core Design>
2
1
Wistron Corporation
Title
DCIN JACK
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
3D3V_S5
Power Sequence
2
2013/06/26 Change time sequence for PCH_PWRGD Ryan
R706
10KR2J-3-GP
(R)
3D3V_S5
2011/9/22
2
13,20 PWROK3_1_R 1
R691
2
0R2J-2-GP ALL_SYS_PWRGD3V_150MS
R688
10KR2J-3-GP
(R)
Reserve for
system power
1
VCORE_PWRGD R687
1 2 SYS_PWROK_R 1 2SYS_PWROK
6,7,13,41 VCORE_PWRGD SYS_PWROK 13
R690 (R) 0R2J-2-GP PCH_PWRGD_AND
D 0R0402-PAD-2-GP D
ok
BAS16-1-GP
D
1
C534
1 Q70 Q71
(R)
4
SCD01U50V2KX-1GP
2N7002A-7-GP
2
3 (R75.27002.F7C) G (R)
,21,25,35,36,38,40,41 PM_SLP_S3# 2N7002KDW-GP
2
S
1
3
D20
(R)
S0_PWR_GOOD
34 S0_PWR_GOOD
M
O
ANNIE Run Power Modify 3V/5V Logic Control as Load Switch 5V_S0 5V_CHARGER
3D3V_S5
3D3V_S0
3D3V_A
1
.C
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
U7 EC11 EC27
1 R717 2
2
15 (R) (R) 100KR2J-1-GP
GND
C791
SC10U16V5ZY-GP
R710 1 14 (R)
1 2 RUN_EN_4 2 VIN1#1 VOUT1#14 13
PM_SLP_S3#
D
VIN1#2 VOUT1#13
1
3 12 RUN_EN_1
ON1 CT1
C1593
13,20,21,25,35,36,38,40,41 4K7R2J-2-GP 4 11 5V_S0 Q75 (R)

VBIAS GND
AM
5V_CHARGER RUN_EN_2
SCD01U50V2KX-1GP
5 10 2N7002K-2-GP
C C
2
6 ON2 CT2 9
VIN2#6 VOUT2#9 84.2N702.J31
1
7 8 SB:must to be
VIN2#7 VOUT2#8
(R) closed U3604 2ND = 84.2N702.031
1
C792
SC470P50V2KX-3GP
C1592
SC470P50V2KX-3GP
C790
SC10U16V5ZY-GP
2
TPS22966DPUR-GP
S
G
2
2
3D3V_S5
13,20,21,25,35,36,38,40,41 PM_SLP_S3#
1
10KR2J-3-GP
R1050
T
20131018 Madrid SA Charles Add R3620 and R3621 for
Add to replace Page39 1D5V_S0 discharge S5->S0
2
RUNPWR_R4 12V_S0
LA
1D5V_S3
1D5V_S0
6
MAX=0.15A
10KR2J-3-GP
R1051
Q69
2N7002KDW-GP
D
(75.27002.F7C)
Q84
1
R835 10KR2J-3-GP AO3418L-GP

RUN_EN_3 2 1 Q9630.G G (84.03052.031)
IX
S
1
PC97 (R) 1 modify F7 Mark as Always mount

SCD1U10V2KX-5GP (R) C783
SCD047U16V2KX-1-GP
2
1D5V_S0
2
B
.F 20131204 Madrid SB Charles B
add 0.47uF 16V on Q84 G and S
EUP Power 5V_CHARGER

W
U39 (R)
1 D D 6 5V_S5
2012/06/08_ROME SA 2 D D 5
DCBATOUT Change R3608 from 47k to 33k Q35 3 G S 4
W
PMBS3906-GP
(84.T3906.E11) R343 AO6402A-GP 1 2 20131204 Madrid SB Charles
R355 1 2 EUP_R1 2 3 EUP_R3 1 2 R1039 add 47K 63.47334.1DL for 5V_S5 for power discharge,
33KR2F-GP 47KR2J-2-GP
close to U39
1
0R0402-PAD-2-GP
R344 R342 20121204 aPisa -1 Charles
1
1 2 EUP_R2 1KR2J-1-GP 5V_CHARGER

47KR2J-2-GP 0ohm short pad
W
1
R357 330KR2J-L1-GP
C192
2
SCD1U25V2KX-2-GP
2
Q83
1
change 20131025
R354 AO3418L-GP 5V_S5
100KR2J-1-GP
D S
EUP_R5
2
(84.03052.031)
EUP_R4

G
R336
Colay with U3604
1 2 EUP_R6
20 EC_EUP_EN# 3D3V_A
A A
4K7R2J-2-GP
EUP_EN
6
Q33 U12 ID=7A <Core Design>
2N7002KDW-GP 1 D D 6
2 D 5
(75.27002.F7C) 3
D
G S 4 Wistron Corporation
1
3D3V_S5 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

AO6402A-GP Taipei Hsien 221, Taiwan, R.O.C.
1
Title
C193 C784 1 2
SCD01U50V2KX-1GP RUN POWER & SEQUENCE
2
SCD047U16V2KX-1-GP Size Document Number Rev

Custom
add 0.47uF 16V on U12 G and S Madrid SA
5 4 3 2 1
5 4 3 2 1
12V_PWR 12V_S0
D D
PR55 1 2 0R0805-PAD
PR53 1 2 0R0805-PAD
PR54 1 2 0R0805-PAD
PR48 PC36
2D2R5J-1-GP
2 1 12V_PWR_BT1
SCD1U50V3KX-GP
2 1 IMax=3A
12V_PWR
U60 PL5
IND-5D6UH-45-GP
12V_PWR_BOOT 1 9
2 BOOT GND 8 12V_PWR_LX 1 2
3 NC#2 SW 7
12V_PWR_FB 4 NC#3 VIN 6 PR51
M
FB GND
1
5 12V_PWR_EN 2 1 10KR2J-3-GP PC82 PC44 PC43 PC81
EN SC10U16V5KX-GP-U SC10U16V5KX-GP-U SC10U16V5KX-GP-U SC10U16V5KX-GP-U
PR144
2
RT8289GSP-GP 2D2R5J-1-GP
112V_PWR_LX1_SNB 2
1
C C
HIGH-->ENABLE (R) C97
K
PR589
O
LOW-DISABLE SC1U6D3V3KX-2GP
10KR2J-3-GP D31 (R)
1
SSM54PT-GP PC40
2
SC68P50V2JN-1GP
PM_SLP_S3# 13,20,21,25,35,38,40,41
2
PC80
.C
SC1500P50V3KX-GP
1
DCBATOUT_12V
DCBATOUT R1
2
R140
88K7R2F-GP
0R0805-PAD 2 1PR47
2
0R0805-PAD 2 1PR46
AM
Vout=1.222(1+R1/R2)
1
PC34 PC35
SC10U25V5KX-GP SC10U25V5KX-GP
1
R2
2
R135
10KR2F-2-GP
B B
2
T
LA
IX
<Core Design>
A A
Wistron Corporation
.F 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
DC to DC_12V(NCP1589A)
W
Custom
SA
5 4 3 2 1
W
W
5 4 3 2 1
D D
DCBATOUT PWR_DCBATOUT
R909 1 2 0R3J-0-U-GP
5V_PWR 5V_CHARGER
R910 1 2 0R3J-0-U-GP
3D3V_A 3D3V_PWR R911 1 2 0R3J-0-U-GP PR65 1 2 0R0805-PAD-2-GP
R912 1 2 0R3J-0-U-GP PWR_DCBATOUT PR163 1 2 0R0805-PAD-2-GP
M
PR67 1 2 0R0805-PAD-2-GP PR164 1 2 0R0805-PAD-2-GP
20131027 CM
PR68 1 2 0R0805-PAD-2-GP PWR_DCBATOUT PWR_DCBATOUT PR162 1 2 0R0805-PAD-2-GP
If EMI or power concern,
1
20131206 Madrid SB Charles change to 2pcs 68.00335.181
PR69 1 2 0R0805-PAD-2-GP Delete TC7 ; Add C1591 PR161 1 2 0R0805-PAD-2-GP
[Layout] C1591 place back to C591 PR165
PR70 1 2 0R0805-PAD-2-GP 5D1R2J-1-GP PR62 1 2 0R0805-PAD-2-GP
O
2
PR71 1 2 0R0805-PAD-2-GP 20131206 Madrid SB Charles PR63 1 2 0R0805-PAD-2-GP
1
1
Delete TC4 ; Add C1590
C1591 C591 C590 C1590 [Layout] C1590 place back to C590 PR64 1 2 0R0805-PAD-2-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
2
2
1
LDO5V PC89 2 1 SC4D7U6D3V2MX-GP-U PU11
D 8
D 7
D 6
D 5
5
6
7
8
RT8243BZQW-GP PC93 Imax=10A, OCP>16A
D
D
D
D
.C
Q37 SCD1U50V3KX-GP Freq=300KHz
2
SIS412DN-T1-GE3-GP 12 change 20131025
PG7 1 2 GAP-CLOSE-PWR-2U-GP 8243_LDO5 14 ENLDO change 20131025
LDO5
Imax=4.4A, OCP>9.5A 8243_HG2_R 8243_HG1_R 4
G
Freq=355KHz 11 8243_VIN
S
S
S
change 20131025 5V_PWR
1 S
2 S
3 S
4 G
VIN
1
3D3V_PWR PC96 SCD1U50V3KX-GP PR166 PR148 PC85 PQ5
3
2
1
C DCR=4.8 m ohm+/-20% PR167 1 2 8243_BT2_R 1 2 8243_BT2 7 19 8243_BT1 1 2 8243_BT1_R 1 2 PR159 FDMS7698-GP DCR=4.8 m ohm+/-20% C
BOOT2 BOOT1
IDC=15A, Isat=15A 10KR2J-3-GP PR168
8243_HG2 8243_HG1
PR158 10KR2J-3-GP IDC=15A, Isat=15A
1 2 2D2R5J-1-GP 8 18 2D2R5J-1-GP 1 2 SCD1U50V3KX-GP
AM
UGATE2 UGATE1
PL6 COIL-3D3UH-37-GP
2
PL7 1 2 IND-3D3UH-116-GP 2D2R5J-1-GP 8243_LX2 9 17 8243_LX1 2D2R5J-1-GP 1 2
PHASE2 PHASE1
16 8243_LG1
LGATE1
1
PC47 8243_LG2 10
LGATE2
1
D 8
D 7
D 6
D 5
5
6
7
8
1
PTC11 PG5 SC1800P50V3KX-GP PC90
1
1
D
D
D
D
PC94 SE220U6D3VM-8GP GAP-CLOSE-PWR-2U-GP (R) 8243_FB2 5 1 8243_FB1 SC1800P50V3KX-GP PG8 PTC10 PC91
2
SC1U16V3KX-5GP FB2 FB1 (R) GAP-CLOSE-PWR-2U-GP SE220U6D3VM-8GP SC1U16V3KX-5GP

2
2
8243_SN2 20 8243_BYP
2
2
BYP1 8243_SN1
1
1
8243_VO2 4 PC88 2 1 SC4D7U6D3V2MX-GP-U 8243_LDO3 15 LDO5V PC86 4
G
G
LDO3
1
S
S
S
PR66 PR153 SC1U10V2KX-1GP
1 S
2 S
3 S
220uF/6.3V ESR=15m ohm 2D2R5J-1-GP 3D3V_PWR20140103 Madrid -1A Charles 13 8243_SECFB 2 1 PQ4 PR152
3
2
1
SECFB
T
Delete Net LDO3V because useless
Ripple Current =3110mA (R)
21K5R2F-GP
FDMS0312AS-GP 2D2R5J-1-GP 220uF/6.3V
(R)
ESR=15m ohm
2
(R) Q39 PR160 1 2 10KR2J-3-GP 8243_PG 6 PR154

Ripple Current
2
PGOOD
1
PC92 SIS780DN-T1-GE3-GP 1 2
PR155 SC22P50V2JN-4GP PR59 2 1 91KR2F-GP 8243_CS1 2
10KR2F-2-GP 20131206 Madrid SB Charles (R) =3110mA
1
1
ENTRIP1
R1 6K65R2F-GP
(64.33025.6DL) PR154 mount 64.33025.6DL PC87
2
LA
PC95 3 8243_TON SC22P50V2JN-4GP PR149
TON force controller enter to skip mode for EUP saving
8243_CS2 R1
SCD1U25V2KX-2-GP
PR61 2 1 107KR2F-GP 4 15K4R2F-GP

2
2
ENTRIP2
1
change 20131025
GND
PR60
2
68KR2F-GP
21
2
1
PR156
R2 10KR2F-2-GP VOut=2*(1+(R1/R2))
VOut=2*(1+(R1/R2))
IX
1
2
PR151
R2 10KR2F-2-GP
2
B .F B
W
W
EE needs to check Sequence!!

W
A A
<Variant Name>
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
Title
DC to DC_5V/3D3V(RT8223M)

Custom SA
5 4 3 2 1
5 4 3 2 1
5V_S5
1
D D
C562
SC1U10V3KX-3GP
R777
2
5D1R2J-1-GP
2
C561
SC1U10V3KX-3GP
2 1
PWR_DCBATOUT_1D5V DCBATOUT
PWR_DCBATOUT_1D5V 1D5V_S3 R913 1 2 0R3J-0-U-GP
1
R914 1 2 0R3J-0-U-GP
8207_VDD
R772
14K3R2F-GP (R)
M
1
1
C227 C228 TC8 R915 1 2 0R3J-0-U-GP
2
1
1
8207_CS SC10U25V5KX-GP SC10U25V5KX-GP SE47U25VM-14-GP
20131027 CM
2
R758 R768
13
11
12
620KR2F-GP 100KR2J-1-GP U33
If EMI or power concern,
change to 2pcs 68.00335.181
5
6
7
8
R744
VDD
CS
VDDP
2
D
D
D
D
2D2R5J-1-GP C555 change 20131025
O
18 8207_BT 2 1 8207_BT1 2 1 SCD1U50V3KX-GP Q38
8207_PG 10 BOOT R827 FDMS7698-GP
PGOOD 2D2R5J-1-GP
8207_TON 9 17 8207_UG 2 1 8207_UG1 4 L6 1D5V_DDR
G
TON UGATE
S
S
S
COIL-1UH-43-GP
PWR_1D5V_EN_S5 8 20131111 Madrid SA Charles
3
2
1
S5
.C
PWR_1D5V_EN_S3 7 16 8207_LX 1 2 Edward confirm OK
S3 PHASE
8207_LDOIN 19
VLDOIN
5
6
7
8
5
6
7
8
1
1
D
D
D
D
D
D
D
D
C678 15 8207_LG
20131015 Madrid SA Charles SC1U6D3V2KX-GP LGATE (R) Q32 Q34
modify FDMS0312AS-GP FDMS0312AS-GP R824 (R)
2
1
0D75V_S0 8207_VTT 2D2R5J-1-GP TC5 TC6
AM
1 14 4 4 C538 E820U2D5VM-7-GP E820U2D5VM-7-GP
G
C C
2
VTTGND PGND
SCD1U25V2KX-2-GP
S
S
S
S
S
S
2
change 20131025
3
2
1
3
2
1
R702 5 8207_VDDQ
VDDQ
8207_SNB
0R0805-PAD (R)
1
1 2 8207_VTT 20 6 8207_FB C549
VTT FB SCD1U25V3KX-GP
1
2
2
VTTSNS
VTTREF
R713
10K2R2F-GP
Rt
GND
GND
1
C585
SC1800P50V3KX-GP
2
(R) RT8207MZQW-GP-U 20131220 Madrid SB Charles
T
21
2
1
C547 C546 Modify Symbol to costdown

SC10U6D3V3KX-GP SC10U6D3V3KX-GP W/ Q62
18207_VTTREF
2
1D5V_DDR 1D5V_S3
LA
C548 R308 1 2 0R0805-PAD
SCD033U16V2KX-GP
2
R309 1 2 0R0805-PAD
1
R714
10KR2F-2-GP
Rb R310 1 2 0R0805-PAD
IX
1
2
1
R313 1 2 0R0805-PAD
R718
0R0805-PAD R704
0R0402-PAD R312 1 2 0R0805-PAD
2
VOUT=0.75*(1+(Rt/Rb))
2
B
.F R311 1 2 0R0805-PAD
B
W
ENABLE SIGNAL
W
1 2 PWR_1D5V_EN_S5
13,20,31 PM_SLP_S4# PR147 0R0402-PAD
1
PC84
(R) SCD1U10V2KX-5GP
2
W
1 2 PWR_1D5V_EN_S3
13,20,21,25,35,36,40,41 PM_SLP_S3# PR146 0R0402-PAD
1
PC83
(R) SCD1U10V2KX-5GP
2
A A
<Variant Name>
Wistron Incorporated
Hsichih, Taipei
Title
DC to DC_DDR3 1D5VS3

C SA
5 4 3 2 1
5 4 3 2 1
D D
M
O
.C
C C
T AM
LA
IX
B B
.F
W
W
<Variant Name>
W
A A
Wistron Corporation
Title
DC to DC_1D5V(APL5930)
B
SA
5 4 3 2 1
5 4 3 2 1
D D
PCH_VIN_1D5V 1D5V_S3
12V_S0
PCH_1D05V PR56 1 2 0R0805-PAD
M
PR57 1 2 0R0805-PAD
PCH_VIN_1D5V
1
PR58 1 2 0R0805-PAD
R940 84.00172.037 SIR172DP

5D1R2J-1-GP
O
Vgs @ 4.5V,
1
3D3V_S0 PC45
Id = 13.6A,
2
SC10U6D3V3MX-GP PC46 change 20131025
Rds(on) = 10.3~12.4mohm, SCD1U25V2KX-2-GP
2
1
PR39
1
100KR2F-L1-GP
.C
PC27
5
6
7
8
13.05/20 Rossi keep APL5611 solution SC1U16V3KX-2GP 5A(Imax)
D
D
D
D
C
PCH_1D05V_EN
High Enable PU4
PCH_VCC
PU6 C
1 6 PR145 FDMS7698-GP
EN VCC 100R5J-4-GP
2 5 PCH_1D05V_DRV 2 1 PCH_1D05V_DRV_1 4 PD=(1.5-1.05)*5=2.25(W)
G
GND DRV
AM
S
S
S
PC29 3 4 PCH_1D05V_SS
3
2
1
FB SS
1
SCD1U25V2KX-2-GP
PC41
1
change 20131025
APL5611ACI-TRG-GP SCD01U25V2KX-3GP
(78.10324.2FL)
2
1
PC28 PR38
SCD047U16V2KX-1-GP 10KR2F-2-GP
(78.10322.2FL) 1D05V_PWR PCH_1D05V
2
PR44
PCH_1D05V_FB_1
1PR149_2
1 2 PR52 1 2 0R0805-PAD
0R0402-PAD
1
20131022 Madrid SA PR50 1 2 0R0805-PAD
T 1
PC32
Power Edward modify
1
SC1KP50V2KX-1GP PC30 PR43 PR49 1 2 0R0805-PAD
(R) PR42 10R2F-L-GP (09.8271N.A5L)
1PC73_1
2
1
ENABLE Signal
8K06R2F-GP
R1
2
LA
Follow London2
PC42 PT1 PC37
W/ Q9
Modify Symbol to costdown
SCD1U25V2KX-2-GP
SC150P50V2KX-GP E820U2D5VM-7-GP SC4D7U6D3V3KX-GP
2
change 20131025
3D3V_S0
PC33
SCD047U16V2KX-1-GP
2
1
PCH_1D05V_FB
PR41
100KR2F-L1-GP
1
From SLP_S4 change to SLP_S3--Kai 0327 (R)
IX
2
B PR45 1 2 0R0402-PAD PCH_1D05V_EN R2 PR40

24KR2F-GP Vout = 0.8*(1+R1/R2)=0.951V B
13,20,21,25,35,36,38,41 PM_SLP_S3#
2
1
PC31
SCD1U10V2KX-5GP
(R)
.F
2
Add PR4646--Kai 0328

W
W
W
A A
HR PX
Wistron Corporation
Title
DC to DC_1D05V(RT8237)
Custom
SA
5 4 3 2 1
5 4 3 2 1
SSID = CPU.Regulator
P_CPU_VCCIO PR86 1 2 4K02R2F-GP
DCBATOUT P_DCBATOUT_VCORE PR87 1 2 49K9R2F-L-GP
1
R547 2 1 0R0805-PAD PR82 PR84 PR88 1 2 21KR2F-GP
54D9R2F-L1-GP 130R2F-1-GP
R543 2 1 0R0805-PAD 20131211 Madrid SB Charles
PR89 1 2 34KR2F-GP Power Edward modify
2
R539 2 1 0R0805-PAD
Set PR89 as origenral 34K
R535 2 1 0R0805-PAD PR90 1 2 1D24MR2F-GP
R533 2 1 0R0805-PAD
PWR_VCC_PROG1
PWR_VCC_PROG2
PWR_VCC_PROG3
PWR_VCC_DRSEL
PWR_VCC_SLOPE
D PR85 2 1 0R2J-2-GP PWR_VCC_SDA D
7 H_VIDSOUT_VR
(R)
PR83 2 1 0R2J-2-GP PWR_VCC_ALERT#
7 H_VIDALERT_N_VR
PR91 1 2 0R2J-2-GP 5V_S0
PR81 2 1 0R2J-2-GP PWR_VCC_SCLK
7 H_VIDSCK_VR
check list VCORE_EN_N PR80 2 1 0R2J-2-GP
32
31
30
29
28
27
26
25
PU8
From 3D3V_S5 change to
ALERT#
PROG1
PROG2
PROG3
DRSEL
SCLK
SDA
SLOPE
3D3V_S0-- 131105 kai
PR79 2 1 1K91R2F-1-GP PWR_VCC_VRON 1 24
3D3V_S0 VR_ON PS4# PWR_VCC_PS4# 42
change 20131025
PC51 1 2SC1KP50V2KX-1GP
M
2 23
6,7,13,35,41 VCORE_PWRGD PGOOD PWM3
PR92 1 2 130KR2F-GP PWR_VCC_IMON 3 22

IMON PWM2 PWR_VCC_PWM2 42
PR93 2 1 0R2J-2-GP PWR_VCC_VRHOT# 4 74.95825.073 21

7,34 H_PROCHOT_N VR_HOT# NC#21
O
PWR_VCC_NTC
Place near high side MOSFET of Phase1 PC52 2 1 SC43P50V2JN-GP 5
NTC PWM1
20
PWR_VCC_PWM1 42
B=3940K PR20
PWR_VCC_NTC_1 PWR_VCC_COMP PWR_VCC_PHASE1
2 1 PR95 2 1 3K83R2F-GP 6 19 R537 2 1 0R2J-2-GP
COMP PHASE1 PWR_5019_VSWH1 42
NTC-470K-8-GP-U
PWR_VCC_FB 7 18 C352 2 1 SC100P50V2JN-3GP
.C
PR94 FB DRCTRL P_DCBATOUT_VCORE
1 2
PWR_VCC_FB2 PWR_VCC_DRCTRL 42
27K4R2F-GP 8 17
FB2 VIN PWR_VCC_VIN R540 1 2 2D2R5J-1-GP
ISUMN
ISUMP
1
ISEN3
ISEN2
ISEN1
SC56P50V2JN-2GP 1 2 PC56 33
NC#9
VDD
RTN
PAD C355
SCD22U25V3KX-3-GP
2
ISL95825HRTZ-T-GP
PR102
10
11
12
13
14
15
16
PC55 PC70 (R)
AM
C PWR_VCC_COMP_2 C
1 2 1 2 1 2 PR99 R545 1 2 2D2R5J-1-GP 5V_S0
1 2PWR_VCC_NC
PWR_VCC_ISUMN_IC
SC22P50V2JN-4GP 100R2F-L1-GP-U SC680P50V2KX-2GP
0R2J-2-GP
PWR_VCC_VDD C356 1 2 SC1U10V3KX-4GP-U
PWR_VCC_ISEN3
PC54 PR98
1 2 PWR_VCC_COMP_1 1 2 PR101 1 2 1K96R2F-1-GP
PWR_VCC_ISUMP
PWR_VCC_ISUMP 42
SC1200P50V2KX-1GP 60K4R2F-GP PR114
VCC_CORE 2 1
1
1
(R)
1
10R2F-L-GP PC65 2 1 SC330P50V2KX-3GP PC68 PC69 PR113
ISUMN_ISUMP_C
2K61R2F-1-GP
SCD033U25V2KX-GP
SCD1U25V2KX-2-GP
PR100
1K54R2F-GP
7 VCC_SENSE
2
1
PC66
T
1 PWR_VCC_COMP_3 2
2
1
SC330P50V2KX-3GP
7 VSS_SENSE
1
(R)
2
PC58 SCD01U50V2KX-1GP PC67 ISUMN_P_1 PR112
Place near Phase1 choke
1 2 change 20131025 SCD33U6D3V2KX-1-GP 11KR2F-L-GP
1
change 20131025
2
1
PR103
LA
2 1 PR119 PR30
15R2F-2-GP NTC-10K-26-GP-U
10R2F-L-GP (69.60013.131) B=3370K
PC62
PR111
2
SC680P50V2KX-2GP
2
1 2
PWR_VCC_ISUMN 42
2
42 PWR_VCC_ISEN2
1K15R2F-GP
42 PWR_VCC_ISEN1
PC63
PC64
(R) PC72 PR118
R1 PR104 2 1 0R2J-2-GP 1 2 PWR_VCC_ISUMN_CR 1 2
5V_S0
IX 1
1
1KR2F-3-GP
SC1800P50V2KX-1GP
R2
SCD22U16V2KX-GP
SCD22U16V2KX-GP
5V_S0 PR116 2 1 0R2J-2-GP
2
1PHASE 2PHASE3PHASE
B R1 stuff DY
.F DY B
R2 stuff stuff DY
1
PC74
SCD1U25V2KX-2-GP
2
W
3D3V_S5 3D3V_S0
R19
2
R17 1 2 VCORE_EN_N
W
1
10KR2J-3-GP PC23
SCD1U25V2KX-2-GP
22KR2J-GP
1
2
Q2
1 6
R18 1 210KR2J-3-GP VRM_EN_1 2
13,20,21,25,35,36,38,40 PM_SLP_S3#
5 VRM_EN_3 R16 1 2 10KR2J-3-GP
1
VCORE_EN_N 3 4
W
PC18
20131023 Madrid SA Charles MBT3904DW1T1G-2-GP
2
SCD1U25V2KX-2-GP
check list modify (75.03904.A7C)
VRM_EN_2
Q1 (R)
1 6 VRM_EN_6 R5 1 2 100R2J-2-GP
VRM_EN_4 H_PWRGD 7,13
R7 1 2 2
10KR2J-3-GP 5 VRM_EN_7 R8 1 2 10KR2J-3-GP
R10 1 2 VRM_EN_5 3 4
6,7,13,35,41 VCORE_PWRGD
100R2J-2-GP
MBT3904DW1T1G-2-GP
(75.03904.A7C)
A A
<Core Design>
Wistron Corporation
Title
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
VIN RIPPLE CURRENT Imax=9.40A P_DCBATOUT_VCORE
PHASE1
1
PC11 PC13 PC12 PTC2 (R)
5V_S0 SCD1U50V3KX-GP SC10U25V5KX-GP SC10U25V5KX-GP SE47U25VM-14-GP
2
1
D PR1 20131206 Madrid SB Charles D
1R5J-2-GP Unmount PTC3 ;Add PC112,PC113
[Layout] PC112 place back to PC12
2
PC113 place back to PC13
1
PC1 PC113 PC112
1 2 SC10U25V5KX-GP SC10U25V5KX-GP
2
SC1U10V3KX-4GP-U
PWR_5019_VCC1
PR3
2D2R5J-1-GP
PWR_5019_BOOT1 1 2BS1_PHASE1
M
2 0.36uH,
(R)
1
C1 DCR=0.76mohm+/-5% 20131212 Madrid SB Charles
21
2
6
7
8
3
PR7 U2 SCD22U25V3KX-3-GPIdc=30A power modify PL1,PL2to down SIZE
0R2J-2-GP Isat=40A Main : 68.R2010.10P
VCC
VIN
VIN
VIN
VIN
BOOT
2
2nd : 68.R2010.20A 20131211 Madrid SB Charles
1
PWR_5019_VSWH1 41 Power Edward modify VCC_CORE
O
1 2 0R2J-2-GP PWR_5019_PWM1 BS1_PHASE1_C PL1
PR10 23 5
41 PWR_VCC_PWM1 PWM VSWH#5 PWR_5019_VSWH1
16 1 2
PR8 1 2 0R2J-2-GP PWR_5019_FCCM1 1 VSWH#16 15 IND-D2UH-13-GP
41 PWR_VCC_DRCTRL SMOD VSWH#15 14
VSWH#14
2
PR16 1 2 0R3J-0-U-GP PWR_5019_EN1 22 13
5V_S0 EN VSWH#13 TP1 PG1 PG2
1
.C
TPAD14-OP-GP PR26 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP TC17 PTC4
E820U2D5VM-7-GP
PWR_5019_GH1 1
ST330U2D5VBM-GP
(R80.3371V.A2L)
PR13 1 2 0R2J-2-GP 4 2D2R5J-1-GP
41,42 PWR_VCC_PS4#
1
AOZ5019QI-GP GH
2
(R) 19 PWR_5019_GL1 1
20 GL
1PWR_5019_SNB1
CGND
PGND
PGND
PGND
PGND
PGND
PGND
TP32
TPAD14-OP-GP
AM
18
17
12
11
10
9
C C
PC21
SC1500P50V3KX-GP
PHASE1_ISUMN1
PHASE1_ISUMP1
330uF/2.5V
2
ESR= 9 m ohm
Ripple Current =3900mA
PR120 1 2 10R2F-L-GP
PWR_VCC_ISUMN 41,42
PR105 1 2 10KR2F-2-GP
PWR_VCC_ISEN2 41,42
(64.18215.6DL) (64.18215.6DL)
PR590 1 PHASE1_ISUMP_R
2 3K65R2F-1-GP PR122 1 2 3K65R2F-1-GP
PWR_VCC_ISUMP 41,42
T
PR107 1 2 10KR2F-2-GP
PWR_VCC_ISEN1 41,42
LA
P_DCBATOUT_VCORE
From 5V_S5 change to
5V_S0-- 131105 kai
PHASE2 5V_S0
1
1
PC15 PC17 PC16 PTC3
SCD1U50V3KX-GP SC10U25V5KX-GP SC10U25V5KX-GP SE47U25VM-14-GP
IX
2
2
1
PR2
1R5J-2-GP 20131216 Madrid SB Charles
mount PTC3, unmount PC116,PC117
2
to solve high frequency noise when CPU idle

PC2
1 2 (R) (R)
between C0 to C6
.F
1
PC117 PC116
B SC1U10V3KX-4GP-U SC10U25V5KX-GP SC10U25V5KX-GP B
2
2
PWR_5019_VCC2
PR4
2D2R5J-1-GP
PWR_5019_BOOT2
1 2BS2_PHASE2 CPU=35W
W
TDC=20A
0.36uH, IccMax=48A
1
C2 DCR=0.76mohm+/-5%
21
2
6
7
8
From 5V_S5 change to U1 SCD22U25V3KX-3-GP Idc=30A

Isat=40A
VCC
VIN
VIN
VIN
VIN
BOOT
5V_S0-- 131105 kai

2

VCC_CORE
PWR_5019_PWM2 BS2_PHASE2_C PL2 Power Edward modify
PR11 1 2 0R2J-2-GP 23 5 Add TC18 ,delete PTC5
41 PWR_VCC_PWM2 PWM VSWH#5 PWR_5019_VSWH2
16 1 2
1 VSWH#16 15 IND-D2UH-13-GP
SMOD VSWH#15 14
VSWH#14
1
PR14 1 2 0R3J-0-U-GP PWR_5019_EN2 22 13

5V_S0 EN VSWH#13 TP2 PG4 PG3
1
W
(R) TPAD14-OP-GP PR18 GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP TC18

PR12 1 2 0R2J-2-GP 4 PWR_5019_GH2 1 2D2R5J-1-GP E820U2D5VM-7-GP
41,42 PWR_VCC_PS4#
1
AOZ5019QI-GP GH
2
2
19 PWR_5019_GL2 1
20 GL
1PWR_5019_SNB2
PHASE2_ISUMN2
CGND
PGND
PGND
PGND
PGND
PGND
PGND
PHASE2_ISUMP2
TP31
TPAD14-OP-GP PR117 1 2 10R2F-L-GP
PWR_VCC_ISUMN 41,42
18
17
12
11
10
9
PC14
SC1500P50V3KX-GP PR108 1 2 10KR2F-2-GP
PWR_VCC_ISEN1 41,42
2
(64.18215.6DL) (64.18215.6DL)
PR591 1 2 3K65R2F-1-GP
PR121 1 2 3K65R2F-1-GP
PHASE2_ISUMP_R PWR_VCC_ISUMP 41,42
A A
PR106 1 2 10KR2F-2-GP
PWR_VCC_ISEN2 41,42
<Core Design>
Wistron Corporation
Title
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
HDMI-IN
change the 3D3V_S5 to 3D3V_A

EMI/ESD near Connector
Use 62.10078.041 30u -> NG for production EMI/ESD near Connector
HDMI
-1A change to use 62.10078.291 and check HDMI_5V
3D3V_A
21,43 HDMI1_D2+ alternate source
1
(S)
D 21,43 HDMI1_D2- R434
D
1
21,43
21,43
HDMI1_D1+
HDMI1_D1- Connector D13
R444
(S)
1KR2J-1-GP
HDMI_HDCP_READY
2
HDMI1_D0- HDMI1_D0+
10KR2J-3-GP
21,43 HDMI1_D0+ change symbol as 62.10078.631 HDMI1_D0+_C 1
2
21,43 HDMI1_D0- HDMI1_CK- HDMI1_CK+ HDMI1_D0-_C 2 3
2
HDMI1 (S) HDMI1_CK+_C 4 8 DET_HDMI#
21,43 HDMI1_CK+
2
22 HDMI1_CK-_C 5
21,43 HDMI1_CK- HDMI1_D2+_C 1 R473 R489 R490 R472 2010/03/08
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 6 9 Change R792 to 20K
1
2 (R) (R) (R) (R) 7 10
1
HDMI1_D2-_C 3 U21 (S75.23C62.07D)
1
HDMI1_D1+_C
check! 4
5
SP3010-04UTG-GP AZ23C6V2-1-GP
M
HDMI1_D1-_C 6
HDMI1_D0+_C (R)
7
3
20,21,43 DET_HDMI# 8
HDMI1_D0-_C 9 20
R442 1KR2J-1-GP HDMI1_CK+_C 10
2 1 DET_HDMI_C 11
21 DDC_WP 20,21,43 DET_HDMI# HDMI1_CK-_C 12
20131018 Mardrid SA Charles
O
21,43 HDMI1_SDA
21,43 HDMI1_SCL
(S) 13 modify ESD connect point
14
HDMI_SCL_IN 15
21 HDMI_HDCP_READY HDMI_SDA_IN 16
For HDMI 1.3 Spec 17
18
HDMI_HPDET
.C
19
21 D15 HDMI_SCL_IN
HDMI_5V
SKT-HDMI22-11-GP HDMI1_D2- HDMI1_D2+ HDMI1_D1-_C 1
HDMI_5V HDMI1_D1+_C 2 3 HDMI_SDA_IN
HDMI1_D1- HDMI1_D1+ HDMI1_D2-_C 4 8
2
HDMI1_D2+_C 5
1
C240
2
2
2
SCD1U16V2ZY-2GP 6 9 U22 (R)
AM
1
C (R) R482 R491 R483 7 10 AZ23C6V2-1-GP C

R484 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
10KR2J-3-GP (R) (R) (R) SP3010-04UTG-GP
R433 (S) (R)
1
1
3
HDMI_HDCP_READY 2 1 100R2J-2-GP Modify for Madrid 20131001 Charles (R)
Modify HDMI as 62.10078.521
T
LA
5V_S0 5V_S5_AMP
Michael 2011/12/01
2009/12/13
2009/12/08
All 10K RES "Reserve"
Vendor Comment
1
IX
R392 R385
0R0402-PAD-2-GP 0R2J-2-GP HDMI_CLK & DATA level shift
20121204 aPisa -1 Charles (R)
(S66.R0036.04L) (S66.R0036.04L)
0ohm short pad don't need from Scalar
2
DLM11SN900HY2L-GP DLM11SN900HY2L-GP
3 4 HDMI1_D2-_C 3 4 HDMI1_D0-_C
21,43 HDMI1_D2- 21,43 HDMI1_D0-
change 20131025
B
DDC5V_HDMI_R 1
DDC5V_HDMI
.F 21,43 HDMI1_D2+
2 1 HDMI1_D2+_C
21,43 HDMI1_D0+
2 1 HDMI1_D0+_C
B
3 DDC5V_HDMI TR20 TR18
HDMI_5V
2
1
20131027 CM
R471 R479 R487 (R)
W
3
BAT54C-11-GP 4K7R2J-2-GP 10KR2J-3-GP C256

4K7R2J-2-GP
(S83.6R803.E31) D5 (S) (S64.10015.6DL) (S) SCD1U16V2ZY-2GP

MainSource0822 (S66.R0036.04L) (S66.R0036.04L)
2
U25 DLM11SN900HY2L-GP DLM11SN900HY2L-GP

D4 3 4 HDMI1_D1-_C 3 4 HDMI1_CK-_C
21,43 HDMI1_D1- 21,43 HDMI1_CK-
(S) 8 1
2
BZX84-C6V8-GP R478 (S64.10015.6DL) DDC_WP_1 7 VCC A0 2 2 1 HDMI1_D1+_C 2 1 HDMI1_CK+_C

HDMI_SCL_IN WP A1 21,43 HDMI1_D1+ 21,43 HDMI1_CK+
1 2 47R2J-2-GP 6 3
W
HDMI_SDA_IN 1 2 47R2J-2-GP 5 SCL A2 4

R470 (S) SDA GND TR19 TR17
1
(R) (R) AT24C02C-SSHM-T-GP 20131028 Madrid SA Charles ;

C310 C296 (S) Swap
21,43 HDMI1_SDA
21,43 HDMI1_SCL
2
2
SC33P50V2JN-3GP
SC33P50V2JN-3GP
R488
1 2 100R2J-2-GP DDC_WP
W
1
C309 C295 (S)

DUMMY-C2
DUMMY-C2
2
Michael 2011/12/01
change R283 and R305 from 100ohm to 47ohm
A
Vendor Comment A
<Core Design>
Wistron Corporation
Title
HDMI IN
C
Madrid
Tuesday, January 21, 2014
SA
Date: Sheet 43 of 68
5 4 3 2 1
5 4 3 2 1
SSID = VIDEO HDMI Level Shifter & CONNECTOR Pin 3 Pin 4 Pin 6 Pin 10 Pin 34 Pin 35
71.03411.B03 Low Low Low Low Low Low

UMA_Muxless : default setting used PS8101. if don't used PS8101 71.03411.D03 Low Low NC NC NC NC
please change C5103~C5110 to 0 ohm resister
NXP Eq NC NC NC NC NC
： Check SPEC
Eq：
HDMI port0 & port2 cross
3D3V_S0
change 20131025
DDSP_B_TX_DATA3# C244 1(S) 2 SCD1U10V2KX-5GP HDMI_CLK_R#

4 DDSP_B_TX_DATA3# DDSP_B_TX_DATA3 C243 1(S) 2 SCD1U10V2KX-5GP HDMI_CLK_R
4 DDSP_B_TX_DATA3
2
D D
DDSP_B_TX_DATA2# C250 1(S) 2 SCD1U10V2KX-5GP HDMI_DATA0_R# R904 (S) F5 (R)
4 DDSP_B_TX_DATA2# DDSP_B_TX_DATA2 C249 1(S) 2 SCD1U10V2KX-5GP HDMI_DATA0_R 0R3J-0-U-GP
4 DDSP_B_TX_DATA2 POLYSW-2A6V-2-GP
1
HDMI_VDD
modify NXP/ Parade Colay solution
DDSP_B_TX_DATA1# C248 1(S) 2 SCD1U10V2KX-5GP HDMI_DATA1_R# HDMI_VDD
4 DDSP_B_TX_DATA1# DDSP_B_TX_DATA1 C247 1(S) 2 SCD1U10V2KX-5GP HDMI_DATA1_R
4 DDSP_B_TX_DATA1
(S) (S) (S) (S) (S) (S) (S) (S)
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
1
DDSP_B_TX_DATA0# C246 1(S) 2 SCD1U10V2KX-5GP HDMI_DATA2_R#
20131027 CM
C616
C612
C611
C613
C620
C621
C622
C619
4 DDSP_B_TX_DATA0# DDSP_B_TX_DATA0 HDMI_DATA2_R
C245 1(S) 2 SCD1U10V2KX-5GP
4 DDSP_B_TX_DATA0
2
HDMI_VDD
2
R418
0R0402-PAD
DUMMY 0 ohm change to 0 ohm--Kai 0308
M
R412 (S)
1 2
HDMI_LVL_11
HDMI_LVL_33
HDMI_VDD
1KR2J-1-GP
DDC_EN
OE_N
25
32
11
15
21
33
40
46
26
2
U16
OE SELECTION
O
(S71.08171.B03)
DDC_EN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
OE#
HDMI_VDD
HDMI_DATA0_R# 38 23 HDMI_DATA0_C_R#
HDMI_DATA0_R 39 IN_D1- OUT_D1- 22 HDMI_DATA0_C_R
IN_D1+ OUT_D1+
1
HDMI_DATA1_R# 41 20 HDMI_DATA1_C_R#
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
IN_D2- OUT_D2-
1
HDMI_DATA1_R 42 19 HDMI_DATA1_C_R
R397
R398
R422
R406
R400
(R)
4K7R2J-2-GP
IN_D2+ OUT_D2+
R1076
R1077
R1075 (R) (R) (S) (R)
R404
HDMI_DATA2_R# 44 17 HDMI_DATA2_C_R# (S)
HDMI_DATA2_R 45 IN_D3- OUT_D3- 16 HDMI_DATA2_C_R (S) (R)
.C
2
2
IN_D3+ OUT_D3+ OC_0 OC_1 OC_3 EQ_0 EQ_1 OC_2
1 2
HDMI_CLK_R# 47 14 HDMI_CLK_C_R#
IN_D4- OUT_D4-
1
HDMI_CLK_R HDMI_CLK_C_R
0R2J-2-GP
0R2J-2-GP
0R2J-2-GP
48 13
HDMI_LVL_11
HDMI_LVL_33
HDMI_LVL_27
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
4K7R2J-2-GP
IN_D4+ OUT_D4+
1
R1072
R856
R847
R853
R861
R852
R846
R1073
R1074
(R) (R) (R) (R) 487R2F-GP
28 DDC_CLK_HDMI (R) (R) (R) (S)
OC_0 3 SCL_SINK 29 DDC_DATA_HDMI (S)
2
OC_0 SDA_SINK 30 HPD_HDMI_CON
2
OC_1 4 HPD_SINK
OC_1
EQ_0 34 9 HDMI_CLK_1
EQ_0 SCL_SOURCE 8 HDMI_DATA_1
EQ_1 35 SDA_SOURCE 7 HPD_HDMI_CON_R
EQ_1 HPD_SOURCE
OC_2/REXT
C C
AM
OC_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PI3VDP411LSZBE-GP
6
10
1
5
1 HDMI_LVL_12 12
18
24
27
31
36
37
43
49
1 HDMI_LVL_1
OC_2
OC_3
U5103 change to NXP--Kai 0319
HDMI_LVL_27
0R2J-2-GP
1
R1071 0R2J-2-GP
R1078
(S) C781
SC2D2U6D3V2MX-GP (R) (R)
T
LA
Modify for Madrid 20131001 Charles
Modify HDMI as 62.10078.521
IX
Down size CMC--Kai 0307
TR15 TR14
1
(S)
1
HDMI_DATA0_C_R 1 2 HDMI_DATA0_C_RH (S) HDMI_DATA2_C_R 1 2 HDMI_DATA2_C_RH R1060

R1054 180R2J-1-GP
HDMI_DATA0_C_R# 4 3 HDMI_DATA0_C_RH# 180R2J-1-GP HDMI_DATA2_C_R# 4 3 HDMI_DATA2_C_RH#
2
DLM11SN900HY2L-GP DLM11SN900HY2L-GP
2
(S66.10036.04L) (S66.10036.04L)
HDMI CONN
B
TR16
20131027 CM
TR13
.F (S) HDMI2
B
22
1
HDMI_DATA1_C_R 1 2 HDMI_DATA1_C_RH (S) HDMI_CLK_C_R 1 2 HDMI_CLK_C_RH (S) 1 HDMI_DATA2_C_RH

R1057 R1063
HDMI_DATA1_C_R# 4 3 HDMI_DATA1_C_RH# 180R2J-1-GP HDMI_CLK_C_R# 4 3 HDMI_CLK_C_RH# 180R2J-1-GP 2
3 HDMI_DATA2_C_RH#
DLM11SN900HY2L-GP DLM11SN900HY2L-GP 4 HDMI_DATA1_C_RH
2
(S66.10036.04L) (S66.10036.04L) 5
6 HDMI_DATA1_C_RH#
HDMI_DATA0_C_RH
W
7
8
20 9 HDMI_DATA0_C_RH#
20131028 Madrid SA Charles ; HDMI_CLK_C_RH
Swap 10
11
12 HDMI_CLK_C_RH#
13
14 5V_HDMI 5V_S0
15 DDC_CLK_HDMI
16 DDC_DATA_HDMI
17 F6 (S)
18 5V_HDMI 1 2 20131128 Madrid SB Charles
19 NB team cost review
21 POLYSW-1D1A6V-9-GP-U
W
SKT-HDMI22-11-GP

change symbol as 62.10078.631 F5102 from 1.5A change to 1.1A--Kai 0519
3D3V_S0
W
5V_S0
DDC CLK & DATA HPD_HDMI_CON

1
1
R411
BAT54C-12-GP 10KR2J-3-GP
D23 (R)
2
(S75.00054.T7D)
3
DDC_HDMI_PU
HPD_HDMI_CON_R
HPD_HDMI_CON_R 12
3
4
3
1
C609 (S) D6
1
RN16 (S) SCD1U16V2ZY-2GP R389 BZX84-C6V8-GP
R407
SRN1K5J-GP 200KR2J-L1-GP DY (R)
2
(R) 1MR2J-1-GP
(R)
2
PCH PU to 2.2K
1
2
2
5V Tolerance
1 4 HDMI_CLK_1 DDC_CLK_HDMI
A 12 DDPB_CTRL_CLK 2 3 HDMI_DATA_1 DDC_DATA_HDMI A
12 DDPB_CTRL_DATA
RN9
SRN0J-6-GP(S)
C618 C617
1
SC470P50V2KX-3GP SC470P50V2KX-3GP
(R) (R)
ESD
2
CHPZ6V2PT-1-GP-U
D24 U19 (R) U18 (R)
(R)
3
HDMI_DATA1_C_RH# 1 HDMI_CLK_C_RH# 1
HDMI_DATA1_C_RH 2 3 HDMI_CLK_C_RH 2 3 <Core Design>
HDMI_DATA2_C_RH# 4 8 HDMI_DATA0_C_RH# 4 8
HDMI_DATA2_C_RH 5 HDMI_DATA0_C_RH 5
6 9 6 9
Wistron Corporation
7 10 7 10 Taipei Hsien 221, Taiwan, R.O.C.
SP3010-04UTG-GP SP3010-04UTG-GP Title

20131028 Madrid SA Charles ; HDMI OUT
Swap
Custom
Madrid SA
5 4 3 2 1
SSID = SATA SATA HDD/Power Connector
HDD1
Layout: Put them together
9 5V_HDD
7
C257 1 2 SCD01U50V2KX-1GP SATA_TXP0_C 6 5V_S0 5V_HDD
12 SATA_TXP0 SATA_TXN0_C
C255 1 2 SCD01U50V2KX-1GP 5 F3
12 SATA_TXN0 4 1 2 C211
1
C238 1 2 SCD01U50V2KX-1GP SATA_RXN0_C 3 (R78.10421.2FL)
12 SATA_RXN0 SATA_RXP0_C SC10U10V5ZY-1GP
C236 1 2 SCD01U50V2KX-1GP 2 POLYSW-2A6V-GP C201
12 SATA_RXP0
2
20131010 Madrid SA Charles 1 (69.50014.001) SCD1U10V2KX-5GP
8 SB
Net name follow superb
O
(20.81593.007) 20131220 Madrid SB Charles
OBS change, study to cost down
1
SKT-SATA7P-19-GP-U
Black color F4 R349 (R)
.C
3D3V_S0 1 2 3D3V_HDD 0R3J-0-U-GP
HDDPW1
SATA 2.0 CONN
1 12V_HDD FUSE-1D5A6V-11GP
2
2
AM
3 20131202 Madrid SB Charles
5V_HDD 12V_S0 12V_HDD
4
5
Delete R368 for connector layout
3D3V_HDD
F2
1
1 2
JWT-CON5-S7-GP C219
1
SCD1U16V2ZY-2GP 20131202 Madrid SB Charles FUSE-3A15V-GP C190
2
T
(21.61820.105) 2013/06/24_CLOSE HDDPW1_EMI Delete C189 for connector layout SC1U25V3KX-1-GP
2
LA
change BOM to 1u 25V
update Symbo
IX
SATA ODD/ Power Connector
.F
ODD1
8
W
1 5V_S0 V_5_ODD
ODDPW1
F1
2 SATA_RXP4_C C112 1 2 SCD01U50V2KX-1GP SATA_RXP4 1 2 V_5_ODD 1
SATA_RXP4 12
3 SATA_RXN4_C C113 1 2 SCD01U50V2KX-1GP SATA_RXN4
SATA_RXN4 12
1
W
4 POLYSW-2A6V-GP C106 (R) C102 2

5 SATA_TXN4_C C122 1 2 SCD01U50V2KX-1GP SATA_TXN4 SC10U10V5ZY-1GP SC1U16V3KX-2GP
SATA_TXN4 12
6 SATA_TXP4_C C125 1 2 SCD01U50V2KX-1GP SATA_TXP4 (69.50014.001)
SATA_TXP4 12
2
7 JWT-CON2-S14-GP
9 (21.61783.102)
W
SKT-SATA7P-19-GP-U 20131010 Madrid SA Charles

(20.81593.007)
Black color Net name follow superb Front View
<Core Design>
SATA 2.0 CONN
Wistron Corporation
Pin1(GND) Taipei Hsien 221, Taiwan, R.O.C.
Title
20.60341.104: 4pin right angle HDD/ODD
20.60334.103: 3pin right angle Size Document Number Rev
Custom
Madrid SA
5 4 3 2 1
SSID = Wireless and Bluetooth 2011/11/29

Michael
ADD USB for BT Function
D
Mini Card Connector(Wireless LAN+BT) L44
(66.R0036.04L) D
FILTER-4P-137-GP
2012/06/26_ROME SA Change symbol to 5.2mm 11 USB_PP9
USB_PP9 4 3 USB_PP9W
Michael 2011/11/29 USB_PN9 USB_PN9W
Height: 5.2mm 11 USB_PN9
1 2
Change 1D5V_MEM to 1D5V_S0 T-CONN: 62.10043.831
1D5V_S0_WLAN
BELLWETHER: 62.10043.A81 20131027 CM
3D3V_S5 MINI1
Michael 2011/11/29
3D3V_S5 6 11 CLK_PCIE_WLAN#
Change 3D3V_S0 to 3D3V_EUP 1_5V REFCLK- 13 CLK_PCIE_WLAN
CLK_PCIE_WLAN# 14
M
REFCLK+ CLK_PCIE_WLAN 14
2
3_3VAUX
1
1D5V_S0 1D5V_S0_WLAN 23 PCIE_RXN5
R534 PERN0 PCIE_RXN5 11
(R) (R) 28 25 PCIE_RXP5
+1_5V PERP0 PCIE_RXP5 11
2 1 0R2J-2-GP 0R2J-2-GP 48
R544 +1_5V 31 PCIE_TXN5
11 20131010 Madrid
O
PETN0 PCIE_TXN5
24 33 PCIE_TXP5
PCIE_TXP5 11 checked
1 2
3D3V_S5_RSV 39 +3_3VAUX PETP0
+3_3VAUX USB_PN9W
2013/05/07 ADD_Ryan PC60
41
52 +3_3VAUX USB_D-
36
38 USB_PP9W
SC10U10V5KX-2GP +3_3VAUX USB_D+
.C
2
(R78.10693.41L) 8
UIM_PWR 1 PCIE_WAKE_N_WLAN_R R31 1 2 0R0402-PAD-2-GP
WAKE# PCIE_WAKE_N_WLAN 13
16 7 W1_CLKREQ_N R29 1 2 0R2J-2-GP
C UIM_VPP CLKREQ# CLK_PCIE_WLAN_REQ# 13 C
22 PLT_WLAN_RST# 20
PERST# 20130726
10 Add 0 ohm, CM
3D3V_S5 UIM_DATA
AM
12 53
14 UIM_CLK 53 54
UIM_RESET 54
1
modify for Madrid 20131001 Charles 17
RESERVED#17/UIM_C8 NP1
NP1
R536 19 NP2
symbol follow Superb, net/sch follow Pisa2 10KR2J-3-GP 45 RESERVED#19/UIM_C4 NP2
47 RESERVED#45
49 RESERVED#47 4 1D5V_S0_WLAN
2
BT_EN RESERVED#49 GND
Please close to PCIE2
11 BT_EN 51 9
RESERVED#51 GND 15
T
3 GND 18
COEX1 GND
1
5 21 C12 C357 C349
1 R550 210KR2J-3-GP COEX2 GND 26 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
3D3V_S5 GND
WLAN_EN 20 27 (R) (R) (R)
11 WLAN_EN
LA
2
W_DISABLE# GND 29
R542 1 210KR2J-3-GP MTK_PWR_EN_R 42 GND 34
MTK_USB_SW
R541 1 (R) 2 0R2J-2-GP MTK_USB_SW_R 44 LED_WWAN# GND 35
46 LED_WLAN# GND 37
LED_WPAN# GND 40
SMB_CLK R549 1 (R) 2 0R2J-2-GP SMB_CLK_WL 30 GND 43
9,10,13,21,22,54 SMB_CLK SMB_CLK GND
SMB_DATA R548 1 (R) 2 0R2J-2-GP SMB_DATA_WL 32 50
9,10,13,21,22,54 SMB_DATA SMB_DATA GND
IX
B B
SKT-MINI52P-93-GP
3D3V_S5
Michael 2011/11/29
.F Please close to PCIE2
Add W3_DISABLE_N for Bluetooth P3P3V
1
C13 C358 C348
Add R1091 and R1089 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC10U10V5ZY-1GP
W
1
2
R328 (R)
10KR2J-3-GP
PLT_WLAN_RST#
2
W
1
MTK_USB_SW
MTK_USB_SW
(R) C359
SB
SC10P50V2JN-4GP
2
W
<Core Design>
A A
Wistron Corporation
Title
Mini PCIE Card WLAN / BT

Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
D D
M
O
.C
C C
T AM
LA
B B
IX
.F
W
W
A A
<Core Design>
Wistron Corporation
W

Title
Mini PCIE Card (TV & SIM)
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
D D
M
O
.C
C C
T AM
LA
B
IX B
.F
W
W
W
<Core Design>
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
Title
Mini PCIE Card mSATA

Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
USB_PWR_3 G1
1 2 V_5_LED
5V_S0 COPPER-CLOSE-GP-U
3D3V_S5 USB_PWR_3
SUSPEND LED
1
L26 R481
PWRLED_CON 1 2 V_5_PWR1 1 2 R519 R511
D (63.10133.16L) 4K7R2J-2-GP 10KR2J-3-GP D
MHC1608S601LBP-GP
130R5J-GP (R)
2
20110626
Q55
2
(84.T3906.E11) R510
1 SUSLED_1 1 2 SUSLED_2 SUSLED_N
PMBS3906-GP SUSLED_N 20
2K2R2J-2-GP
Michael 2011/12/16
1
2010/11/15
SUSLED_CON_P1
(63.10334.1DL) add as vendor R526
suggestion
LED SW will be defined later 10KR2J-3-GP
(R)
2
1
2009/12/01 20131212 Madrid 1A Charles
R477 modify to change pin
M
150R5J-GP
2
3D3V_A
modify R477 to 150 ohm to meet ACER spec
C V_5_SUS1 C
2
O
2
R492
330KR2J-L1-GP 10mW L21
MHC1608S601LBP-GP
L31
1
PWRBTN# 1 2 PWRBTN#_1 2 1 PWRBTN_IN

PWRBTN_IN 20 3D3V_A P3P3V
Pannel on/off switch Branch
.C
MHC1608S601LBP-GP
1
2
R486
470R2J-2-GP C320 SUSLED_CON
1
(64.47005.6DL) SCD01U50V2KX-1GP R408 R413 10KR2J-3-GP
1
R460 10KR2J-3-GP (S)

10KR2J-3-GP (U)
(R) (S)
3
PANEL_SW_SC 1 2
AM
2
2
U24 (R) R414 0R2J-2-GP PANEL_SW
BAV99-13-GP 20110616 (U)
PANEL_SW_EC 1 2
R409 0R2J-2-GP
2
B USB_PWR_3 B
Delete D7
T
PANEL_SW_SC
21 PANEL_SW_SC
LA
PWRBT1 PANEL_SW_EC
20 PANEL_SW_EC
7 DCBATOUT
1
near to PWRBT1 two side
Pannel_SW
2 PWRBTN#
3
4 PWRLED_CON PANSW1
1 R181
1
5 SUSLED_CON Panel_SW 2 PANEL_ON_R 1 2

11 Panel_SW
1
SC100P50V2JN-3GP
EC23
SC100P50V2JN-3GP
EC1
6
33R2J-2-GP
IX 3
SC100P50V2JN-3GP
C286
SC100P50V2JN-3GP
C313
SC100P50V2JN-3GP
C314
8 3 4
2
1
D2 C136
SW-TACT-48-GP <Core Design>
2
CLX-CON6-8-GP LBAV99LT1G-1-GP SCD1U16V2ZY-2GP

(22.40126.181)
(R83.BAV99.D11)
2
A Wistron Corporation A
2
USB_PWR_3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
.F Taipei Hsien 221, Taiwan, R.O.C.
close to PWRBT1 as much as possible. Title

20121205 Charles
Add EMI solution PWR BT/Side Key/LED
W
Custom
Madrid SA
5 4 3 2 1
W
W
PWRLED_CON
PWRLED_CON
5 4 3 2 1
3D3V_S0
1
D R864 D
10KR2J-3-GP
DBGH1
2 1
2
13,20 LPC_AD3 LPC_FRAME# 13,20
4 3 V_3P3_DBP
13,20 LPC_AD2 6 5
M
X CLK_PCI_LPC 14
8 7
13,20 LPC_AD1 10 9
13,20 LPC_AD0 12 11 PLT_RST# 7,11,20
20 SIO_DEBUG_TX
14 13
O
20 SIO_DEBUG_RX 3D3V_S0
JWT-CONN14D-SFP-1-GP
.C
MP0822
AM
C C
2012/09/07_aPisa_SA
TPM Header Add TPM Header
T
12,20 INT_SERIRQ
LA
IX
.F
B B
W
W
W
<Core Design>
A
Wistron Corporation A
Title
Debug connector
A4
Madrid SA
5 4 3 2 1
5 4 3 2 1
For U3702 not OD AND gate 1U X 2 Under GPU 10U X 2 mid TO GPU
R3719 to 64.15015.6DL
R3720 to 64.75005.6DL 4.7U X 2 NEAR TO GPU 22U X 2 mid TO GPU
3D3V_VGA_S0
R3702 to DY
R99 (G)
1 2
0R0402-PAD-2-GP
1
10KR2J-3-GP
R109
(R) 1D05V_VGA_S0
3D3V_VGA_S0
2
1 5 3D3V_VGA_S0
20,54 PLTRST_GPU# IN B VCC
R107 1 2 IN_A_R 2 (G) (G)
D 3D3V_VGA_S0 D
IN A
1
C402 (G78.22610.5BL)
SC22U4V3MX-GP
C379 (G78.22610.5BL)
SC22U4V3MX-GP
C368 C372
1
10KR2J-3-GP (R78.10421.2FL) 3 4 VGA_RST# C388 C385 C395 C405
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
GND OUT Y
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
(R) C70 VGA1A 1 OF 17
2
(G78.10520.5FL)
(G78.10520.5FL)
SCD1U10V2KX-5GP U5 10KR2J-3-GP (G) (G)
2
1/17 PCI_EXPRESS
74VHC1G09DFT2G-GP R586
(G)
73.01G09.AAH GK107/GF108
2
GK208/GF117
(R)
AJ11 NC
PEX_WAKE#
OD AND gate required PEX_IOVDD_1
AG19
VGA_RST# AJ12 AG21
PEX_RST# PEX_IOVDD_2 AG22
PEG_CLKREQ#_1 AK12 PEX_IOVDD_3 AG24
PEX_CLKREQ# PEX_IOVDD_4 AH21
AL13 PEX_IOVDD_5 AH25 1U X 2 Under GPU 10U X 2 mid TO GPU
14 CLK_PCIE_VGA AK13 PEX_REFCLK PEX_IOVDD_6
14 CLK_PCIE_VGA# PEX_REFCLK#
M
PEG_RXP0 C381 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXP0 AK14 4.7U X 2 NEAR TO GPU 22U X 2 mid TO GPU
PEG_RXN0 C383 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXN0 AJ14 PEX_TX0
PEX_TX0# 1D05V_VGA_S0
PEG_TXP0 AN12
PEG_TXN0 AM12 PEX_RX0 AG13
PEX_RX0# PEX_IOVDDQ_1 AG15
PEG_RXP1 C378 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXP1 AH14 PEX_IOVDDQ_2 AG16
O
PEG_RXN1 C382 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXN1 AG14 PEX_TX1 PEX_IOVDDQ_3 AG18
PEX_TX1# PEX_IOVDDQ_4 AG25
1
PEG_TXP1 PEX_IOVDDQ_5
C386 (G78.22610.5BL)
SC22U4V3MX-GP
C398 (G78.22610.5BL)
SC22U4V3MX-GP
AN14 AH15 C373 (G) C369 (G)
PEG_TXN1 PEX_RX1 PEX_IOVDDQ_6
reserve an active driver for PEX_RST#--Kai 0313 AM14 AH18 C387 C376 C399 C396
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
PEX_RX1# PEX_IOVDDQ_7
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
AH26
2
PEG_RXP2 PEG_C_RXP2 PEX_IOVDDQ_8
(G78.10520.5FL)
(G78.10520.5FL)
C374 (G) 1 2 SCD22U10V2KX-1GP AK15 AH27 (G) (G)
PEG_RXN2 C377 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXN2 AJ15 PEX_TX2 PEX_IOVDDQ_9 AJ27
PEX_TX2# PEX_IOVDDQ_10
.C
AK27
PEG_TXP2 AP14 PEX_IOVDDQ_11 AL27
PEG_TXN2 AP15 PEX_RX2 PEX_IOVDDQ_12 AM28
PEX_RX2# PEX_IOVDDQ_13 AN28
PEG_RXP3 C371 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXP3 AL16 PEX_IOVDDQ_14
PEG_RXN3 C375 (G) 1 2 SCD22U10V2KX-1GP PEG_C_RXN3 AK16 PEX_TX3
PEX_TX3#
4 PEG_RXP[0..3] PEG_TXP3
PEG_TXN3
AN15
AM15 PEX_RX3 Add CAP follow vendor suggestion--Kai 0314
4 PEG_RXN[0..3] PEX_RX3#
AM
C C
AK17
AJ17 PEX_TX4
PEX_TX4#
4 PEG_TXP[0..3]
AN17
AM17 PEX_RX4
4 PEG_TXN[0..3] PEX_RX4#
AH17
AG17 PEX_TX5 GF108 GK208/GK107/GF117
PEX_TX5# AH12
NC PEX_PLL_HVDD 3D3V_VGA_S0
AP17
AP18 PEX_RX5 AG12
PEX_RX5# PEX_SVDD_3V3
AK18
AJ18 PEX_TX6
X7R
T
PEX_TX6#
1
AN18 C392 C456 C451
PEX_RX6
SCD1U10V2KX-5GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AM18
3.3V +/- 5%
2
PEX_RX6# (G78.10421.2FL)
(G) (G)
AL19
PEX_TX7 120mA
LA
AK19
PEX_TX7# (See NV DG)
AN20
AM20 PEX_RX7
PEX_RX7#
AK20
AJ20 PEX_TX8
PEX_TX8# L4
VDD_SENSE VGACORE_VDD_SENSE_1 60
AP20
AP21 PEX_RX8
PEX_RX8# L5
GND_SENSE VGACORE_GND_SENSE_1 60
AH20
IX
AG20 PEX_TX9
PEX_TX9#
AN21
AM21 PEX_RX9
PEX_RX9#
AK21
AJ21 PEX_TX10
PEX_TX10# P8
AN23 NC_3V3AUX
B
.F AM23
AL22
PEX_RX10
PEX_RX10#
1.05V +/- 3%
B
PEX_TX11
AK22
PEX_TX11# 120mA
AP23
PEX_RX11
(See NV DG)
AP24
PEX_RX11# AJ26 PEX_TSTCLK_OUT
W
AK23 PEX_TSTCLK_OUT AK26 PEX_TSTCLK_OUT# R572 1 (R) 2 200R2F-L-GP
PEX LANES 8 TO 15 NC FOR GF117/GK208

PEX_TX12 PEX_TSTCLK_OUT#
AJ23
PEX_TX12# Use 0 ohm at L8301 with N14P-GV2, please change to 63.00000.00L
AN24
Use 120 ohm@100MHz bead (ESR = 0.18 ohm)at L8301 for N14M-GE, please mount 68.00335.141
AM24 PEX_RX12 PEX_PLLVDD 1D05V_VGA_S0
PEX_RX12#
AH23 L45
PEX_TX13 PEX_PLLVDD
SC4D7U6D3V3KX-GP
AG23 AG26 1 2
PEX_TX13# PEX_PLLVDD
SCD1U10V2KX-5GP
SC1U10V2KX-1GP
W
AN26 MCB1608S121IBP-GP
1
AM26 PEX_RX13
PEX_RX13# X7R
1
C391 (G63.00000.00L)
AK24 R564 C389 (G) C390
2
AJ24 PEX_TX14 1
AK11 TESTMODE 2 10KR2J-3-GP (G78.10421.2FL) (G78.10520.5FL)
2
PEX_TX14# TESTMODE
Change to 0603 0 ohm.--Kai 0313
AP26 (G)
AP27 PEX_RX14
since GPU PCI-E is 8 lanes.--Kai 0313

PEX_RX14# 100MHZ 120mohm
W
AL25
AK25 PEX_TX15
PEX_TX15# R81
AN27 AP29 PEX_TERMP
1 2 2K49R2F-GP
AM27 PEX_RX15 PEX_TERMP
PEX_RX15# (G)
N14P-GS-A1-GP
(G)
madrid 20131017 Charles
power ask to modify as 09.8271N.A5L
A A
<Core Design>
Wistron Corporation
Title
GPU (1/5): PEG

A2
Madrid SA
5 4 3 2 1
5 4 3 2 1
LVDS Interface HDMI Interface

VGA1J 10 OF 17 VGA1K 11 OF 17
5/17 IFPAB 6/17 IFPC
ALL PINS NC FOR GF117
DP(GK208) LVDS
AN6 AF8
DPA_L3 IFPA_TXC# IFPC_RSET
AM6 DVI/HDMI DP
DPA_L3 IFPA_TXC
AJ8
IFPAB_RSET
AN3 IFPC_PLLVDD_PD AF7 AG2
DPA_L2 IFPA_TXD0# IFPC_PLLVDD I2CW_SDA IFPC_AUX_I2CW_SDA#
D AP3 AG3 D
DPA_L2 IFPA_TXD0 I2CW_SCL IFPC_AUX_I2CW_SCL
1
IFPAB_PLLVDD_PD AH8
IFPAB_PLLVDD AM5 (R) R580 AG4
DPA_L1 IFPA_TXD1# TXC IFPC_L3#
DPA_L1
AN5 10KR2J-3-GP AG5
IFPA_TXD1 TXC IFPC_L3
2
1
AH4
(R) AK6 IFPC TXD0 IFPC_L2# AH3
DPA_L0 IFPA_TXD2# TXD0 IFPC_L2
R579 AL6
DPA_L0 IFPA_TXD2
10KR2J-3-GP TXD1 AJ2
IFPC_L1# AJ3
TXD1
2
AH6 IFPC_L1
IFPA_TXD3# AJ6 AJ1
IFPA_TXD3 TXD2 IFPC_L0# AK1
TXD2 IFPC_L0
M
DPB_L3
AH9
IFPB_TXC# AJ9
DPB_L3 IFPB_TXC IFPC_IOVDD_PD AF6 P2
IFPAB_IOVDD_PD AG8 IFPC_IOVDD GPIO15
IFPA_IOVDD AP5
DPB_L2 IFPB_TXD4#
1
AG9 DPB_L2
AP6 N14P-GS-A1-GP
IFPB_IOVDD IFPB_TXD4
O
(G)
(R) R587
1
DPB_L1 AL7 10KR2J-3-GP

(R) IFPB_TXD5# AM7
DPB_L1
2
R577 IFPB_TXD5
10KR2J-3-GP
AM8
.C
DPB_L0
2
IFPB_TXD6# AN8
DPB_L0 IFPB_TXD6
AL8
IFPB_TXD7# AK8
IFPB_TXD7
AM
C C
GPIO14
N4 EDP Interface
IFPAB VGA1L 12 OF 17
N14P-GS-A1-GP 7/17 IFPD
(G)
AN2
IFPD_RSET
DVI/HDMI DP
T
VGA1M 13 OF 17 IFPD_PLLVDD_PD AG7 AK2
IFPD_PLLVDD I2CX_SDA IFPD_AUX_I2CX_SDA#
8/17 IFPEF I2CX_SCL AK3
IFPD_AUX_I2CX_SCL
LA
ALL PINS NC FOR GF117 AK5
TXC IFPD_L3#
1
AK4
TXC IFPD_L3
DVI-DL DVI-SL/HDMI DP AL4
(R) R590
TXD0 IFPD_L2#
10KR2J-3-GP IFPD TXD0 IFPD_L2
AL3
2
I2CY_SDA I2CY_SDA AB4 TXD1 AM4
IFPE_AUX_I2CY_SDA# AB3 IFPD_L1# AM3
I2CY_SCL I2CY_SCL IFPE_AUX_I2CY_SCL TXD1 IFPD_L1
IFPEF_PLLVDD_PD AB8
IFPEF_PLLVDD
IX
AM2
TXD2 IFPD_L0#
1
AC5 AM1
TXC TXC IFPE_L3# TXD2 IFPD_L0
AD6 AC4
(R) R598 IFPEF_RSET TXC TXC IFPE_L3
10KR2J-3-GP AC3
NC FOR GK208 TXD0 TXD0 IFPE_L2# AC2 IFPD_IOVDD_PD AG6 M6
2
TXD0 TXD0 IFPE_L2 IFPD_IOVDD GPIO17

AC1
B
IFPE
TXD1
TXD1
TXD1
TXD1
.F IFPE_L1#
IFPE_L1
AD1 N14P-GS-A1-GP
B
1
(G)
AD3
TXD2 TXD2 IFPE_L0# AD2 (R) R573
TXD2 TXD2 IFPE_L0 10KR2J-3-GP
2
NC FOR GK208
W
HPD_E HPD_E R1
GPIO18
W
IFPDE_PLL_IO_VDD_PD AC7
IFPE_IOVDD AF2
I2CZ_SDA IFPF_AUX_I2CZ_SDA#
I2CZ_SCL AF3
AC8 IFPF_AUX_I2CZ_SCL
IFPF_IOVDD
AF1
W
NC FOR GK208 TXC IFPF_L3#

TXC AG1
IFPF_L3
1
AD5
TXD3 TXD0 IFPF_L2#
(R) R597 AD4
TXD3 TXD0 IFPF_L2
10KR2J-3-GP
TXD4 TXD1 AF5
IFPF
2
IFPF_L1# AF4
TXD4 TXD1 IFPF_L1
AE4
TXD5 TXD2 IFPF_L0# AE3
TXD5 TXD2 IFPF_L0
NC FOR GK208
A A
HPD_F P3
GPIO19
<Core Design>
N14P-GS-A1-GP
(G)
Wistron Corporation
Title
GPU DIGITALOUT(2/5)
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
VGA1B 2 OF 17
2/17 FBA
VGA1C 3 OF 17
3/17 FBB
R129
(G)
58 MDA[7..0] MDA0 L28 E1 FB_CLAMP 1 2 ALL PINS NC FOR GF117/GK208
MDA1 M29 FBA_D0 FB_CLAMP
MDA2 L29 FBA_D1 10KR2J-3-GP G9
MDA3 M28 FBA_D2 E9 FBB_D0
MDA4 N31 FBA_D3 G8 FBB_D1
P29 FBA_D4 K27 FB_PLLVDD F9 FBB_D2 1D5V_VGA_S0
MDA5
FBA_D5 FB_DLL_AVDD 33mA FBB_D3
MDA6 R29 F11
MDA7 P28 FBA_D6 G11 FBB_D4
SCD1U10V2KX-5GP
56 MDA[15..8] MDA8 J28 FBA_D7 F12 FBB_D5 4 OF 17 VGA1D
MDA9 H29 FBA_D8 G12 FBB_D6
FBA_D9 X7R FBB_D7
14/17 FBVDDQ
1
MDA10 J29 G6
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC1U6D3V3KX-2GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
MDA11 H28 FBA_D10 C443 F5 FBB_D8 AA27
MDA12 G29 FBA_D11 (G78.10421.2FL) E6 FBB_D9 FBVDDQ_1 AA30 X7R X7R X7R X7R X7R X7R X7R X7R
2
FBA_D12 FBB_D10 FBVDDQ_2
1
MDA13 E31 F6 AB27
D MDA14 E32 FBA_D13 F4 FBB_D11 FBVDDQ_3 AB33 C454 C460 C466 C463 C476 C464 C481 C480 C477 C468 C469 C472 D
MDA15 F30 FBA_D14 G4 FBB_D12 FBVDDQ_4 AC27
2
56 MDA[23..16] C34 FBA_D15 E2 FBB_D13 FBVDDQ_5 AD27
MDA16
FBA_D16 Place close to Ball FBB_D14 FBVDDQ_6
MDA17 D32 F3 AE27 (G) (G) (G) (G)
(G78.10521.5BL)
(G78.10521.5BL)
(G78.10521.5BL)
(G78.10521.5BL)
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
MDA18 B33 FBA_D17 C2 FBB_D15 FBVDDQ_7 AF27
MDA19 C33 FBA_D18 D4 FBB_D16 FBVDDQ_8 AG27
MDA20 F33 FBA_D19 D3 FBB_D17 FBVDDQ_9 B13
MDA21 F32 FBA_D20 C1 FBB_D18 FBVDDQ_10 B16
MDA22 H33 FBA_D21 B3 FBB_D19 FBVDDQ_11 B19
MDA23 H32 FBA_D22 C4 FBB_D20 FBVDDQ_12 E13
58 MDA[31..24] MDA24 P34 FBA_D23
FBA_D24
B5 FBB_D21
FBB_D22
FBVDDQ_13
FBVDDQ_14
E16 Under GPU.
MDA25 P32 C5 E19
MDA26 P31 FBA_D25 A11 FBB_D23 FBVDDQ_15 H10
MDA27 P33 FBA_D26 C11 FBB_D24 FBVDDQ_16 H11
L31 FBA_D27 D11 FBB_D25 FBVDDQ_17 H12 1D5V_VGA_S0
MDA28
MDA29 L34 FBA_D28 B11 FBB_D26 FBVDDQ_18 H13
MDA30 L32 FBA_D29 D8 FBB_D27 FBVDDQ_19 H14
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
MDA31 L33 FBA_D30 A8 FBB_D28 FBVDDQ_20 H15
59 MDA[39..32] MDA32 AG28 FBA_D31 C8 FBB_D29 FBVDDQ_21 H16
FBA_D32 FBB_D30 FBVDDQ_22
1
C431 (G78.22610.5BL)
SC22U4V3MX-GP
MDA33 AF29 U30 B8 H18 C478
MDA34 AG29 FBA_D33 FBA_CMD0 T31 -FBA_CS0 56,58 F24 FBB_D31 FBVDDQ_23 H19 (G) C474 C475
MDA35 AF28 FBA_D34 FBA_CMD1 U29 G23 FBB_D32 D13 FBVDDQ_24 H20
SC22U6D3V5MX-2GP
2
2
MDA36 AD30 FBA_D35 FBA_CMD2 R34 FBA_ODT0 56,58 E24 FBB_D33 FBB_CMD0 E14 FBVDDQ_25 H21
FBA_D36 FBA_CMD3 FBA_CKE0 56,58 FBB_D34 FBB_CMD1 FBVDDQ_26
M
AD29 R33 G24 F14 H22
MDA37
MDA38 AC29 FBA_D37 FBA_CMD4 U32 FBA_A14 56,57,58,59 Need to connect FBA_CMD4 to FBA_A14 D21 FBB_D35 FBB_CMD2 A12 FBVDDQ_27 H23
(G) (G)
Modify power cap--Kai 0315
59 MDA[47..40]
MDA39 AD28 FBA_D38
FBA_D39
FBA_CMD5
FBA_CMD6
U33 FBA_RST 56,57,58,59
FBA_A9 56,57,58,59
for support 256Mx16 memory--Kai 0315 E21 FBB_D36
FBB_D37
FBB_CMD3
FBB_CMD4
B12 FBVDDQ_28
FBVDDQ_29
H24
MDA40 AJ29 U28 G21 C14 H8
MDA41 AK29 FBA_D40 FBA_CMD7 V28 FBA_A7 56,57,58,59 F21 FBB_D38 FBB_CMD5 B14 FBVDDQ_30 H9
MDA42 AJ30 FBA_D41 FBA_CMD8 V29 FBA_A2 56,57,58,59 G27 FBB_D39 FBB_CMD6 G15 FBVDDQ_31 L27
MDA43 AK28 FBA_D42
FBA_D43
FBA_CMD9
FBA_CMD10
V30 FBA_A0
FBA_A4
56,57,58,59
56,57,58,59
D27 FBB_D40
FBB_D41
FBB_CMD7
FBB_CMD8
F15 FBVDDQ_32
FBVDDQ_33
M27 Near GPU.
MDA44 AM29 U34 G26 E15 N27
MDA45 AM31 FBA_D44 FBA_CMD11 U31 FBA_A1 56,57,58,59 E27 FBB_D42 FBB_CMD9 D15 FBVDDQ_34 P27
MDA46 AN29 FBA_D45 FBA_CMD12 V34 FBA_BA0 56,57,58,59 E29 FBB_D43 FBB_CMD10 A14 FBVDDQ_35 R27
MDA47 AM30 FBA_D46 FBA_CMD13 V33 -FBA_WE 56,57,58,59 F29 FBB_D44 FBB_CMD11 D14 FBVDDQ_36 T27
57 MDA[55..48] FBA_D47 FBA_CMD14 FBA_A15 56,57,58,59 FBB_D45 FBB_CMD12 FBVDDQ_37
O
MDA48 AN31 Y32 E30 A15 T30
MDA49 AN32 FBA_D48 FBA_CMD15 AA31 -FBA_CAS 56,57,58,59 D30 FBB_D46 FBB_CMD13 B15 FBVDDQ_38 T33
MDA50 AP30 FBA_D49 FBA_CMD16 AA29 -FBA_CS1 57,59 A32 FBB_D47 FBB_CMD14 C17 FBVDDQ_39 V27
MDA51 AP32 FBA_D50 FBA_CMD17 AA28 C31 FBB_D48 FBB_CMD15 D18 FBVDDQ_40 W27
MDA52 AM33 FBA_D51 FBA_CMD18 AC34 FBA_ODT1 57,59 C32 FBB_D49 FBB_CMD16 E18 FBVDDQ_41 W30
MDA53 AL31 FBA_D52 FBA_CMD19 AC33 FBA_CKE1 57,59 B32 FBB_D50 FBB_CMD17 F18 FBVDDQ_42 W33
MDA54 AK33 FBA_D53 FBA_CMD20 AA32 FBA_A13 56,57,58,59 D29 FBB_D51 FBB_CMD18 A20 FBVDDQ_43 Y27
MDA55 AK32 FBA_D54 FBA_CMD21 AA33 FBA_A8 56,57,58,59 A29 FBB_D52 FBB_CMD19 B20 FBVDDQ_44
57 MDA[63..56] MDA56 AD34 FBA_D55 FBA_CMD22 Y28 FBA_A6 56,57,58,59 C29 FBB_D53 FBB_CMD20 C18
MDA57 AD32 FBA_D56 FBA_CMD23 Y29 FBA_A11 56,57,58,59 B29 FBB_D54 FBB_CMD21 B18 F1
AC30 FBA_D57 FBA_CMD24 W31 FBA_A5 56,57,58,59 B21 FBB_D55 FBB_CMD22 G18 FB_VDDQ_SENSE
.C
MDA58
AD33 FBA_D58 FBA_CMD25 Y30 FBA_A3 56,57,58,59 C23 FBB_D56 FBB_CMD23 G17 1D5V_VGA_S0
MDA59
MDA60 AF31 FBA_D59 FBA_CMD26 AA34 FBA_BA2 56,57,58,59 A21 FBB_D57 FBB_CMD24 F17 F2
MDA61 AG34 FBA_D60 FBA_CMD27 Y31 FBA_BA1 56,57,58,59 C21 FBB_D58 FBB_CMD25 D16 FB_GND_SENSE
MDA62 AG32 FBA_D61 FBA_CMD28 Y34 FBA_A12 56,57,58,59 B24 FBB_D59 FBB_CMD26 A18 (G) R614
MDA63 AG33 FBA_D62 FBA_CMD29 Y33 FBA_A10 56,57,58,59 C24 FBB_D60 FBB_CMD27 D17 2 1 FB_CAL_PD_VDDQ J27
FBA_D63 FBA_CMD30 V31 -FBA_RAS 56,57,58,59 B26 FBB_D61 FBB_CMD28 A17 FB_CAL_PD_VDDQ
FBA_CMD31 C26 FBB_D62 FBB_CMD29 B17 40D2R2F-GP
P30 R32 FBB_D63 FBB_CMD30 E17 FB_CAL_PU_GND H27
58 DQMA0 FBA_DQM0 NC FBA_CMD_RFU0 FBB_CMD31 FB_CAL_PU_GND
F31 AC32
56 DQMA1 FBA_DQM1 NC FBA_CMD_RFU1
F34 E11 C12
FBA_DEBUG0
56 DQMA2 M32 FBA_DQM2 GF117/GK208 E3 FBB_DQM0 FBB_CMD_RFU0 C20 FB_CAL_TERM_GND H25

58 DQMA3 AD31 FBA_DQM3 GK107/GF108 A3 FBB_DQM1 FBB_CMD_RFU1 FB_CAL_TERM_GND
59 DQMA4 AL29 FBA_DQM4 1D5V_VGA_S0 C9 FBB_DQM2
AM
C 59 DQMA5 AM32 FBA_DQM5 F23 FBB_DQM3 N14P-GS-A1-GP C
57 DQMA6 AF34 FBA_DQM6 R28 R599 1 (G) 2 F27 FBB_DQM4 (G)
57 DQMA7 FBA_DQM7 FBA_DEBUG0 AC28 R593 1 (G) 2 60D4R2F-GP C30 FBB_DQM5
FBA_DEBUG1 FBB_DQM6
1
60D4R2F-GP A24 G14 R620
M31 FBA_DEBUG1 FBB_DQM7 FBB_DEBUG0 G20 R608
58 QSAP_0 FBA_DQS_WP0 FBB_DEBUG1
42D2R2F-GP
G31 (G) 51D1R2F-GP
56 QSAP_1 FBA_DQS_WP1
56 QSAP_2
E33 R30 D10 (G)
M33 FBA_DQS_WP2 FBA_CLK0 R31 CLKA0 56,58 D5 FBB_DQS_WP0
58 QSAP_3
2
AE31 FBA_DQS_WP3 FBA_CLK0# AB31 CLKA0# 56,58 C3 FBB_DQS_WP1 D12
59 QSAP_4 FBA_DQS_WP4 FBA_CLK1 CLKA1 57,59 FBB_DQS_WP2 FBB_CLK0
59 QSAP_5
AK30 AC31 B9 E12
AN33 FBA_DQS_WP5 FBA_CLK1# CLKA1# 57,59 E23 FBB_DQS_WP3 FBB_CLK0# E20
57 QSAP_6 FBA_DQS_WP6 FBB_DQS_WP4 FBB_CLK1
57 QSAP_7
AF33 E28 F20
FBA_DQS_WP7 B30 FBB_DQS_WP5 FBB_CLK1#
A23 FBB_DQS_WP6
M30 K31 FBB_DQS_WP7
58 QSAN_0 FBA_DQS_RN0 FBA_WCK1
56 QSAN_1
H30 L30
E34 FBA_DQS_RN1 FBA_WCK1# H34 D9 F8
56 QSAN_2 FBA_DQS_RN2 FBA_WCK23 FBB_DQS_RN0 FBB_WCK1
58 QSAN_3
M34 J34 E4 E8
AF30 FBA_DQS_RN3 FBA_WCK23# AG30 B2 FBB_DQS_RN1 FBB_WCK1# A5
T
59 QSAN_5
AK31 AG31 A9 A6
AM34 FBA_DQS_RN5 FBA_WCK45# AJ34 D22 FBB_DQS_RN3 FBB_WCK23# D24
57 QSAN_7
AF32 AK34 D28 D25
FBA_DQS_RN7 FBA_WCK67# A30 FBB_DQS_RN5 FBB_WCK45# B27
J30 B23 FBB_DQS_RN6 FBB_WCK67 C27
FBA_WCKB1 J31 FBB_DQS_RN7 FBB_WCK67#
THE FBA_WCKBxx
FBA_WCKB1# J32 D6
PINS ARE USED
FBA_WCKB23 J33 FBB_WCKB1 D7
ONLY ON GK107
FBA_WCKB23# THE FBB_WCKBxx FBB_WCKB1#
LA
THEY ARE NC AH31 C6
FBA_WCKB45 AJ31 PINS ARE USED FBB_WCKB23 B6
FOR GK208/GF108
FBA_WCKB45# AJ32 1D05V_VGA_S0 ONLY ON GK107 FBB_WCKB23# F26
/GF117
FBA_WCKB67 AJ33 (G68.00335.181) THEY ARE NC FBB_WCKB45 E26
FBA_WCKB67# FOR GF108 FBB_WCKB45# A26
FB_PLLVDD
66mA L46
FBB_WCKB67
H26 U27 1 2 A27
FB_VREF FBA_PLL_AVDD MHC1608S300QBP-GP FBB_WCKB67#
H17 FB_PLLVDD
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
NC FBB_PLL_AVDD
N14P-GS-A1-GP
(G)
NV Review change to 30 ohm --> 68.00335.051 GF108 GK107
X7R X7R Pisa2: 80ohm --> 68.00335.181
1
NV suggestion C422 C430 C457 C461 C444

N14P-GS-A1-GP
(G)
SC22U6D3V3MX-1-GP
Follow vendor suggestion--Kai 0319

2
(G) (G) (R)

(G78.10421.2FL)
(G78.10421.2FL)
IX
Near GPU
N14P-GV2 only have one partition (FBA),
B
.F FBB is NC so you should not connect memory signals to FBB.--Kai 0313
B
CLKA1 CLKA0
1
R85 R128
(G) 162R2F-GP (G) 162R2F-GP
W
2
CLKA1# CLKA0# Group A

FBA_CKE0
CKE0
FBCLK Termination place on VRAM side CKE1 FBA_CKE1
FBA_RST
Reset
FBA_ODT0
ODT0
W
FBA_ODT1
ODT1
1
1
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP
(G) (G) (G) (G) (G)
R93 R606 R110 R567 R124

2
2
W
A A
<Core Design>
Wistron Corporation
Title
GPU_VRAM I/F(3/5)
A1
Madrid SA
5 4 3 2 1
5 4 3 2 1
3D3V_VGA_S0
L49
MMZ1608S301CTAH0-GP
3D3V_VGA_S0_DACA_VDD_16MIL 1 2
(R) 3D3V_VGA_S0 RN1 (G)
1
SRN2K2J-1-GP
X7R X7R X7R 1 4
1
2 3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC1U10V2KX-1GP
SC4D7U6D3V3KX-GP
R588 C414 C413 C421 C400 C415
2
(R) (R) (R) (R) (R)
10KR2J-3-GP
R90 1 (R) 20R2J-2-GP
6 1 SMB_DATA_GPU
20 GPU_SMDAT0
(G) 5 2
X7R, Under GPU. 60,61 DGPU_PWROK
Q11
VGA1N 14 OF 17 2N7002KDW-GP 4 3
4/17 DACA 84.2N702.A3F 9,10,13,21,22,46 SMB_CLK
GF108/GK107 GF108/GK107 2nd = 84.DM601.03F 9,10,13,21,22,46 SMB_DATA 3D3V_VGA_S0
GK208 GF117 GF117 GK208
AG10 R4 VGA_CRT_DDCCLK TP89 TPAD28 (G75.27002.F7C) SMB_CLK_GPU

DACA_VDD NC NC I2CA_SCL R5 VGA_CRT_DDCDATA TP92 TPAD28
DACA_VREF_AK12 AP9 NC I2CA_SDA
DACA_VREF TSEN_VREF 20 GPU_SMCLK0
DACA_RSET AP8 AM9 VGA_CRT_HSYNC TP7 TPAD28
DACA_RSET NC NC DACA_HSYNC AN9 VGA_CRT_VSYNC TP5 TPAD28 R89 1 (R) 2 0R2J-2-GP
NC DACA_VSYNC
1
(G) (G)
AK9 VGA_CRT_RED TP8 TPAD28

20130426 SWAP D/S connection by NV_Ryan R98
2K2R2J-2-GP
R97
2K2R2J-2-GP
NC DACA_RED
1
(G) VGA1Q 17 OF 17
1
AL10 VGA_CRT_GREEN TP10 TPAD28

NC 10/19 MISC1
DACA_GREEN
2
C41S R84 T4 SMB_CLK_GPU R94 1 (R) 20R2J-2-GP SMB_CLK
124R2F-U-GP AL9 VGA_CRT_BLUE TP9 TPAD28 I2CS_SCL T3 SMB_DATA_GPU R95 1 (R) 2 0R2J-2-GPSMB_DATA 3D3V_VGA_S0
CD1U10V2KX-5GP
NC DACA_BLUE I2CS_SDA
2
(G78.10421.2FL)
D D
2
R2 I2CC_SCL_PU
N14P-GS-A1-GP I2CC_SCL R3 I2CC_SDA_PU
(G) I2CC_SDA GPIO8_OVERT#
100KR2J-1-GP 1 (G) 2 R102
R7
TP_THERMDN K4 NC I2CB_SCL R6 GPIO9_ALERT# 1 (G) 2 R101
TPAD28 TP95 100KR2J-1-GP
THERMDN NC I2CB_SDA
TPAD28 TP12 TP_THERMDP K3 GPIO12_AC_DETECT
100KR2J-1-GP 1 (G) 2 R100
R80 THERMDP GF117
GK107/GF108
GK208
10KR2J-3-GP
1 2 N12P_JTAG_TCK AM10
TPAD28 TP6 (R) N12P_JTAG_TMS AP11 JTAG_TCK
TPAD28 TP4 N12P_JTAG_TDI AM11 JTAG_TMS
TPAD28 TP3 N12P_JTAG_TDO AP12 JTAG_TDI
1 2 N12P_GPIO_JTAG_TRST AN11 JTAG_TDO P6 GPIO0_FB_CLAMP
TP90 TPAD28 (G)
PLLVDD_PWR JTAG_TRST# GPIO0 M3 GPIO1_FBVDDQCTL
TP11 TPAD28 (G)
R83 (G) GPIO1 L6 GPIO2_BL_PWM
GPIO2 P5 GPIO3_PPEN_R
L48
(G68.00335.181) UNDER GPU 10KR2J-3-GP
GPIO3 GPIO4_BLEN
P7
1 2 GPIO4 L7 GPIO5_PWM_VID_BOOT_EN
TP94 TPAD28 (G)
1D05V_VGA_S0 GPIO5 GPIO6_FB_CLAMP_TGL_REQ
M7 TP91 TPAD28 (G)
GPIO6 N8 GPIO7_3D_STEREO
GK208 GPIO7 GPIO8_OVERT#
1
(G78.10421.2FL)
1
MHC1608S300QBP-GP (G) M1
OVERT GPIO8 GPIO9_ALERT#
SCD1U10V2KX-5GP
C419 C416 M2
GPIO9 GPIO10_MEM_VREF_CTL GPIO9_ALERT# 34,60
SC22U6D3V3MX-1-GP
L1
GPIO10 GPIO11_PWM_VID
2
M5
GPIO11 N3 GPIO12_AC_DETECT GPIO11_PWM_VID 60
GPIO12 M4 GPIO13_NVVDD_PSI
NEAR GPU VGA1O 15 OF 17
GPIO13 GPIO13_NVVDD_PSI 60 GPIO GF117
11/17 XTAL_PLL R8
GPIO16 NC GPIO16 GPIO16 P4
GPIO20 NC NC GPIO20 P1
(G68.00335.181) NC
L47 AD8 GPIO8 NC GPIO21 GPIO 0 FAN_PWM/FB_CLAMP/DEBUG Service
1 2 SP_PLLVDD_L AE8 PLLVDD GK208 GF117 GK107 GF108
1D05V_VGA_S0 SP_PLLVDD GPIO 1
M
MEM_VDD_CTL
1
SC1U10V2KX-1GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
100KR2J-1-GP
AD7
VID_PLLVDD NC
1
(G78.10421.2FL)
(G78.10421.2FL)
MHC1608S300QBP-GP GPIO 2
R603 R604 R600 R601 R106 UNUSED
1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
C417 (G) (G) C409 C408 GF108/GK107 GF117 (G) (G) (G) (G) (G)
(G78.10520.5FL) C403 C404 GPIO 3 UNUSED
GK208
2
2
SC22U6D3V3MX-1-GP
SC4D7U6D3V3KX-GP
N14P-GS-A1-GP
2
2
(G) GPIO 4 UNUSED
TPAD28 TP13 VIDEO_CLK_XTAL_SS H1 J4 N12P_XTAL_OUTBUFF
XTAL_SSIN XTAL_OUTBUFF GPIO 5 Reserved
H3 H2 GPIO 6 FB_CLAMP_TGL_REQ
XTAL_IN XTAL_OUT
1
N14P-GS-A1-GP GPIO 7 3DVision(UNUSED)
1
(G) 20PF 5% 50V +/-0.25PF 0402 R609

(G) 10KR2J-3-GP GPIO 8 GPU Overtemp
(G) R116
O
10KR2J-3-GP GPIO 9 GPU Thermal Alert
2
R123 (R)
2
27MHZ_IN 1 1MR2J-1-GP
2 27MHZ_OUT GPIO 10
Add CAP follow vendor suggestion--Kai 0314 FB Vref Control
remove L8603 / L8604 follow vendor suggestion--Kai 0319
2
R120 GPIO 11 NVVDD PWM_VID
390R2J-1-GP
X1 GPIO 12
(G) (G63.10234.1DL) PWR_Level AC Detect
3 2 GPIO 13 UNUSED(No Need to Set in VBIOS)
1
20140114 Madrid 1A Charles GPIO 14
change to 1K N/A on Package
4 1 27MHZ_OUT_R GPIO 15 N/A on Package
.C
GPIO 16 N/A on Package
XTAL-27MHZ-137-GP GPIO 17 N/A on Package
1
1
C88 (G) C87 GPIO 18 N/A on Package
SC15P50V2JN-2-GP SC15P50V2JN-2-GP
2
2
(G) GPIO 19 N/A on Package
GPIO 20 N/A on Package
GPIO 21
20130507 COST DOWN PART_Ryan N/A on Package
Strap
C C
AM
Strap pin name Logical strapping Logical strapping Logical strapping Logical strapping
name bit3# name bit2# name bit1# name bit0#
PCI_DEVID[4] SUB_VENDOR PCI_DVID[5] PCI_PLL_EN_TER_M

ROM_SCLK
0 0 1 0 GPU_ROM_SI for 1Gbit for 2Gbit for 1Gbit for 2Gbit
Hynix VRAM Hynix VRAM Samsung VRAM Samsung VRAM
RAM_CFG[0]=0 RAM_CFG[0]=0 RAM_CFG[0]=1 RAM_CFG[0]=1
RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] RAM_CFG[1]=1 RAM_CFG[1]=1 RAM_CFG[1]=1 RAM_CFG[1]=1
RAM_CFG[2]=0 RAM_CFG[2]=1 RAM_CFG[2]=0 RAM_CFG[2]=1
ROM_SI Hynix 0 0 1 0 RAM_CFG[3]=0 RAM_CFG[3]=0 RAM_CFG[3]=0 RAM_CFG[3]=0
Samsung 0 0 1 1
XCLK_417 Bar_size SMB_ALT_ADDR VGA_DEVICE
ROM_SO
T
GPU_ROM_SO VGA_DEVICE =1 (low bit)
1 0 0 1 SMB_ALT_ADDR =0
FB_0_BAR_SIZE =0
XCLK_417 =0 (High bit)
USER[3] USER[2] USER[1] USER[0]
STRAP0
1 1 1 1
3GPO_PADCFG[3] 3GPO_PADCFG[2] 3GPO_PADCFG[1] 3GPO_PADCFG[0]
LA
STRAP1 GPU_ROM_SCLK PEX_PLL_EN_TERM =0
SLOT_CLK_CFG =1
0 1 1 0 SUB_VENDOR =0
PCI_DEVID[4] =1
N11P Fermi QS 1
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP2
1 0 0 1
SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

STRAP3
0 0 0 0
RESERVED PCI_SPEED_CHANGE_GEN3 PCI_MAX_SPEED DP_PLL_VDD33V

STRAP4
0 0 1 1
IX
External BIOS ROM 3D3V_VGA_S0
Reserve EEPROM for VBIOS
U30
1 8
3D3V_VGA_S0 2 CS# VCC 7
B 3
4
SO/SIO1
WP#
GND
HOLD#
SCLK
SI/SIO0
6
5
.F B
1
R627
MX25L1006EMI-10G-GP
(R)10KR2F-2-GP (R72.02510.001)
C55 (R) Modify As winbom 1M
2
1 2
ROM_CS_R*
R624 1 (R) 2 SCD1U16V2KX-3GP
33R2J-2-GP
ROM_SI_R
R625 1 (R) 2
33R2J-2-GP
ROM_SCLK_R
R615 1 (R) 2
W
VGA1P 16 OF 17 33R2J-2-GP
12/17 MISC2
H6 ROM_CS*
ROM_CS#
H5 ROM_SI
ROM_SI H7 ROM_SO
STRAP0 J2 ROM_SO H4 ROM_SCLK
STRAP1 J7 STRAP0 ROM_SCLK

STRAP2 J6 STRAP1
STRAP3 J5 STRAP2 3D3V_VGA_S0
J3 STRAP3 NC
STRAP4
STRAP4 NC
GK107/GF117 GF108
GK208
W
L2
BUFRST#
STRAP_REF0_GND_N9 J1 L3
MULTI_STRAP_REF CEC 20131029 Madrid SA Charles
1
CEC IS NC FOR (R)

R621
10KR2F-2-GP
R626
4K99R2F-L-GP
R616
4K99R2F-L-GP
With GB4B-128: NV Review
Unstuff R616, Stuff R611 with 4.99K
1
GK107/GK208/GF117 (R) (R)

(G)
Unstuff R626, Stuff R617 with 4.99K
2
R115 ROM_SI
ROM_SO
40K2R2F-GP
N14P-GS-A1-GP ROM_SCLK The strapping value of ROM_SI depends on which memory part will be use.
Change R111 to 50K
2
(G)
1
R619 R617 R611

Unstuff R605, Unstuff R610, Unstuff R607, Unstuff R113
W
4K99R2F-L-GP 4K99R2F-L-GP 4K99R2F-L-GP

(G) (G) (G)
2
13/11/02 modify VRAM strap R619 (default set Hynix)--Kai

Hynix H5TC4G63AFR-11C
R619=4.99K(64.49915.6DL)
3D3V_VGA_S0
3D3V_VGA_S0 THERMAL PROTECTION
Samsung K4W4G1646D-BC1A 20131029 Madrid SA Charles 3D3V_VGA_S0
R619=15K(64.15025.6DL) NV Review
1
R623
R108
SUB_VENDOR Strap--ROM_SI_D3
1
1
R111 45K3R2F-L-GP (R) (R) 4K99R2F-L-GP (G)
45K3R2F-L-GP C86
(G64.49925.6DL) (R) R613 (R) R618 SCD1U16V2ZY-2GP 3D3V_VGA_S0
2
2
34K8R2F-1-GP 24K9R2F-L-GP STRAP3 20131024 Madrid SA Charle
SMB_ALT_ADDR Strap--ROM_SLK_D4 20131029 Madrid SA Charles
2
2
STRAP0 STRAP4 PMBS3906-GP 1 GPU_3D3V_S0_THERM R114 1 2

NV Review 2 0R2J-2-GPGPU_THERM_SHUTDOWN*_R Q14
STRAP1
7,12 H_THERMTRIP_N R119 1 2K2R2J-2-GP
1
STRAP2 R607 R113 (R) (G84.T3906.E11) GPU_PLTRST

(G)
3
VGA_DEVICE Strap--ROM_SO_C4
4K99R2F-L-GP 45K3R2F-L-GP
GPU_3D3V_S0_THERM_2
1
R605 (R) (R) R118 1 2 0R2J-2-GP R103 1 2 GPIO8_OVERT#

60 GPU_THERM_SHUTDOWN*
45K3R2F-L-GP R610 2K2R2J-2-GP
D
A (R) R112 (R) (R) 15KR2F-GP A
(G)
2
3
2KR2J-1-GP (G) Q12
Q13 1 GPU_THERM_SHUTDOWN*_1 2 1 2 R125 1GPU_THERM_SHUTDOWN*_2 1 Q15 R117
2
PMBS3904-1-GP 10KR2J-3-GP PMBS3904-1-GP (G84.2N702.J31) G PLTRST_N_1A 2 1

PLTRST_GPU# 20,51
(G84.T3904.H11) (G) (G84.T3904.H11) 2N7002A-7-GP (G)
2
2
R127 1KR2J-1-GP
1
10KR2J-3-GP
S
1
1
C90 (G)
1
C89 SC1KP50V2JN-2GP C84
PCIE_MAX_SPEED Strap--STRAP4
2
SC1KP50V2JN-2GP (G64.33025.6DL) (G78.10224.2FL) SC100P50V2JN-3GP

2
2
Unstuff R8634, Stuff R8635 with 10K.--Kai 0313 (G78.10224.2FL) R126
33KR2J-3-GP
R8635 should be 15K--Kai 0314 Change R8619 to 45.3K.--Kai 0313
2
<Core Design>
Wistron Corporation
Title
GPU_GPIO/STRAP(4/5)
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
EDP 50A
(TDP 37W)
VGA1G 7 OF 17
VGA_CORE 16/17 GND_2/2
VGA1F 6 OF 17 N19 T28

VGA1H N2 GND_141 GND_170 T32
15/17 GND_1/2
8 OF 17 A2 AM25 N21 GND_142 GND_171 T5
Under GPU 13/17 NVVDD AA17 GND_1 GND_71 AN1 N23 GND_143 GND_172 T7
AA18 GND_5 GND_72 AN10 N28 GND_144 GND_173 U12
AA12 AA20 GND_6 GND_73 AN13 N30 GND_145 GND_174 U14
AA14 VDD_1 AA22 GND_7 GND_74 AN16 N32 GND_146 GND_175 U16
D D
AA16 VDD_2 AB12 GND_8 GND_75 AN19 N33 GND_147 GND_176 U19
AA19 VDD_3 AB14 GND_9 GND_76 AN22 N5 GND_148 GND_177 U21
VDD_4 GND_10 GND_77 GND_149 GND_178
1
1
AA21 AB16 AN25 N7 U23
C446 C435 C438 C439 C436 C428 C429 C432 C433 C434 AA23 VDD_5 AB19 GND_11 GND_78 AN30 P13 GND_150 GND_179 V12
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
AB13 AB2 AN34 P15 V14
2
2
AB15 VDD_7 AB21 GND_13 GND_80 AN4 P17 GND_152 GND_181 V16
(G) (G) (G) (G) (G) (G) (G) (G) (G) (G) AB17 VDD_8 A33 GND_14 GND_81 AN7 P18 GND_153 GND_182 V19
AB18 VDD_9 AB23 GND_2 GND_82 AP2 P20 GND_154 GND_183 V21
AB20 VDD_10 AB28 GND_15 GND_83 AP33 P22 GND_155 GND_184 V23
AB22 VDD_11 AB30 GND_16 GND_84 B1 R12 GND_156 GND_185 W13
AC12 VDD_12 AB32 GND_17 GND_85 B10 R14 GND_157 GND_186 W15
AC19 VDD_15 AC13 GND_20 GND_88 B28 R21 GND_160 GND_189 W20
M
AC21 VDD_16 AC15 GND_21 GND_89 B31 R23 GND_161 GND_190 W22
AC23 VDD_17 AC17 GND_22 GND_90 B34 T13 GND_162 GND_191 W28
M12 VDD_18 AC18 GND_23 GND_91 B4 T15 GND_163 GND_192 Y12
Under GPU M14 VDD_19 AA13 GND_24 GND_92 B7 T17 GND_164 GND_193 Y14
M16 VDD_20 AC20 GND_3 GND_93 C10 T18 GND_165 GND_194 Y16
M19 VDD_21 AC22 GND_25 GND_94 C13 T2 GND_166 GND_195 Y19
M21 VDD_22 AE2 GND_26 GND_95 C19 T20 GND_167 GND_196 Y21
O
1
1
C665 C664 C418 C412 C411 C407 M23 AE28 C22 T22 Y23
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
N13 AE30 C25
N15 VDD_25 AE32 GND_29 GND_98 C28
2
2
N17 VDD_26 AE33 GND_30 GND_99 C7
N18 VDD_27 AE5 GND_31 GND_100 D2
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
N20 VDD_28 AE7 GND_32 GND_101 D31
N22 VDD_29 AH10 GND_33 GND_102 D33
.C
P12 VDD_30 AA15 GND_34 GND_103 E10 AG11 AH11
P14 VDD_31 AH13 GND_4 GND_104 E22 GND_F GND_H
P16 VDD_32 AH16 GND_35 GND_105 E25
P19 VDD_33 AH19 GND_36 GND_106 E5
P21 VDD_34 AH2 GND_37 GND_107 E7
P23 VDD_35 AH22 GND_38 GND_108 F28
R13 VDD_36 AH24 GND_39 GND_109 F7
R15 VDD_37 AH28 GND_40 GND_110 G10
NEAR TO GPU
AM
R17 VDD_38 AH29 GND_41 GND_111 G13 C16
C C
R18 VDD_39 AH30 GND_42 GND_112 G16 GND_OPT_1 W32
R20 VDD_40 AH32 GND_43 GND_113 G19 GND_OPT_2
R22 VDD_41 AH33 GND_44 GND_114 G2 Optional CMD GNDs (2)
T12 VDD_42 AH5 GND_45 GND_115 G22 NC for 4-Lyr cards
VDD_43 GND_46 GND_116
1
1
C447 (G78.22610.5BL)
SC22U4V3MX-GP
C450 (G78.22610.5BL)
SC22U4V3MX-GP
C445 (G78.22610.5BL)
SC22U4V3MX-GP
C425 (G78.22610.5BL)
SC22U4V3MX-GP
C401 (G78.22610.5BL)
SC22U4V3MX-GP
C448 (G78.22610.5BL)
SC22U4V3MX-GP
C37
SC22U4V3MX-GP
T14 AH7 G25

T16 VDD_44 AJ7 GND_47 GND_117 G28 N14P-GS-A1-GP
T19 VDD_45 AK10 GND_48 GND_118 G3 (G)
2

(R78.22610.5BL)
T21 AK7 G30

T23 VDD_47 AL12 GND_50 GND_120 G32
U13 VDD_48 AL14 GND_51 GND_121 G33
U15 VDD_49 AL15 GND_52 GND_122 G5
T
U17 AL17 G7
U18 VDD_51 AL18 GND_54 GND_124 K2
U20 VDD_52 AL2 GND_55 GND_125 K28
U22 VDD_53 AL20 GND_56 GND_126 K30
V13 VDD_54 AL21 GND_57 GND_127 K32
V15 VDD_55 AL23 GND_58 GND_128 K33
LA
V17 VDD_56 AL24 GND_59 GND_129 K5 VGA1I 9 OF 17
V18 VDD_57 AL26 GND_60 GND_130 K7 9/17 XVDD
V20 VDD_58 AL28 GND_61 GND_131 M13
1
V22 AL30 M15

NEAR TO GPU VDD_60 GND_63 GND_133
CONFIGURABLE
SC4D7U6D3V3KX-GP
C440 C441 C442 C427 C426 W12 AL32 M17 POWER

SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
W14 AL33 M18 CHANNELS

2
W16 VDD_62 AL5 GND_65 GND_135 M20 U1

(G) (G) (G) (G) (G) W19 VDD_63 AM13 GND_66 GND_136 M22 XVDD_1 U2
W21 VDD_64 AM16 GND_67 GND_137 N12 XVDD_2 U3
W23 VDD_65 AM19 GND_68 GND_138 N14 XVDD_3 U4
IX
Y13 VDD_66 AM22 GND_69 GND_139 N16 XVDD_4 U5
Y15 VDD_67 GND_70 GND_140 XVDD_5 U6
Y17 VDD_68 XVDD_6 U7
Y18 VDD_69 XVDD_7 U8
Y20 VDD_70 N14P-GS-A1-GP XVDD_8
Y22 VDD_71 (G)
VDD_72 V1
XVDD_9 V2
C449 C36 N14P-GS-A1-GP
.F XVDD_10
XVDD_11
V3
1
B (G) (R) (G) V4 B

XVDD_12 V5
XVDD_13
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
V6
2
XVDD_14 V7
XVDD_15 V8
XVDD_16
W
W2
XVDD_17 W3
NEAR TO GPU XVDD_18 W4
XVDD_19 W5
XVDD_20 W7
XVDD_21 W8
VGA1E 5 OF 17 XVDD_22
W
17/17 NC/VDD33
3D3V_VGA_S0
GK208
GK107
GF117 Y1
AJ28 J8 XVDD_23 Y2
NC#AJ28 3V3MISC 3V3MISC_1 XVDD_24
C15 K8 Y3
NC#C15 3V3MISC 3V3MISC_2 XVDD_25
D19 Y4
NC#D19 XVDD_26
1
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
D20 L8 Y5
W
TC2 C370 D23 NC#D20 VDD33_1 M8 XVDD_27 Y6

NEAR TO GPU NC#D23 VDD33_2 X7R X7R X7R XVDD_28
1
1
SC47U6D3V5MX-1-GP
SE470UF2VDM-GP
(R) D26 Y7
2
H31 NC#D26 C453 C462 C471 C452 C393 XVDD_29 Y8

NC#H31 XVDD_30
SC1U6D3V2KX-GP
SC4D7U6D3V3KX-GP
V32
2
2
NC#V32
AC6 (G) (G) AA1
(G78.10421.2FL)
(G78.10421.2FL)
(G78.10421.2FL)
(R) AJ4 DNU#AC6 DO NOT XVDD_31 AA2

AJ5 DNU#AJ4 CONNECT XVDD_32 AA3
AL11 DNU#AJ5 THESE XVDD_33 AA4
T8 DNU#AL11 PINS XVDD_34 AA5
DNU#T8 XVDD_35 AA6
XVDD_36 AA7
N14P-GS-A1-GP XVDD_37 AA8
(G) XVDD_38
A
Change C8709 to 0.1uF, N14P-GS-A1-GP
(G) A
Add additional 0.1uF at 3V3MISC..--Kai 0314
<Core Design>
0.1U Under GPU
Wistron Corporation
4.7U NEAR TO GPU 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
1U NEAR TO GPU
GPU_PWR/GND(5/5)
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
CHANNEL A:2GB DDR3

MICRON 256x16 900MHz 4Gb
1D5V_VGA_S0
MT41K256M16HA-107G:E LF+HF
VRAM2
MDA[23..16] 53
KN.00404.001
K8 E3 MDA23
K2 VDD DQL0 F7 MDA19
N1 VDD
VDD
DQL1
DQL2
F2 MDA22 Hynix 256x16 900MHz 4Gb
R9
B2 VDD DQL3
F8
H3
MDA16
MDA21
H5TQ4G63MFR-11C
D D
D9 VDD
VDD
DQL4
DQL5
H8 MDA18 KN.0040G.006
G7 G2 MDA20
R1 VDD DQL6 H7 MDA17
N9 VDD DQL7
VDD MDA[15..8] 53
D7 MDA12
A8 DQU0 C3 MDA8
A1 VDDQ DQU1 C8 MDA15
C1 VDDQ DQU2 C2 MDA10
C9 VDDQ DQU3 A7 MDA13
D2 VDDQ DQU4 A2 MDA9
E9 VDDQ DQU5 B8 MDA14
VRAM1_VREF F1 VDDQ DQU6 A3 MDA11
VDDQ DQU7
M
H9
H2 VDDQ C7
VDDQ DQSU QSAP_1 53
B7
DQSU# QSAN_1 53
VRAM1_VREF H1
M8 VREFDQ F3
VRAM_ZQ2 VREFCA DQSL QSAP_2 53
L8 G3
ZQ DQSL# QSAN_2 53
O
2
K1
ODT FBA_ODT0 53,58
R121 53,57,58,59 FBA_A0 N3
P7 A0
243R2F-2-GP 53,57,58,59 FBA_A1 A1
(G) 53,57,58,59 FBA_A2 P3 L2
A2 CS# -FBA_CS0 53,58
53,57,58,59 FBA_A3 N2 T2
.C
FBA_RST 53,57,58,59
1
P8 A3 RESET#
53,57,58,59 FBA_A4 A4
53,57,58,59 FBA_A5 P2
R8 A5 M7
53,57,58,59 FBA_A6 A6 NC#M7 FBA_A15 53,57,58,59
53,57,58,59 FBA_A7 R2 L9
T8 A7 NC#L9 L1
53,57,58,59 FBA_A8 A8 NC#L1
53,57,58,59 FBA_A9 R3 J9
A9 NC#J9
C Need to connect 53,57,58,59 FBA_A10 L7 J1 C
AM
R7 A10/AP NC#J1
53,57,58,59 FBA_A11
FBA_CMD4 to 53,57,58,59 FBA_A12 N7 A11
A12/BC#
T3 J8
FBA_A14 53,57,58,59
53,57,58,59
FBA_A13
FBA_A14 T7 A13 VSS M1
A14 VSS
for support VSS
M9
J2
256Mx16 53,57,58,59 FBA_BA0 M2 VSS P9
BA0 VSS
memory--Kai 0315 53,57,58,59 FBA_BA1 N8
M3 BA1 VSS
G8
B3 1D5V_VGA_S0
53,57,58,59 FBA_BA2 BA2 VSS T1
VSS A9
T
VSS
1
J7 T9
53,58 CLKA0 CK VSS
K7 E1 VRAM1_VREF R602
53,58 CLKA0# CK# VSS P1 (G) 1K33R2F-GP
K9 VSS VRAM1_VREF
53,58 FBA_CKE0 CKE
LA
G1
VSSQ
2
F9
VSSQ
2
D3 E8 VRAM1_VREF
53 DQMA1 DMU VSSQ
E7 E2 C458
53 DQMA2 DML VSSQ
1
D8 SCD01U50V2KX-1GP
1
VSSQ
2
D1 R612
L3 VSSQ B9 1K33R2F-GP C465
53,57,58,59 -FBA_WE W E# VSSQ
K3 B1 (G) SCD01U50V2KX-1GP (G)
53,57,58,59 -FBA_CAS CAS# VSSQ
1
J3 G9
IX
53,57,58,59 -FBA_RAS RAS# VSSQ
2
(G)
K4W4G1646B-HC11-GP
(GKN.0040G.002) .F
B B
OBS,follow Lily_Tripoli--Kai 0311
W
1D5V_VGA_S0 DG requires 4x0.1uF and 8x1.0uF per
VRAM chip
W
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
FOR VRAM1
1
1D5V_VGA_S0
C92 C91
2
(G78.10421.2FL)
(G78.10421.2FL)
SC10U6D3V3MX-GP
1
C423
2
(G)
A CLOSE TO THE MEMORY A

1
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
<Core Design>
C424 C58 C69 C479
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
2
Wistron Corporation
Title
GPU-VRAM1 (1/4)
Custom
Add VRAM decoupling cap--Kai 0315 Madrid SA
5 4 3 2 1
5 4 3 2 1
CHANNEL A:2GB DDR3

1D5V_VGA_S0
VRAM1
MDA[63..56] 53
K8 E3 MDA58
K2 VDD DQL0 F7 MDA57
VDD DQL1
N1
VDD DQL2
F2 MDA62 MT41K256M16HA-107G:E LF+HF
R9 F8 MDA60
B2 VDD DQL3 H3 MDA63 KN.00404.001
D9 VDD DQL4 H8 MDA61
G7 VDD DQL5 G2 MDA56
R1 VDD
VDD
DQL6
DQL7
H7 MDA59 Hynix 256x16 900MHz 4Gb
N9
VDD D7 MDA51
MDA[55..48] 53 H5TQ4G63MFR-11C
D D
A8
VDDQ
DQU0
DQU1
C3 MDA53 KN.0040G.006
A1 C8 MDA50
F1 VDDQ DQU6 A3 MDA55
VRAM3_VREF H9 VDDQ DQU7
H2 VDDQ C7
VDDQ DQSU QSAP_6 53
B7 QSAN_6 53
VRAM3_VREF H1 DQSU#
M8 VREFDQ F3 QSAP_7 53
M
VRAM_ZQ3 L8 VREFCA DQSL G3
ZQ DQSL# QSAN_7 53
K1
ODT FBA_ODT1 53,59
2
53,56,58,59 FBA_A0 N3
R92 P7 A0
53,56,58,59 FBA_A1 A1
243R2F-2-GP P3 L2
O
53,56,58,59 FBA_A2 A2 CS# -FBA_CS1 53,59
(G) 53,56,58,59 FBA_A3 N2 T2
A3 RESET# FBA_RST 53,56,58,59
53,56,58,59 FBA_A4 P8
1
P2 A4
53,56,58,59 FBA_A5 A5
53,56,58,59 FBA_A6 R8 M7 FBA_A15 53,56,58,59
R2 A6 NC#M7 L9
53,56,58,59 FBA_A7
.C
T8 A7 NC#L9 L1
53,56,58,59 FBA_A8 A8 NC#L1
53,56,58,59 FBA_A9 R3 J9
L7 A9 NC#J9 J1
53,56,58,59 FBA_A10 A10/AP NC#J1
Need to connect 53,56,58,59 FBA_A11 R7
N7 A11
53,56,58,59 FBA_A12
C FBA_CMD4 to 53,56,58,59 FBA_A13 T3 A12/BC#
A13 VSS
J8 C
T7 M1
FBA_A14 53,56,58,59 FBA_A14
AM
A14 VSS M9
VSS
for support M2 VSS
J2
P9
53,56,58,59 FBA_BA0
256Mx16 53,56,58,59 FBA_BA1 N8 BA0 VSS G8 1D5V_VGA_S0
BA1 VSS
memory--Kai 0315 53,56,58,59 FBA_BA2 M3
BA2 VSS
B3
T1
VSS
1
A9
J7 VSS T9 R595
53,59 CLKA1 CK VSS
K7 E1 VRAM3_VREF (G) 1K33R2F-GP
53,59 CLKA1# CK# VSS P1
VSS
T
K9
53,59 FBA_CKE1
2
CKE G1 VRAM3_VREF
VSSQ F9 VRAM3_VREF
D3 VSSQ E8
53 DQMA6 DMU VSSQ
2
LA
53 DQMA7 E7 E2
DML VSSQ
2
D8 R88 C394
VSSQ D1 (G) 1K33R2F-GP C410 SCD01U50V2KX-1GP
1
L3 VSSQ B9
53,56,58,59 -FBA_WE SCD01U50V2KX-1GP
1
K3 WE# VSSQ B1
53,56,58,59 -FBA_CAS
2
J3 CAS# VSSQ G9 (G)
53,56,58,59 -FBA_RAS RAS# VSSQ (G)
K4W4G1646B-HC11-GP
IX
(GKN.0040G.002)
B OBS,follow Lily_Tripoli--Kai 0311 FB CMD mapping Mode D-N12x B

.F
VRAM SAMSUNG 1Gb S72.41646.Q0U
1D5V_VGA_S0 VRAM HYNIX 1Gb H72.51G63.H0U
W
FOR VRAM3
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
CLOSE TO THE MEMORY

1
C42 C94
1D5V_VGA_S0
2
(G78.10421.2FL)
(G78.10421.2FL)
W
SC10U6D3V3MX-GP
1
C34
(G)
2
1
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A
C62 C38 C39 C56 CLOSE TO THE MEMORY <Core Design> A
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
2
Wistron Corporation
Title
GPU-VRAM3 (2/4)
Add VRAM decoupling cap--Kai 0315 Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
1D5V_VGA_S0
VRAM4
CHANNEL B:2GB DDR3
K8 E3 MDA26
MDA[31..24] 53 MICRON 256x16 900MHz 4Gb
K2 VDD
VDD
DQL0
DQL1
N1 F2 MDA28
R9 VDD DQL2 F8 MDA30 KN.00404.001
B2 VDD DQL3 H3 MDA24
G7 VDD
VDD
DQL5
DQL6
G2 MDA25 Hynix 256x16 900MHz 4Gb
R1 H7
D N9 VDD DQL7
MDA29
H5TQ4G63MFR-11C D
MDA[7..0] 53
VDD
DQU0
D7 MDA7 KN.0040G.006
A8 C3 MDA0
A1 VDDQ DQU1 C8 MDA6
VRAM1_VREF F1 VDDQ DQU6 A3 MDA1
H9 VDDQ DQU7
H2 VDDQ C7
VDDQ DQSU QSAP_0 53
B7 QSAN_0 53
M
VRAM1_VREF H1 DQSU#
M8 VREFDQ F3
VRAM_ZQ1 VREFCA DQSL QSAP_3 53
L8 G3 QSAN_3 53
ZQ DQSL#
2
K1
ODT FBA_ODT0 53,56
R122 N3
O
53,56,57,59 FBA_A0 A0
243R2F-2-GP 53,56,57,59 FBA_A1 P7
(G) P3 A1 L2
53,56,57,59 FBA_A2 A2 CS# -FBA_CS0 53,56
53,56,57,59 FBA_A3 N2 T2
FBA_RST 53,56,57,59
1
P8 A3 RESET#
53,56,57,59 FBA_A4 A4
53,56,57,59 FBA_A5 P2
.C
R8 A5 M7
53,56,57,59 FBA_A6 A6 NC#M7 FBA_A15 53,56,57,59
53,56,57,59 FBA_A7 R2 L9
T8 A7 NC#L9 L1
53,56,57,59 FBA_A8 A8 NC#L1
53,56,57,59 FBA_A9 R3 J9
L7 A9 NC#J9 J1
53,56,57,59 FBA_A10 A10/AP NC#J1
N7 A11
53,56,57,59 FBA_A12
AM
C FBA_CMD4 to 53,56,57,59 FBA_A13 T3 A12/BC#
A13 VSS
J8 C
T7 M1
FBA_A14 53,56,57,59 FBA_A14 A14 VSS M9
VSS
for support M2 VSS
J2
P9
53,56,57,59 FBA_BA0
256Mx16 53,56,57,59 FBA_BA1 N8 BA0
BA1
VSS
VSS
G8
BA2 VSS
B3
T1
VSS A9
J7 VSS T9
53,56 CLKA0 CK VSS
T
53,56 CLKA0# K7 E1
CK# VSS P1
K9 VSS
53,56 FBA_CKE0 CKE G1
VSSQ
LA
F9
D3 VSSQ E8
53 DQMA0 DMU VSSQ
53 DQMA3 E7 E2
DML VSSQ D8
VSSQ D1 VRAM1_VREF
L3 VSSQ B9
53,56,57,59 -FBA_WE WE# VSSQ
K3 B1
53,56,57,59 -FBA_CAS CAS# VSSQ
2
J3 G9
53,56,57,59 -FBA_RAS RAS# VSSQ C85
IX
SCD01U50V2KX-1GP
1
K4W4G1646B-HC11-GP
(GKN.0040G.002)
.F (G)
B OBS,follow Lily_Tripoli--Kai 0311 B

N14P-GV2 only have one partition (FBA)--Kai 0313
W
1D5V_VGA_S0
W
DG requires 4x0.1uF and 8x1.0uF per

VRAM chip
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
1
C397 C459
FOR VRAM2 1D5V_VGA_S0
2
2
W
(G78.10421.2FL)
(G78.10421.2FL)
SC10U6D3V3MX-GP
CLOSE TO THE MEMORY
1
C473
2
(G)
CLOSE TO THE MEMORY

1
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A A
<Core Design>
C455 C470 C35 C437
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
2
Wistron Corporation
Title
GPU-VRAM2 (3/4)
Madrid SA
5 4 3 2 1
5 4 3 2 1
CHANNEL B:2GB DDR3

1D5V_VGA_S0
VRAM3
MDA[47..40] 53
K8 E3
K2 VDD DQL0 F7
MDA43
MDA42
N1 VDD
VDD
DQL1
DQL2
R9 F8 MDA40
B2 VDD DQL3 H3 MDA46 KN.00404.001
G7 VDD DQL5 G2 MDA44
R1 VDD
VDD
DQL6
DQL7
H7 MDA47 Hynix 256x16 900MHz 4Gb
D
N9
VDD D7 MDA33
MDA[39..32] 53 H5TQ4G63MFR-11C D
A8
VDDQ
DQU0
DQU1
C3 MDA37 KN.0040G.006
A1 C8 MDA32
F1 VDDQ DQU6 A3 MDA38
VRAM3_VREF H9 VDDQ DQU7
H2 VDDQ C7
VDDQ DQSU QSAP_4 53
B7
DQSU# QSAN_4 53
M
VRAM3_VREF H1
M8 VREFDQ F3
VREFCA DQSL QSAP_5 53
VRAM_ZQ4 L8 G3
ZQ DQSL# QSAN_5 53
K1
ODT FBA_ODT1 53,57
2
N3
O
53,56,57,58 FBA_A0 A0
R574 53,56,57,58 FBA_A1 P7
P3 A1 L2
243R2F-2-GP 53,56,57,58 FBA_A2 A2 CS# -FBA_CS1 53,57
(G) 53,56,57,58 FBA_A3 N2 T2
A3 RESET# FBA_RST 53,56,57,58
53,56,57,58 FBA_A4 P8
1
P2 A4
53,56,57,58 FBA_A5
.C
R8 A5 M7
53,56,57,58 FBA_A6 A6 NC#M7 FBA_A15 53,56,57,58
53,56,57,58 FBA_A7 R2 L9
T8 A7 NC#L9 L1
53,56,57,58 FBA_A8 A8 NC#L1
53,56,57,58 FBA_A9 R3 J9
L7 A9 NC#J9 J1
53,56,57,58 FBA_A10 A10/AP NC#J1
N7 A11
AM
C 53,56,57,58 FBA_A12 C
FBA_CMD4 to 53,56,57,58 FBA_A13 T3 A12/BC#
A13 VSS
J8
T7 M1
FBA_A14 53,56,57,58 FBA_A14 A14 VSS M9
VSS
for support M2 VSS
J2
P9
53,56,57,58 FBA_BA0
256Mx16 53,56,57,58 FBA_BA1 N8 BA0
BA1
VSS
VSS
G8
BA2 VSS
B3
T1
VSS A9
J7 VSS T9
T
53,57 CLKA1 CK VSS
53,57 CLKA1# K7 E1
CK# VSS P1
K9 VSS
53,57 FBA_CKE1 CKE G1
LA
VSSQ F9
D3 VSSQ E8 VRAM3_VREF
53 DQMA4 DMU VSSQ
E7 E2
53 DQMA5 DML VSSQ D8
VSSQ
2
D1
L3 VSSQ B9 C54
53,56,57,58 -FBA_W E WE# VSSQ
K3 B1 SCD01U50V2KX-1GP
53,56,57,58 -FBA_CAS
1
J3 CAS# VSSQ G9
IX
53,56,57,58 -FBA_RAS RAS# VSSQ
(G)
K4W 4G1646B-HC11-GP
(GKN.0040G.002) .F
B B
OBS,follow Lily_Tripoli--Kai 0311
CLOSE TO THE MEMORY
1D5V_VGA_S0
W
1D5V_VGA_S0
FOR VRAM4
1
W
C44
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SC10U6D3V3MX-GP
1
(G)
2
C384 C74
2
(G78.10421.2FL)
(G78.10421.2FL)
W
CLOSE TO THE MEMORY

1
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A <Core Design> A
C406 C33 C72 C93
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
(G78.10520.5FL)
2
Wistron Corporation
Title
GPU-VRAM4 (4/4)
Madrid SA
5 4 3 2 1
5 4 3 2 1

PC4,PC5,PC6,PC7,PC9,PC10
5V_S0 Always mount for UMA EMI solution
84.00172.037 SIR172DP
5V_S0
Vgs @ 4.5V, VIN RIPPLE CURRENT Imax=5.86.A DCBATOUT_VGA_CORE DCBATOUT DCBATOUT_VGA_CORE
Id = 12.9A,
1
(G) Rds(on) = 10.3~12.4mohm,
PR115 0R0805-PAD 2 1 PR96
2D2R3J-2-GP
1
(G) 0R0805-PAD 2 1 PR97
2
PR9
D 2 1 PR6 D
2D2R5J-1-GP 84.SRA12.037 SIRA12DP (G) (G) 0R0805-PAD
1
PC10 PC105 PC5 PC53 PC6
Vgs @ 4.5V,
5
6
7
8
5
6
7
8
SCD1U25V3KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
(G) 0R0805-PAD 2 1 PR5
Id = 20A,
2
1
D
D
D
D
D
D
D
D
PC73 (G84.A14DP.037)
2
SC4D7U10V3KX-GP Rds(on) = 4.4~6.0mohm, PU3 PU10
1
SIR172ADP-T1-GE3-GP
SIR172ADP-T1-GE3-GP
(G) (R)
1
PU9 PC8 PTC1
SE47U25VM-14-GP
SC1U10V3KX-3GP 4 4
2
NCP81172_VCC 15 21 NCP81172_PVCC
S
S
S
S
S
S
2
VCC PVCC
3
2
1
3
2
1
25 22 (G) (G84.A14DP.037) Unmount PTC1 ; Add PC105
GND PGND PR127 [Layout] PC105 place back to PC5
2D2R5J-1-GP VDDC_PWR
2 PWR_VGA_CORE_UGATE1 1 2PWR_VGA_CORE_UGATE1_R
HG1 PWR_VGA_CORE_UGATE1_R
0.36uH, DCR=1.05~1.2mohm, Idc=30A
1 (G)
PWR_VGA_CORE_EN 3 BST1 24 PR110 (G)
PWR_VGA_CORE_PSI 4 EN PH1 23 2D2R5J-1-GP PC61 SCD1U50V3KX-GP (G)
PWR_VGA_CORE_PGOOD 16 PSI LG1 PWR_VGA_CORE_BOOT1 1 2PWR_VGA_CORE_BOOT1_1 1 2 PL4 1 2IND-D36UH-19-GP
PWR_VGA_CORE_TALERT 14 PGOOD
(R) PWR_VGA_CORE_VID 5 TALERT# 17 PWR_VGA_CORE_PHASE1
PR17 2 1 100KR2F-L1-GP (G) VID HG2 18 VDDC_PWR VGA_CORE
3D3V_VGA_S0 BST2
2
PR19 2 1 100KR2F-L1-GP NCP81172_TSENSE 13 19 (G)
3D3V_VGA_S0 TSNS PH2
5
6
7
8
1
PR15 20 PWR_VGA_CORE_LGATE1 (G84.010DP.037) PR125 (G) (G) (G)
LG2
5
6
7
8
D
D
D
D
1 2 0R0402-PAD PR21 (G) (G) PQ6 (G84.010DP.037) 2D2R5J-1-GP PC25 PTC6 PTC7 0R0603-PAD 2 1 PR142
54,61 DGPU_PWROK
D
D
D
D
E820U2D5VM-7-GP
PWR_VGA_CORE_VREF
SIRA12DP-T1-GE3-GP
E820U2D5VM-7-GP
1 2 0R0402-PAD PR24 1 2 20KR2F-L-GP 8 PR131 PQ1
SC22U6D3V5MX-2GP
1NCP81172_PH1_SB
34,54 GPIO9_ALERT#
2
PWR_VGA_CORE_REFIN VREF NCP81172_FBRTN
SIRA12DP-T1-GE3-GP
7 10 2D2R5J-1-GP 0R0603-PAD 2 1 PR143
1
6 REFIN FBRTN 11 NCP81172_FB PWR_VGA_CORE_UGATE2 1 2
VIDBUF FB
1
(R) (G) 9 12 NCP81172_COMP (G) 4 0R0603-PAD 2 1 PR36
G
1 2 SC1000P50V3JN-GP-U FS COMP 4
S
S
S
PC76 PC22 PR109
G
SCD1U25V2KX-GP 0R0603-PAD 2 1 PR35
M S
S
S
2D2R5J-1-GP
PWR_VGA_CORE_REFADJ
2
3
2
1
1
PWR_VGA_CORE_TON
NCP81172MNTXG-GP-U PWR_VGA_CORE_BOOT2 1 2 (G)
3
2
1
PR123 (G) (G) PC71 0R0603-PAD 2 1 PR136
PWR_VGA_CORE_BOOT2_1
PWR_VGA_CORE_VREF_1
54 GPIO11_PWM_VID 1 2 0R0402-PAD PR27 SC1500P50V3KX-GP madrid 20131017 Charles
PWR_VGA_CORE_PHASE2 0R0603-PAD 2 1 PR137
2KR2F-3-GP 330uF/2.5V, ESR=9mohm power ask to modify as 09.8271N.A5L
2
(R)
1
(G) PC24 0R0603-PAD 2 1 PR138
C PWR_VGA_CORE_VREF PR22 1 2 5K9R3F-3-GP SC2700P50V3KX-1GP PWR_VGA_CORE_LGATE2 C
0R0603-PAD 2 1 PR139
2
DCBATOUT_VGA_CORE 0R0603-PAD 2 1 PR140
O
1
(G) (G)
PR25 1 2 20KR2F-L-GP R546 0R0603-PAD 2 1 PR141
1
21KR2F-GP 20131206 Madrid SB Charles
NCP81172_TSENSE (G) 0R0603-PAD 2 1 PR37
Unmount PTC1 ; Add PC104,PC109,PC157
PR128 [Layout] PC104 place back to PC4
2
1
(G) 49K9R2F-L-GP 0R0603-PAD 2 1 PR31

PC19
2
SCD1U16V2ZY-2GP (G) (G) 0R0603-PAD 2 1 PR32
2
5
6
7
8
1
(G) (G) PC7 PC4 PC9 PC104 PC109
PWR_VGA_CORE_UGATE2_R
1
5
6
7
8
D
D
D
D
SCD1U25V3KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
.C
(G) PR28 PC20 (G84.A14DP.037) 0R0603-PAD 2 1 PR33
D
D
D
D
PR23 18KR2F-GP SC2700P50V3KX-1GP PU1
2
SIR172ADP-T1-GE3-GP
NTC-100K-8-GP PU2 0R0603-PAD 2 1 PR34
SIR172ADP-T1-GE3-GP
Put colse to
2
2
4
G
VCORE hot spot
1
PWR_VGA_CORE_VREF_2 PWR_VGA_CORE_UGATE2_R 4
S
S
S
(G)
S
S
S
PC59
3
2
1
SCD1U50V3KX-GP
2
3
2
1
2 (G84.A14DP.037)
PR29
0R0402-PAD 0.36uH, DCR=1.05~1.2mohm, Idc=30A
VDDC_PWR
Iomax=40A
OCP>60A
AM
1
(G)
PL3 1 2 IND-D36UH-19-GP
3D3V_VGA_S0
2
(G)
5
6
7
8
5
6
7
8
1
(G) PR135 (G) (G) (G)
D
D
D
D
D
D
D
D
R11 (G84.010DP.037) (G84.010DP.037) 2D2R5J-1-GP PC26 PTC8 PTC9
E820U2D5VM-7-GP
E820U2D5VM-7-GP
33KR2F-GP PQ3 PQ2
SC22U6D3V5MX-2GP
2
2
SIRA12DP-T1-GE3-GP
SIRA12DP-T1-GE3-GP
1 NCP81172_PH2_SB
1
2
R15 4 4
G
B B
S
S
S
S
S
S
0R0402-PAD
2 1 PWR_VGA_CORE_PSI
54 GPIO13_NVVDD_PSI
3
2
1
3
2
1
(G)
1
(R) PC79
R12 SC1500P50V3KX-GP madrid 20131017 Charles
T
(R) 15KR2F-GP power ask to modify as 09.8271N.A5L
2
C8
SCD01U25V2KX-L1-GP 330uF/2.5V, ESR=9mohm
LA
1
(G)
PR132
3D3V_VGA_S0 100R2F-L1-GP-U
2
1
PR129
(G) 1 2 0R0402-PAD
VGACORE_GND_SENSE_1 51
R9
47KR2J-2-GP
2
IX
(G)
R6(G) (G) PC78
PWR_VGA_CORE_EN 1 2 0R2J-2-GP (G) PR126 SC47P50V2JN-3GP
GPU_THERM_SHUTDOWN* 54 PC77 SC22P50V2JN-4GP 51R2F-2-GP PR133
1 2 1 2 NCP81172_FB1
1 2 PWR_VGA_CORE_SENCE+_1 1 2 0R0402-PAD
VGACORE_VDD_SENSE_1 51
(G)
(G) PC75
1
C6(G) PWR_VGA_CORE_EN 62 PR124 SC100P50V2JN-3GP (G)
1
A SC1U10V2KX-1GP 82KR2F-1-GP PR130 A
2 1 NCP81172_COMP11 2 2 10KR2F-2-GP
1 (G)
2
PR134
20131209 Madrid SB Charles 100R2F-L1-GP-U
Muount C6 (1uF) for GPU PWR sequence
.F <Core Design>
2
VDDC_PWR Wistron Corporation
Title
GPU PWR_NVVDD(NCP81172)
W
SA
5 4 3 2 1
W
W
5 4 3 2 1
1D5V_VGA_S0 GPU VCORE -> MEMORY POWER

D
MAX=6A 1D5V_S3

84.07698.037
5
6
7
8
DCBATOUT (G) Q62
D
D
D
D
FDMS7698-GP
MEMORY DIE_S0
M
1
C
DCBATOUT R33
4
2A C
G
82K5R2F-GP
S
S
S
(G)
O
2
3
2
1
R32 R55 (G) 1D5V_VGA_S0
100KR2J-1-GP GPUPG_2 1 2 GPUPG_3
(G) 10KR2J-3-GP
1
D
2
.C
Q7 R58 C25
2N7002-11-GP 100KR2J-1-GP C28 (G78.10421.2FL) 20131211 Madrid SB Charles
2
(G78.10421.2FL)
(G84.2N702.J31) (G) SCD1U25V2KX-GP Delete TC1
2
GPUPG_1
SCD1U25V2KX-GP
G
2
3D3V_VGA_S0 20131105 Madrid SA
unmount to check when SA
S
1
Q4 20110228
AM
2
2N7002-11-GP R30
D
(G) (G84.2N702.J31) 100KR2J-1-GP
B R25 (G) B
10KR2J-3-GP
2
G
54,60 DGPU_PWROK
1
T
LA
<Variant Name>
Wistron Corporation
IX
A A
Title
GPU PWR_1D5V_VGA(51363)
.F Custom
Madrid SA
5 4 3 2 1
W
W
W
5 4 3 2 1
Power Sequencing Requiremen

N15S-GT-B-A2
1.05V to 1.05V_VGA_S0 Transfer
Power-on: FDMS0310, POWER PAK

Max Rdson=3.5m ohm at Vgs=10V,21A
D
3D3V_VGA_S0-->NVVDD==1D05V_VGA_S0-->1D5V_VGA_S0 PCH_1D05V D
Power-off:
The timing of all power rail need power down to 0V under 10ms. SCD1U25V2KX-GP
1
(G) (G78.10421.2FL)
C31 C30
5
6
7
8
Q9
D
D
D
D
SC4D7U6D3V3KX-GP
(G)
+3VS to 3.3V_DELAY Transfer FDMS7698-GP
M
1D05V_VGA_S0
84.07698.037
4
S
S
S
DCBATOUT 3.6A
R132
3
2
1
1 2
RUNON_R_2_C
0R0603-PAD-2-GP DCBATOUT R40
.C
(G) 82K5R2F-GP
1
C (G) C
1
C29
2
3D3V_VGA_S0 R35 R59 (G) (R78.10421.2FL)
2
100KR2J-1-GP GPUPG_12 1 2 SCD1U25V2KX-GP
AM
3D3V_S0 S (G) 10KR2J-3-GP
1
D
D
2
1
D
(R) Q17 Q8 R44

1
DMP2130L-7-GP 2N7002-11-GP 100KR2J-1-GP C27

R133 84.02130.031 (G84.2N702.J31) (G) (R78.10421.2FL)
2
G
3D3V_VGA_S0
(G84.2N702.J31)
2N7002-11-GP
(R) 100KR2J-1-GP 2ND = 84.03413.A31 GPUPG_11 G SCD1U25V2KX-GP
2
2
S
2
1
T
3.3V_ALW_1 20110228
(G) R34
D
Q5 100KR2J-1-GP
1
10KR2J-3-GP R26 (G)
LA
6
Q16 R130 R903
2
2N7002KDW-GP (R) 200R2F-L-GP 1 2 GPUPG_10 G
84.2N702.A3F
1
2nd = 84.DM601.03F 0R2J-2-GP
2
S
B (R75.27002.F7C) C7 B
1
IX
2
SCD1U25V2KX-GP
(R78.10421.2FL)
3.3V_RUN_VGA_1 60 PWR_VGA_CORE_EN
R131
10KR2F-2-GP
.F
3D3V_S0 1 23D3V_VGA_S0_EN
(R)
1
W
C95 (R)
SCD22U10V2KX-1GP
2
<Variant Name>
W
1D5V_VGA_S0 1D05V_VGA_S0
1
R66 1 R65 Wistron Corporation

A (G63.10334.1DL) 100KR2J-1-GP 100KR2J-1-GP 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, A
(G63.10334.1DL)
W

2
Title
GPU PWR_1D05V/3D3V
Custom
Madrid SA
5 4 3 2 1
5 4 3 2 1
H1 H2
CPU
2
4 4
1 1
HS1 HS2 HS3 HS4
5 8 5 8 STF296R205H152-GP STF296R205H152-GP STF296R205H152-GP STF296R205H152-GP
D 6 D
1
GENS315R158-8-F-A-GP GENS315R158-8-F-A-GP
H3 H4
M
3
2
4 4
1 1
5 8 5 8
O
MINI1 WLAN/BT
6
VGA
.C
GENS315R158-8-F-A-GP GENS315R158-8-F-A-GP (G) (G)
HS5 HS6 HS7
STF296R205H152-GP STF296R205H152-GP STF256R113-UH258-GP
34.3HJ02.001 -> 1.5mm

34.3KF01.001 -> 3.3mm
1
34.3HJ03.001 -> 6.5mm
AM
C C
1
H5
34.3KF01.001 for 5.2mm slot 62.10043.G11
34.3HJ03.001 for 9.0mm slot 62.10043.E41
3
4
1
5 8
T
6
GENS315R158-8-F-A-GP
LA
CPU Plate
IX
SKT1 SKT2
B
2012/09/10_aPisa_SA
.F B
2012/09/30_aPisa_SB
Modify H4 symbol
W
Load Plate Back Plate

(22.78005.181) (22.78002.011)
W
W
5V_S0 1D5V_S3 3D3V_S5 1D5V_S3
A FC4 (R) A
<Core Design>
1
1
SC33P50V2JN-3GP FC2 FC1 FC3 (R) (R)
(R) SC47P50V2JN-3GP SCD01U25V2KX-3GP SC33P50V2JN-3GP EC26 EC24
(78.10324.2FL) SCD1U16V2KX-3GP SCD1U16V2KX-3GP
DY Wistron Corporation
2
2
20121007 Charles 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Marge material Taipei Hsien 221, Taiwan, R.O.C.
Title
STAND OFF/HOLE/EMI CAP

A3
Madrid SA
5 4 3 2 1
5 4 3 2 1
Material part HeatSink+FAN Symbol

Vendor
LGA115x CPU SOCKET Symbol P/N:
SKTY Back Plate (R) SKTZ ILMCOVER (R)
D SKTX Load Plate (R) D
Vendor: LOTES
P/N:22.78002.011 Vendor:LOTES
Vendor:LOTES P/N: 22.78005.171
P/N:22.78003.011 Thickness: max 2.2mm (含mylar及及及耐)
Vendor: FOXCONN Vendor:FOXCONN
Vendor:FOXCONN P/N:22.78006.011 P/N: 22.78005.161 HSFAN1
(R60.3KN01.001)
P/N:22.78006.001
Thickness:2.0mm(含mylar)
M
O
.C
SKT4
C
ILMCOVER C
(R60.3EE01.001)
Vendor:LOTES
P/N: 22.78005.171
AM
LABEL Vendor:FOXCONN
P/N: 22.78005.161
LBL1
LABEL
LAN ID :
F80F4105EB9A
(45.41107.011) MB serial NO# and MAC address
LBL2
45.41101.001 -> 35 x 15mm
T
LABEL 45.41107.011 -> 70 x 8mm
LAN ID : (R)
F80F4105EB9A
LA
LBL3
LABEL
LAN ID : (R)
F80F4105EB9A
BAT1
BATTERY CR2032_30MM
(R23.21221.024)
Wire Length:30mm
IX
B B
HeatSink Symbol Vendor

P/N:
PCH Vendor
P/N: Pisa2
23.21221.024
23.21212.031
PCHHS1 60.3ET05.001
.F
HEATSINK 60.3ET05.011
(60.3MN01.001) 60.3ET05.021
Vendor
W
P/N: Madrid
60.3MN01.011(second source) BAT2
60.3MN01.001 BATTERY BR2032_60MM
(R23.24220.612)
Battery Symbol
W
Wire Length:60mm PCB Symbol

耐耐耐>85C
Vendor
BAT3
P/N: Vendor PCB1
BATTERY CR2032 PCB
23.20068.001 P/N:
W
(23.20068.001) (R)
A 23.20023.311 23.21208.061 A
23.24220.612 Wistron Incorporated
23.22063.001
Hsichih, Taipei
Title
HeatSink / Battery cell /etc
B SA
Madrid
5 4 3 2 1
5 4 3 2 1
PU4701
0D75V_EN
PU4501 PU4801
PM_SLP_S3# 1D8V_S0
RUNPWROK 1.05VTT_PWRGD 0D85V_S0

PU4601
D PM_SLP_S4#
1D05V_S0 0D85V_S0
Power Sequence D
1D05V_VTT ALL_POWER_OK
1D5V_S3 1D5V_S3
0D75V_EN
0D75V_S0
PLT_RST#
M
U7901 PCH1 CPU1
O
PCH
ATXPG PM_DRAM_PWRGD H_CPU_SVIDCLK
.C
ITE8731 S0_PWR_GOOD CPU
SUSB# And Gate
3D3V_S0 SIO can delay: ALL_POWER_OK

23h<3:2>
AM
C C
00b 01b 10b H_CPUPWRGD

400ms / 15ms / 200ms
T
PU4201
VCC_GFXCORE
LA
ALL_POWER_OK
SYS_PWROK
CPU_CORE VCC_CORE
H_CPU_SVIDCLK
IX
IMVP_PWRGD
B
.F B
AND GATE
S0_PWR_GOOD
Reserve
W
W
W
A <Core Design> A
Wistron Corporation
Title
SEQUENCE DIAGRAM
A3
Madrid SA
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram 3D3V_S5 3D3V_S0 KBC SMBus Block Diagram
5V_S0
‧ ‧
3D3V_S0 ‧
SRN2K2J-1-GP SRN2K2J-1-GP
‧
DIMM 1 SRN10KJ-5-GP
SMBCLK SMB_CLK
‧ ‧PCH_SMBCLK
1
SMBDATA SMB_DATA
‧ ‧ PCH_SMBDATA
SCL
SDA
TouchPad Conn. 1
3D3V_S5
PSDAT1 TPDATA
‧ TPDATA TPDATA
SMBus Address:A0 PSCLK1 TPCLK

‧ TPCLK TPCLK
2N7002SPT
‧ 3D3V_AUX_KBC
SRN2K2J-8-GP
‧
SML1CLK SML1_CLK
M
SRN4K7J-8-GP
SML1DATA SML1_DATA To KBC & eDP DIMM 2
3D3V_S5 ‧PCH_SMBCLK SCL SRN100J-3-GP Battery Conn.
SML0CLK SML0_CLK
‧ PCH_SMBDATA SDA
GPIO17/SCL1 BAT_SCL BATA_SCL_1 CLK_SMB
SML0DATA SML0_DATA GPIO22/SDA1 BAT_SDA BATA_SDA_1 DAT_SMB SMBus address:16

‧
O
SMBus Address:A4
SRN2K2J-1-GP
3D3V_S0 G-Sensor BQ24745
.C
‧ XDP ‧PCH_SMBCLK
KBC SCL
SMBus address:12
PCH ‧ PCH_SMBDATA
SCLK
SDATA
NPCE795 SDA
SRN2K2J-1-GP
UMA SMBus address:xx LCDVDD_eDP
SCL
PCH
AM
2 2
SDA
SDVO_CTRLCLK PCH_HDMI_CLK Level DDC_CLK_HDMI
‧
SDVO_CTRLDATA PCH_HDMI_DATA
Shift DDC_DATA_HDMI Minicard LCDVDD_eDP
UMA WLAN SRN2K2J-1-GP
‧PCH_SMBCLK ‧
3D3V_S0
‧ PCH_SMBDATA
SMB_CLK
SMB_DATA
eDP
‧ LCD_SMBCLK SCL
SMBus address:XX
‧
T
‧ LCD_SMBDATA SDA
SRN2K2J-1-GP Minicard GPIO73/SCL2 SML1_CLK

‧
W-WAN 2N7002DW-1-GP
LA
UMA SRN0J-6-GP GPIO74/SDA2 SML1_DATA
PCH_SMBCLK
SMB_CLK
‧
L_DDC_CLK LVDS_DDC_CLK_R
PCH_SMBDATA
L_DDC_DATA LVDS_DDC_DATA_R SMB_DATA
UMA
3D3V_VGA_S0
CRT_DDC_CLK CRT_DDC_CLK
IX
CRT_DDC_DATA CRT_DDC_DATA
‧
SRN2K2J-1-GP
DIS
3
DDC1CLK GPU_LVDS_CLK
SRN0J-6-GP
LVDS_DDC_CLK CLK
.F 3
DDC1DATA GPU_LVDS_DATA LVDS_DDC_DATA DATA LCD CONN

DIS SRN0J-6-GP
W
DDC2CLK VGA_CRT_DDCCLK
DDC2DATA VGA_CRT_DDCDATA
3D3V_S0 DIS 5V_S0

W
VGA ‧ ‧
3D3V_S0
SRN2K2J-1-GP SRN10KJ-6-GP
UMA
‧
UMA
W
SRN0J-6-GP
CRT_DDCCLK_CON
CRT_DDCDATA_CON
CRT CONN
5V_S0
3D3V_VGA_S0 UMA
2N7002DW-1-GP
‧
‧
4
5V_S0 4
SRN1K5J-GP
SRN2K2J-1-GP
DIS
DDC2CLK GPU_HDMI_CLK DDC_CLK_HDMI
<Core Design>
TSCBTD3305CPWR
DDC2DATA GPU_HDMI_DATA DDC_DATA_HDMI
HDMI CONN Wistron Corporation
SRN0J-6-GP
Title
SMBUS BLOCK DIAGRAM

A2
Madrid SA
DIS Date: Tuesday, January 21, 2014 Sheet 66 of 68
A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
SPKR_PORT_D_L-
PAGE28 DXP P2800_DXP SPKR_PORT_D_R+ SPEAKER

MMBT3904-3-GP
SC2200P50V2KX-2GP
M
DXN P2800_DXN
UMA Place near CPU
Codec
Thermal PWM CORE
O
92HD79B1
P2800 HP1_PORT_B_L HP
.C
MMBT3904-3-GP HP1_PORT_B_R
PAGE27 GPIO5 SYS_THRM TDR T8

OUT
KBC GPIO92 CPU_THRM TDL
AM
PURE_HW_SHUTDOWN#
2
OTZ THERM_SYS_SHDN#
2N7002
D EN 3V/5V 2
NPCE795P S
G
IMVP_PWRGD PGOD
VR
Put under CPU(T8 HW shutdown)
MIC
T
GPIO4 VGA_THRM TDR HP0_PORT_A_L
GPIO94 GPIO56 PAGE28
P2800_VGA_DXP HP0_PORT_A_R
DXP THRMDA
VREFOUT_A_OR_F IN
LA
FAN_TACH1
SC2200P50V2KX-2GP SC2200P50V2KX-2GP
VGA DXN
P2800_VGA_DXN
THRMDC
VGA
Thermal
FAN1_DAC
TACH Place near GPU(DISCRETE only).

P2800
IX
FAN
VIN
MMBT3904-3-GP DMIC_CLK/GPIO1 Digital
5V
MIC
3
.F DMIC0/GPIO2
3
PH
OTZ
W
VSET VOUT
VIN
FAN CONTROL
W
P2793 PORTC_L
PAGE28 PORTC_R
Analog
VREFOUT_C MIC
W
4 <Core Design> 4
Wistron Corporation
Title
Thermal/Audio Block Diagram

Custom
Madrid SA
A B C D E
5 4 3 2 1
3D3V_S0
D D
SI4128*1 3D3V_A
3D3V_S5
SI4712*1 Imax=5A (EUP)
PWM
RT8243B
SI4128*1 5V_CHARGER
5V_S0
SI4712*1 Imax=9A
DC_IN Dual PWM Design
M
VCC5_USB
ADP_19V PWM 12V_PWR +12V_S0

5V_S5
O
NCP1589A Imax=3A Imax=3A (EUP) V_5_CODEC
C C
.C
PWM 1D5V_S3
UMA
RT8207MZQW Imax=5.5A MOS GATE 1D5V_S0
?? Imax=0.3 A
0D75V_S0
AM
MOS GATE 1D5V_VGA_S0
AO4468L Imax= 2A
GPU
T
DDR3 VRAM
B B
LA
PWM 1D05V_VTT
PWM SIR172A*2 VCC_CORE Imax=6A
ISL95812HRZ SIRA12 *4 TDC= 9A
Imax=32A
IX
PWM
.F
SIR172A*4 GPU_CORE
NCP81172 SIRA12 *4 Imax=40A <Core Design>
A A
Wistron Corporation
W
Title
POWER BLOCK DIAGRAM

W

Custom
Madrid SA
5 4 3 2 1
W

Madrid SB Schematics

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5 4 3 2 1

Project code :3PD00L010001 Project Name :PIM81L/aMadrid

HASWELL INTEL LYNX POINT

PCH (AUDIO/GPIO/SPI) 13 Mini PCIE Card TV Tuner 47

LCD/Inverter Connector 23 GPU VRAM3 (2/4) 57 23U : SCA1,DCIN2 SCA1 : 071.02586.000G

Battery Charger(Reserve) 32 SMBUS table 66 KN.0040B.005 -> R619=15K(64.15025.6DL)

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

Project code :3PD00L010001

FDIx2 SYSTEM DC/DC

USB2.0*3 SATA x 2 ODD (SATA2_3Gb/s)

LPC debug port HDD (SATA3_6Gb/s)

Flash ROM SPI SIO ITE8732 Temp Ctrl

4 PCH Strapping Huron River Schematic Checklist Rev.0_7 4

INIT3_3V# Weak internal pull-up. Leave as "No Connect".

Default = Do not connect (floating)

Low (0) = Disables the VccVRM. Need to use on-board filter

DMI 20131010 Madrid SA Charles

21 DPD_LANE0N_S DMI_RX#3 AB3 DMI_MT_IR_DP1

20131010 Madrid SA Charles

CPU uLGA (DMI/FDI)

CPU uLGA (DDR)

VCC PCH_1D05V R91 1 2 0R0402-PAD

R75 1 (R) 2 10KR2F-2-GP MBT3904DW1T1G-2-GP

C48 C46 C53 C366

SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP SC22U6D3V5MX-2GP

C362 C361 C360 C363

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

CPU uLGA (VCC)

THERMAL HSW_PCUDEBUG_8 R555 1 (R) 2 1KR2J-1-GP

H_PROCHOT_N R61 1 2 0R0402-PAD H_PROCHOT_R_N HSW_PCUDEBUG_10 R594 1 (R) 2 1KR2J-1-GP

B HSW_PCUDEBUG_12 R561 1 (R) 2 1KR2J-1-GP B

HSW_PCUSTB_0_DN R584 1 (R) 2 1KR2J-1-GP

HSW_PCUSTB_1_DN R581 1 (R) 2 1KR2J-1-GP

CPU uLGA (VCORE/XDP)

CPU1I 9 OF 10 CPU1G 7 OF 10 CPU1J 10 OF 10

A5 HASWELL AJ5 HASWELL HASWELL

NCTF TEST PIN: AU40,

CPU uLGA (VCC)

M_A_DQ55 176 DQ54 VSS 44

M_A_DQS#1 27 127 R196

M_B_DQ24 57 DQ23 VDD3 82

M_B_DQ26 67 DQ25 VDD5 88

M_B_DQ34 141 DQ33 VDD13 112

Layout Note: DQ35 VDD15

M_B_DQ54 174 DQ53 VSS 43

M_B_DQS7 188 168

5 M_B_DIM0_ODT0 120 ODT0 VSS 178

USB3.0 Port Mapping

USB3.0 LYNX-POINT-2-GP-U 20131125 Madrid SB Charles

GPIO55 K18 USB3RN5

20131010 Madrid SA Charles PCH(FDI/PCIE/DMI/USB)

G40 PECI_PCH R261 1 2 0R2J-2-GP H_PECI

PCH1E 5 OF 11 R138 1 (R) 2 10KR2J-3-GP

2013/10/22 Madrid TACH5 R206 1 (R) 2 10KR2J-3-GP

100KR2J-1-GP 1K8R2-GP 1K8R2-GP

LPC 20,50 LPC_AD0

Low = Default 2013/05/03

R45 C14 SMLINK0_DATA

Q6 GND Y ME_CNTL 2 ME_CNTL1 PMBS3906-GP

(R) (R) EV FOR FUTURE ENGINEERING HDA_SDOUT

IN OUT R23 0R2J-2-GP

(R) (R) (R) 3D3V_S0

PCH_SYSPWROK 1 (R) PWROK3_1_R LPC_FRAME#