NuMicro® SPI

A Leading MCU Platform Provider

June 2016
Agenda
• Features
• Block Diagram
• Function Descriptions
• Functions and Sample Code in BSP
• Sample Code (with PDMA)

2
Features (1/2) -Revised
• SPI Mode
- Up to 2 sets of SPI controllers
- Supports Support Master (max. 36 MHz) or Slave (max. 18 MHz) mode
operation
- Support Dual I/O transfer mode
- Configurable bit-length of a transaction word 8- ~ 32-bit
- Provides separate 8-level depth transmit and receive FIFO buffers
- Supports MSB first or LSB first transfer sequence

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Features (2/2)
• SPI Mode
- Supports Byte Reorder function
- Supports PDMA transfer
- Supports 3-Wire, no slave selection signal, bi-direction interface
- Support Byte or Word Suspend function

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Block Diagram

n : indicates the number of SPI controller

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SPI Basic Function Setting (1/3)
Function Slave Mode LSB First Bit length
SLAVE LSB DWIDTH
Value
(SPI_CNTRL[18]) (SPI_CNTRL[10]) (SPI_CNTRL[7:3])

0 Master MSB first 32-bit

1 Slave LSB first

0x08 8-bit
~ ~
0x1F 31-bit

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SPI Basic Function Setting (2/3)
• Support the general SPI Mode 0~3
Function Clock Polarity Transmitting Edge Receiving Edge
CLKPOL TXNEG RXNEG

Value (SPI_CNTRL[11]) (SPI_CNTRL [2]) (SPI_CNTRL [1])

0 SPICLK Idle Low Positive-edge Positive-edge

1 SPICLK Idle High Negative-edge Negative-edge

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SPI Basic Function Setting (3/3)

Function Slave Select Slave Select

No Slave Select Auto Slave Select
Level Trigger Active Level
NOSLVSEL AUTOSS
SS_LTRIG SS_LVL
Value (SPI_CNTRL2[8]) (SPI_SSR[3])
(SPI_SSR[4]) (SPI_SSR[2])

0 4-wire Manual Edge-trigger Active-low

1 3-wire Automatic Level-trigger Active-high

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Serial Clock
• Master:
– DIVIDER (SPI_DIVIDER[7:0]):
• SPI peripheral clock frequency

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Serial Clock (2/2)
• Slave:
- The SPI clock is provided by off-chip Master device. The SPI clock must
be faster than the clock rate from Master device.
- HCLK > SPI Clock >external clock of SPI master device

Note: The frequency of SPI peripheral clock cannot be faster than the system clock rate
regardless of Master or Slave mode.

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Master/Slave Mode
• Master
SPIx_CLK SPIx_CLK

M0564 Series SPIx_MISO SPIx_DO

Slave
SPI Master
SPIx_MOSI SPIx_DI

SPIx_SS SPIx_SS

Note: x = 0, 1

• Slave
SPIx_CLK SPIx_CLK

M0564 Series SPIx_MISO SPIx_DI

Master
SPI Slave
SPIx_MOSI SPIx_DO

SPIx_SS SPIx_SS

Note: x = 0, 1
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Byte Reorder Function
• REORDER (SPI_CNTRL[19]):
- TX/RX FIFO will be rearranged.

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Word-/Byte-Suspend Function
• SP_CYCLE (SPI_CNTRL[15:12]):
- The suspend interval depends on the setting of SP_CYCLE. (0.5~15.5
serial clock periods)
• Word-Suspend only in FIFO mode.
• Byte-Suspend must be in Reorder Mode and 16/24/32-bit length.
Suspend interval
Suspend
Interval

CLKP=0

SPIn_CLK
CLKP=1

MSB
SPIn_MISO0 TX0[31]
TX0[30] TX0[24] TX0[23] TX0[22] TX0[16]

MSB
SPIn_MOSI0 RX0[31]
RX0[30] RX0[24] RX0[23] RX0[22] RX0[16]

1st Transaction Byte 2nd Transaction Byte 13

Dual-IO Mode
• DUAL_IO_EN (SPI_CNTRL2[13]):
- =1, Dual I/O mode enabled.
- =0, Disabled.
• DUAL_IO_DIR (SPI_CNTRL[12]):
- =1, Data write.
- =0, Data read.

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FIFO Mode
• FIFO (SPI_CNTRL[21]):
- =1, FIFO mode enabled.
- =0, Disabled.

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Interrupt
• IE (SPI_CNTRL[17]):
- =1, SPI interrupt Enabled.
- =0, Disabled.
• Interrupt Flags :

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Sample Code Path

NUC029xEEBSPv3.00.001

NuMicro NUC029 Series

Document Driver Reference Guide

SampleCode

StdDriver

SPI_Loopback

SPI_Loopback.uvproj
KEIL

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Functions and Sample Code in BSP
• \SampleCode\StdDriver
- SPI_Loopback
- SPI_MasterFifoMode
- SPI_PDMA_Loopback
- SPI_SlaveFifoMode

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Functions and Sample Code in BSP
• spi.c
- uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode,
uint32_t u32DataWidth, uint32_t u32BusClock)
 This function make SPI module be ready to transfer

• spi.h
- SPI_READ_RX(spi)
 Get the datum read from RX register
- SPI_WRITE_TX(spi, u32TxData)
 Write datum to TX register
- SPI_SET_SS_LOW(spi)
 Set SPIx_SS pin to low state 19
SPI Sample Code
int main (void)
{ ……
/* Configure as a master, clock idle low, 32-bit transaction, drive output on falling clock edge and
latch input on rising edge. */ /* Set IP clock divider. SPI clock rate = 2 MHz */
SPI_Open(SPI0, SPI_MASTER, SPI_MODE_0, 32, 2000000);
/* Enable the automatic hardware slave select function. Select the SS pin and configure as low-active. */
SPI_EnableAutoSS(SPI0, SPI_SS, SPI_SS_ACTIVE_LOW);
……
u32Err = 0;
for(u32TestCount = 0; u32TestCount < 0x1000; u32TestCount++) {
/* set the source data and clear the destination buffer */
for(u32DataCount = 0; u32DataCount < TEST_COUNT; u32DataCount++) {
g_au32SourceData[u32DataCount] = u32DataCount;
g_au32DestinationData[u32DataCount] = 0;
}
u32DataCount = 0;

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SPI Sample Code
while(1) {

/* Write to TX register */
SPI_WRITE_TX(SPI0, g_au32SourceData[u32DataCount]);

/* Trigger SPI data transfer */

SPI_TRIGGER(SPI0);

/* Check SPI0 busy status */

while(SPI_IS_BUSY(SPI0));

/* Read received data */

g_au32DestinationData[u32DataCount] = SPI_READ_RX(SPI0);
u32DataCount++;
if(u32DataCount > TEST_COUNT)
break;
}

/* Check the received data */

for(u32DataCount = 0; u32DataCount < TEST_COUNT; u32DataCount++) {
if(g_au32DestinationData[u32DataCount] != g_au32SourceData[u32DataCount])
u32Err = 1;
}
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Thank you!