VLSI Testing

Built-In Self-Test (BIST)

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0286: Testing and Verification of SoC Designs

Lecture 26
Mar 31, 2008 E0286@SERC 1
 Logic BIST
• Complex systems with multiple chips demand
elaborate logic BIST architectures
¾ BILBO and test / clock system
¾Shorter test length, more BIST hardware
¾ STUMPS & test / scan systems
¾Longer test length, less BIST hardware
• Benefits: cheaper system test, Cost: more h/w
• Must modify fully synthesized circuit for BIST to
boost fault coverage
ƒ Initialization, loop-back, test point hardware

Mar 31, 2008 E0286@SERC 2

 Test / Clock System Example

• New fault set tested every clock period

• Shortest possible pattern length
ƒ 10 million BIST vectors, 200 MHz test / clock
ƒ Test Time = 10,000,000 / 200 x 106 = 0.05 s
ƒ Shorter fault simulation time than test / scan

Mar 31, 2008 E0286@SERC 3

 BILBO – Works as PG and RC

™ Built-in Logic Block Observer (BILBO) -- 4 modes:

1. Flip-flop
2. LFSR pattern generator
3. LFSR response compacter
4. Scan chain for flip-flops

Mar 31, 2008 E0286@SERC 4

 Complex BIST Architecture

• Testing epoch I:
¾ LFSR1 generates tests for CUT1 and CUT2
¾ BILBO2 (LFSR3) compacts CUT1 (CUT2)
• Testing epoch II:
¾ BILBO2 generates test patterns for CUT3
¾ LFSR3 compacts CUT3 response

Mar 31, 2008 E0286@SERC 5

 Bus-Based BIST Architecture

¾ Self-test control broadcasts patterns to each CUT over

bus – parallel pattern generation
¾ Awaits bus transactions showing CUT’s responses to
the patterns: serialized compaction
Mar 31, 2008 E0286@SERC 6
 Built-in Logic Block Observer
(BILBO)
• Combined functionality of D flip-flop, pattern
generator, response compacter, & scan chain
ƒ Reset all FFs to 0 by scanning in zeros

Mar 31, 2008 E0286@SERC 7

 Example BILBO Usage
¾ SI – Scan In
¾ SO – Scan Out
¾ Characteristic polynomial: 1 + x + … + xn
¾ CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR
¾ CUT B: BILBO1 is LFSR, BILBO2 is MISR

Mar 31, 2008 E0286@SERC 8

 BILBO Serial Scan Mode
™ B1 B2 = “00”
™ Dark lines show enabled data paths

Mar 31, 2008 E0286@SERC 9

 BILBO LFSR Pattern
Generator Mode
• B1 B2 = “01”

Mar 31, 2008 E0286@SERC 10

 BILBO in D FF (Normal) Mode

• B1 B2 = “10”

Mar 31, 2008 E0286@SERC 11

 BILBO in MISR Mode

• B1 B2 = “11”

Mar 31, 2008 E0286@SERC 12

 Test / Scan System
¾ New fault tested during 1 clock vector with a
complete scan chain shift
¾ Significantly more time required per test than test /
clock
¾ Advantage: Judicious combination of scan chains
and MISR reduces MISR bit width
¾ Disadvantage: Much longer test pattern set length,
causes fault simulation problems
• Input patterns – time shifted & repeated
¾ Become correlated – reduces fault detection
effectiveness
¾ Use XOR network to phase shift & decorrelate
Mar 31, 2008 E0286@SERC 13
 STUMPS Example
¾ SR1 … SRn – 25 full-scan chains, each 200 bits
¾ 500 chip outputs, need 25 bit MISR (not 5000 bits)

Mar 31, 2008 E0286@SERC 14

 STUMPS
™ Test procedure:
1. Scan in patterns from LFSR into all scan chains
(200 clocks)
2. Switch to normal functional mode and clock 1 x
with system clock
3. Scan out chains into MISR (200 clocks) where
test results are compacted
¾ Overlap Steps 1 & 3
™ Requirements:
¾ Every system input is driven by a scan chain
¾ Every system output is caught in a scan chain or
drives another chip being sampled
Mar 31, 2008 E0286@SERC 15
 Summary
™ LFSR pattern generator and MISR response
compacter – preferred BIST methods
™ BIST has overheads: test controller, extra circuit
delay, Input MUX, pattern generator, response
compacter, DFT to initialize circuit & test the test
hardware
™ BIST benefits:
¾ At-speed testing for delay & stuck-at faults
¾ Drastic ATE cost reduction
¾ Field test capability
¾ Faster diagnosis during system test
¾ Less effort to design testing process
¾ Shorter test application times
Mar 31, 2008 E0286@SERC 16
 Thank You

Mar 31, 2008 E0286@SERC 17