310 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

2, FEBRUARY 2010

A Modified SEPIC Converter for High-Power-Factor

Rectifier and Universal Input Voltage Applications
Priscila Facco de Melo, Roger Gules, Member, IEEE, Eduardo Félix Ribeiro Romaneli,
and Rafael Christiano Annunziato

Abstract—A high-power-factor rectifier suitable for universal

line base on a modified version of the single-ended primary induc-
tance converter (SEPIC) is presented in this paper. The voltage
multiplier technique is applied to the classical SEPIC circuit, ob-
taining new operation characteristics as low-switch-voltage opera-
tion and high static gain at low line voltage. The new configuration
also allows the reduction of the losses associated to the diode re-
verse recovery current, and soft commutation is obtained with a
simple regenerative snubber circuit. The operation analysis, de-
sign procedure, and experimental results obtained from a 650-W
universal line power-factor-correction prototype of the proposed
converter are presented. The theoretical analysis and experimen- Fig. 1. Classical SEPIC converter.
tal results obtained with the proposed structure are compared with
the classical boost topology.
a universal input HPF rectifier, in order to obtain high static gain
Index Terms—AC–DC power conversion, switched circuits, at the lower input voltage with the same dc output voltage level
voltage multipliers. of a classical boost converter (Vo = 400 V).
I. INTRODUCTION The integration of a voltage multiplier cell with a classical
single-ended primary inductance converter (SEPIC) is proposed
HE BOOST converter is the usual structure utilized in
T high-power-factor (HPF) rectifiers in order to improve
power factor (PF) and reduce the total current harmonic distor-
in this paper in order to obtain a high step-up static gain oper-
ating with low input voltage and a low step-up static gain for
the high input voltage operation. The operation characteristics
tion (THDi). However, for universal input voltage application, obtained with this modification makes the proposed structure
the efficiency can be reduced mainly in the lowest input volt- an interesting alternative for the universal input HPF rectifier or
age, and the worst operation condition must be considered in the wide input voltage range applications, operating with high effi-
power converter design procedure [1]. The improvement of the ciency. The proposed converter operates with a switch voltage
efficiency at lower line voltage is important because the thermal lower than the output voltage, and with an input current ripple
design and heat sinks size are defined considering the worst op- lower than the classical boost converter. The power circuit of the
eration point. Many works were developed in order to improve proposed converter can be integrated with a simple regenerative
the operation characteristics of the power converter utilized in snubber, obtaining soft-switching commutation and increasing
HPF universal input rectifiers. A review of the main single-phase the efficiency.
topologies and techniques used in an HPF rectifier is presented
in [2]–[4]. A discussion about the use of single stage and two II. PROPOSED CONVERTER
stages structures is presented in [5]. A two switches topology for
universal input HPF rectifier is presented in [6]. Some single- The power circuit of the classical SEPIC converter is pre-
stage-isolated HPF rectifiers are presented in [7]–[14]. sented in Fig. 1. The step-up and step-down static gains of the
The use of high static gain and low-switch voltage topologies SEPIC converter is an interesting operation characteristic for a
can improve the efficiency operating with low input voltage, as wide input voltage-range application. However, as the switch
presented in [15]–[18]. The voltage multiplier technique was voltage is equal to the sum of the input and output voltages, this
presented in [18] for a boost converter in order to increase the topology is not used for a universal input HPF rectifier.
static gain with reduced switch voltage. However, the boost volt- The voltage multiplier technique was presented in [18] in or-
age doubler cannot be used for a universal input voltage HPF der to increase the static gain of single-phase and multiphase
rectifier because the output voltage must be higher than the dou- boost dc–dc converters. An adaptation of the voltage multiplier
ble of the maximum input voltage (Vo = 800 V). A modification technique with the SEPIC converter is presented in Fig. 2. The
in the multiphase boost voltage doubler was proposed in [1] for modification of the SEPIC converter is accomplished with the
inclusion of the diode DM and the capacitor CM . Many op-
Manuscript received February 19, 2009; revised May 13, 2009. Current erational characteristics of the classical SEPIC converter are
version published February 12, 2010. Recommended for publication by changed with the proposed modification.
Associate Editor P.-T. Cheng. The capacitor CM is charged with the output voltage of the
The authors are with the Federal University of Technology Paraná (UTFPR,),
Curitiba PR 80230-901, Brazil (e-mail: rgules@gmail.com). classical boost converter. Therefore, the voltage applied to the
Digital Object Identifier 10.1109/TPEL.2009.2027323 inductor L2 during the conduction of the power switch (S) is

0885-8993/$26.00 © 2010 IEEE

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DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 311

Fig. 2. Modified SEPIC converter.

Fig. 3. First operation stage.

Fig. 4. Second operation stage.

Fig. 5. Main theoretical waveforms.

higher than that in the classical SEPIC, thereby increasing the
static gain. The polarity of the voltage stored in the capacitor The voltage in all diodes and the power switch is equal to the
CS is inverted in the proposed converter, and the expressions of capacitor CM voltage. The output voltage is equal to the sum of
the capacitors voltages and others operation characteristics are the CS and CM capacitors’ voltages. The average L1 inductor
presented in the theoretical analysis. current is equal to the input current and the average L2 inductor
The continuous conduction-mode (CCM) operation of the current is equal to the output current.
modified SEPIC converter presents the following two operation
stages.
1) First stage ([t0 , t1 ] Fig. 3)—At the instant t0 , the switch S III. THEORETICAL ANALYSIS
is turned-off and the energy stored in the input inductor L1 The main equations and the theoretical analysis of the pro-
is transferred to the output through the capacitor CS and posed converter are presented in this section. The results of the
output diode Do , and also to the capacitor CM through the theoretical analysis are compared with the classical boost con-
diode DM . Therefore, the switch voltage is equal to the verter in order to show the positive and negative aspects of the
capacitor CM voltage. The energy stored in the inductor proposed converter.
L2 is transferred to the output through the diode Do . Some comparison with the classical SEPIC converter is also
2) Second stage ([t1 , t2 ] Fig. 4)—At the instant t1 , the switch presented because the proposed topology is obtained from this
S is turned-on and the diodes DM and Do are blocked, and converter.
the inductors L1 and L2 store energy. The input voltage The equations defined by the theoretical analysis are utilized
is applied to the input inductor L1 and the voltage VCS − for the determination of the inductances and capacitances of the
VCM is applied to the inductor L2 . The voltage VCM is proposed converter. The theoretical analysis is developed con-
higher than the voltage VCS . sidering the operation as an HPF rectifier, and the utilization
The main theoretical waveforms operating with hard- of an ac voltage source and a full-bridge diode rectifier con-
switching commutation are presented in Fig. 5. nected to the input of the proposed converter is considered. All

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312 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

TABLE I
DUTY-CYCLE VARIATION AS A FUNCTION OF THE INPUT
AND OUTPUT VOLTAGES

voltage (D = 0) is the double of the input voltage. Therefore,

this structure cannot be used for a universal input application.
The static gain of the classical boost converter is half of the
voltage doubler boost, and can be used in a universal input ap-
plication. The modified SEPIC converter presents a static gain
closed to the classical boost for low values of duty cycle, and
Fig. 6. Static Gain.
a static gain closed to the voltage doubler for high values of
duty cycle. Therefore, the static gain is higher than the classical
analyses are accomplished for an application with an ac input structures in the operation with high values of duty cycle that oc-
voltage changing from Vi = 100 Vrm s to Vi = 240 Vrm s , an curs in the operation with low input voltage. The operation with
output voltage equal to Vo = 425 Vdc , and a nominal output a higher static gain results in an improvement in the operation
power equal to Po = 650 W. with the lower input voltage. The step-up and step-down char-
acteristics of the classical SEPIC converter are not maintained
A. Static Gain in the modified SEPIC converter. The proposed structure cannot
operate with an output voltage lower than the input voltage.
The static gain of the proposed converter can be obtained The voltage of the series capacitor (VCS ) is defined by sub-
considering that the average inductor voltage is zero at the steady stituting (3) and (8) in (7), resulting the following equation:
state. Therefore, the relation presented in (1) must occur at the
steady state for the inductor L1 VCS D
= . (9)
Vi 1−D
Vi tON = (VCM − Vi ) tOFF (1)
Vi D = (VCM − Vi ) (1 − D) . (2) B. Input Current Ripple and L1 –L2 Inductances
Therefore, the CM capacitor voltage is defined by (3), which The input inductance value is defined as a function of the
is the same equation of the classical boost static gain given by maximum input current ripple. As the classical SEPIC, boost,
and the modified SEPIC converters present the same input stage,
VCM 1 the equation for the determination of the input current ripple is
= . (3)
Vi 1−D the same for all converters. The input current ripple (∆iL 1 )
During the period where the power switch is turned-off (tOFF ), during the conduction of the power switch is defined by the
the diodes DM and D0 are in conduction state, and the following following equation:
relation can be defined:
Vi D
∆iL 1 = (10)
Vo = VCS + VCM . (4) L1 f
The L2 average voltage is zero at the steady state, and the where f is the switching frequency.
following relations can be considered: Although the same equation can be used to calculate the input
ripple, the input current ripple for each converter is not the same
(VCM − VCS ) tON = (Vo − VCM ) tOFF (5) because the duty-cycle variation is different for each topology,
(VCM − VCS )D = (Vo − VCM )(1 − D). (6) as presented in Fig. 6. The duty-cycle variation as a function of
the input and output voltages is presented in Table I.
Substituting (3) and (7) in (6), the static gain of the proposed In order to show the duty-cycle variation in a universal input
converter is obtained and presented in (8) rectifier application, the instantaneous input voltage signal is
VCS = Vo − VCM (7) considered in a semicycle of the input line voltage. Fig. 7 is
obtained considering an input line voltage equal to 100 Vrm s ,
Vo 1+D
= . (8) and Fig. 8 is obtained considering an input line voltage equal to
Vi 1−D 240 Vrm s . The output voltage is equal to Vo = 425 Vdc for both
The static gain variation as a function of the duty cycle of figures.
the modified SEPIC and the static gain of other converters is As can be observed in Figs. 7 and 8, the modified SEPIC
presented in Fig. 6. The voltage doubler boost converter [18] converter presents the lowest duty-cycle value in all range of
presents the highest static gain and is interesting for the opera- the input voltage. Lower duty cycle results in a lower switch
tion with the lower input voltage. However, the minimal output conduction interval (tON ).

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DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 313

Fig. 7. Duty-cycle variation (V i = 100 Vrm s and V o = 425 Vd c ).

Fig. 9. Parameterized input current ripple (V i = 100 Vrm s and V o =

425 Vd c ).

Fig. 8. Duty-cycle variation (V i = 240 Vrm s and V o = 425 Vd c ).

A lower input current ripple is also obtained because the

input voltage (Vi ) is applied to the input inductor L1 in a shorter
interval during the tON period.
The parameterized input current ripple (∆iL 1 ) is defined from
(10) and presented in (11).
Replacing in (11) the duty cycle of each converter presented Fig. 10. Parameterized input current ripple (V i = 240 Vrm s and V o =
in Table I, the parameterized input current ripple is obtained and 425 Vd c ).
presented in Fig. 9 for an input voltage equal to 100 Vrm s , and
in Fig. 10, for an input voltage equal to 240 Vrm s , considering
The input inductance value utilized in the practical imple-
an output voltage equal to Vo = 425 Vdc
mentation is equal to L1 = 1 mH.
∆iL 1 = ∆iL 1 L1 f = Vi D. (11) The input inductance of the proposed converter is 27% lower
than the input inductance of the classical boost converter, and
The input inductance can be defined by (13) obtained from 33% lower than the input inductance of the classical SEPIC
(11). The input inductance is calculated for the power con- converter for the same specifications, as presented in Fig. 9.
verter operating at the peak of the lowest input voltage. For The inductor L2 presents the same equation as the L1 inductor
this operation point, the instantaneous input voltage is equal current ripple. However, the L1 inductor average current is equal
to Vipk = 141 V, the converter duty cycle is equal to D = 0.5, to the average input current, and the L2 average current is equal
and the input current ripple (∆iL 1 ) considered is 23% of the to the output current. As the average input current is higher
peak input current (iinpk ). Therefore, the input current ripple is than the average output current for a step-up converter, the L2
calculated as follows: inductor volume is lower than the L1 inductor volume. The L2
peak current is three times lower than the L1 peak current for the
∆iL 1 = iinpk × 0.23 = 6.5 × 0.23 = 1.5 A. (12) operation with the lower line input voltage. Also, the L2 current
The input inductance calculated is equal to ripple can be higher than the L1 current ripple because the input
current ripple depends only on the L1 current ripple. Therefore,
Vi D 141 × 0.5 the proposed converter uses two inductors, but the L1 inductor
L1 = = = 97 916 µH. (13)
∆iL 1 f 1.5 × 48000 can be 27% lower than the input inductor of the classical boost,

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314 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

the classical SEPIC is equal to the sum of the input and output
voltages. Therefore, the operation voltage is very high, mainly
in the maximum input voltage condition (240 Vrm s ). The switch
voltage of the modified SEPIC converter is equal to the voltage
of the capacitor CM . This voltage is determined by (3), but with
the duty cycle of the modified SEPIC converter presented in
Table I.
As can be observed in Figs. 11 and 12, the switch voltage of
the modified SEPIC is lower than the output voltage in all input
voltage ranges. Figs. 11 and 12 also show the capacitor voltages
VCM and VCS . The output voltage is equal to the sum of the
VCM and VCS capacitors’ voltages.

D. Series Capacitor (CS ) and Multiplier Capacitor (CM )

The CS series capacitor voltage and the CM multiplier ca-
Fig. 11. Parameterized switch voltage (V i = 100 Vrm s and V o = 425 Vd c ).
pacitor voltage change with the line input voltage variation, as
shown in Figs. 11 and 12. Therefore, these capacitances can-
not be large as the output filter capacitor (Co ). However, these
capacitances present a high-frequency voltage ripple due to the
circulating current and the capacitor charge variation (∆Q). As
the circulating current in both capacitances are equal, the high-
frequency voltage ripple is the same. During the power switch
turn-on period, the current in the CS and CM capacitances is
equal to the L2 inductor current. The capacitor charge variation
∆Q is calculated as

∆Q = iL 2 DT. (14)

The high-frequency capacitor voltage ripple (∆Vc ) can be

defined by (15), as a function of the capacitor charge variation
∆Q
∆Vc = . (15)
C
Therefore, the CS and CM capacitances can be defined as
follows:
iL 2 D
Fig. 12. Parameterized switch voltage (V i = 240 Vrm s and V o = 425 Vd c ). CS = CM = (16)
∆Vc f
where f is the switching frequency.
and the L2 volume is smaller than the L1 inductance. The L2
The highest capacitor voltage ripple occurs at the peak of the
inductance utilized in the practical implementation is half of the
lowest line input voltage. The average current of the inductor L2
L1 inductance (L2 = 500 µH).
is equal to the output current (io ), and its peak value must be used
in (16). Considering an input voltage equal to Vi = 100 Vrm s
C. Power Switch Voltage
and a maximum capacitor voltage ripple equal to 12% of the
The power switch voltage is also an important parameter of output voltage (∆Vc = 50 V), the capacitors CS and CM can
the circuit in a wide input voltage application, and presents in- be defined as
fluence in the converter efficiency and cost. The modification iL 2 D 3 × 0.5
proposed in this paper significantly changes the drawback of the CS = CM = = = 625 nF. (17)
∆Vc f 50 × 48000
operation with high switch voltage of the classical SEPIC con-
verter. A comparison of the power switch voltage is presented The capacitances utilized in the practical implementation of
in Fig. 11, considering a line input voltage equal to 100 Vrm s , the proposed converter is equal to CS = CM = 660 nF, com-
and in Fig. 12, for an input voltage equal to 240 Vrm s . In both posed of two capacitors (330 nF) connected in parallel. A
figures, the output voltage is equal to 425 Vdc , and the switch polypropylene capacitor is used in the practical implementation,
voltage is presented parameterized in relation to the output volt- and as the equivalent series resistance (ESR) of the polypropy-
age. The switch voltage is equal to the output voltage for the lene capacitor is very low (ESR = 12 mΩ at 100 kHz), the
boost converter. Therefore, the parameterized voltage of this influence of this resistance in the calculation of the capacitor
converter is unitary in all voltage ranges. The switch voltage for voltage ripple is not considered.

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DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 315

Fig. 13. Turn-on regenerative snubber with switch voltage equal to V o .

Fig. 14. Turn-on/ turn-off regenerative snubber with switch voltage equal to
Vo .

E. Output Capacitor
The output filter capacitor (Co ) is determined as in the clas-
sical boost converter. The capacitance is defined by a function
of the output power (Po ), the grid frequency (fG ), and the low-
frequency output voltage ripple (∆Vo ). Considering an output
voltage ripple equal to 1% of the output voltage, the output
capacitance is calculated as
Po 650
Co = = = 477 µF.
2πfG × 2Vo ∆Vo 2π60 × 2 × 425 × 4.25
(18)
The output filter capacitor utilized in the practical implemen- Fig. 15. Turn-on/ turn-off regenerative snubbers with switch voltage equal to
tation is equal to Co = 500 µF. VC M .

F. Regenerative Snubber with the inclusion of the diode Dsnb .The soft-switching turn-on
A classical problem presented by the hard-switching struc- and turn-off commutation snubbers, presented in Fig. 14, can be
tures operating in CCM is the reduction of the efficiency due obtained including some additional components to the circuit
to the additional losses caused by the reverse recovery current presented in Fig. 13. The inductor Lsnb limits the di/dt at the
of the diodes. This problem is an important source of losses switch turn-on, and when the power switch is turned-off, the
in a universal input HPF rectifier. There are some regenerative energy stored in this inductance is transferred to the capacitor
snubbers proposed for the classical boost converter that can Csnb through the diode Dsnb1 . The initial condition of the volt-
reduce the effects of this problem [19]. However, the correct age in the capacitor Csnb is zero, and the reduced capacitance
operation of these snubbers in all input voltage ranges is dif- value (typically, 3–30 nF) limits the dv/dt of the power switch
ficult. Therefore, the use of these snubber integrated with the voltage. The voltage in this capacitor increases until it reaches
classical boost converter cannot be effective for the universal in- the output voltage value when the diode Dsnb2 conducts. Dur-
put HPF rectifier. There are some soft-switching configurations ing the conduction of the power switch, the energy stored in
with the inclusion of an active switch and other components in the capacitor Csnb is transferred to the capacitor Cs through the
order to reduce the reverse recovery current and eliminate the diode Dsnb2 and inductor Lsnb until the Csnb voltage becomes
commutation losses [4], [20], [21]. This alternative can be used null. The peak current is limited by the Lsnb inductor during this
in high-performance applications, but increases the complexity energy transference. The switch voltage is limited to the output
and cost of the converter. voltage with the use of this snubber.
The power circuit of the modified SEPIC converter allows the Fig. 15 presents the turn-on and turn-off snubbers with the
integration of three regenerative snubbers that reduces the diode power switch voltage equal to VCM , which is lower than the
reverse recovery current problem, and is effective in all input output voltage. The operation of this snubber is almost the same
voltage ranges. The simplest regenerative snubber is presented as the circuit presented in Fig. 14. The unique difference is
in Fig. 13. A small inductance Lsnb (typically, 5–20 µH) is con- that during the energy transference from the inductor Lsnb to
nected in series with the power switch. This inductance limits the capacitor Csnb , after the power switch turn-off, the capaci-
the di/dt at the switch turn-on instant and zero-current switching tor voltage increases until it reaches the CM voltage when the
(ZCS) is obtained. When the power switch is turned-off, the en- diode Dsnb3 conducts, maintaining the switch voltage equal
ergy stored in the Lsnb inductance is transferred to the capacitor to the voltage VCM , as in the hard-switching circuit. During
CS through the diode Dsnb . This configuration eliminates the the conduction of the power switch, the snubber capacitor is
turn-on commutation loss, which is the most significant part of discharged through the diode Dsnb2 and inductor Lsnb , trans-
the commutation losses. The turn-off commutation is dissipa- ferring energy to the capacitor Cs . All snubber circuits does
tive and the power switch voltage is equal to the output voltage not change the static and dynamic operations of the power

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316 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 16. Modified SEPIC converter with magnetic coupling.

circuit, which acts only in the commutation periods, eliminating

the commutation losses and reducing the negative effects of the
reverse recovery current of all diodes.

G. Magnetic Coupling
The inductors L1 and L2 of the proposed converter presented Fig. 17. Implemented prototype.
in Fig. 2 cannot be coupled as in the classical SEPIC topology
without changing significantly the operation characteristics pre-
sented in this paper. Therefore, the magnetic coupling of these verter is used with the proposed converter and the experimental
inductors is not analyzed for the proposed modification of the results obtained confirm this consideration.
SEPIC converter. The operation of the proposed converter with The simplified block diagram of the digital control system
isolation between the input and output with the inductor L2 op- utilized in the implementation of the high-RF rectifier is pre-
erating as a flyback transformer is possible, but is not presented sented in Fig. 17. The control algorithm is developed using the
in this paper. The inductor L2 can also be used as a flyback MC56F8013 digital signal controller operating with a sampling
transformer without isolation, as presented in Fig. 16. The ad- rate equal to 24 kHz. The sample of the output voltage is com-
vantage of this modification is that the transformer turns ratio pared with a reference of the output voltage (Vref ). The error
(nLp2 /nLs2 ) allows the converter operation with a very high signal obtained (Ev ) is applied to a digital proportional–integral
static gain without increasing the power switch voltage. (PI) controller. The result obtained from the voltage controller
Therefore, this modification can be interesting for low input (VCv ) is multiplied by a sample of the rectified input voltage,
voltage and high output voltage applications. and the resultant signal is the reference waveform for the current
control loop (iref ). The sampling of the rectified input current
is compared with the current reference (Iref ). The result (Ei ) is
H. Control System applied to a digital PI controller. The output of the current con-
The control algorithm of the proposed converter is based troller (VCi ) is applied to the pulse width modulator, generating
on the classical structure of the average current-mode control the command signal of the power switch.
with the digital implementation and the power system operat-
ing in CCM. The design procedure of the control system for
IV. EXPERIMENTAL RESULTS
the boost converter is well established and used in this imple-
mentation. The implementation of the control system for the The proposed converter presented in Fig. 15 is tested with the
proposed converter is accomplished by using exactly the same implementation of an experimental prototype, and the perfor-
control designed for the classical boost converter. This approx- mance of the modified SEPIC converter is compared with the
imation is possible because the additional poles inserted by the classical boost converter.
inductor L2 and capacitors CS and CM occur in a frequency A prototype of the classical boost is also built with the same
higher than the poles inserter by the inductor L1 and the output specification of the proposed converter. The power circuit with
filter capacitor Co . As presented in Section III-D, the capacitors the component’s parameters and a representation of the simpli-
CS and CM are very small comparing with the output filter ca- fied block diagram of the digital control system are presented in
pacitor. The inductor L2 is also a fraction of the input inductor Fig. 17. The experimental waveforms are obtained with the ex-
L1 . As the crossing frequencies of the voltage and current con- perimental prototype operating with the nominal output power
trol loops are lower than the frequency of the lower frequency Po = 650 W and with an input voltage changing from Vi =
poles, the additional higher frequency poles does not present a 100 Vrm s to Vi = 240 Vrm s . The output voltage is regulated in
significant influence in the phase margin and the gain margin, Vo = 425 Vdc . The input voltage and current waveform are pre-
thus maintaining approximately the same dynamic response for sented in Fig. 18 for an input voltage equal to Vi = 127 Vrm s .
both power stage structures. In order to show this characteristic, The THDi obtained is equal to THDi = 5.49%, and the PF is
the same control algorithm designed for the classical boost con- equal to PF = 0.99865. The THDi variation as a function of the

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Fig. 18. Input voltage (V i ) and current (Ii ) waveform for an input voltage
V i = 127 Vrm s (100 V/division, 5 A/division, and 5 ms/division).
Fig. 21. L 1 and L 2 inductors current of the proposed converter operating with
V i = 127 Vrm s (5 A/division and 5 ms/division).

Fig. 19. Total current harmonic distortion as a function of the input voltage
variation.

Fig. 22. Input inductor current of the classical boost converter operating with
V i = 127 Vrm s (2.5 A/division and 5 ms/division).

with Vi = 127 Vrm s is presented in Fig. 22. The measured input

current ripple presented by the classical boost converter is equal
to ∆iL = 2 A, using the same value of the input inductor of the
modified SEPIC converter (L1 = Lb o ost = 1 mH).
Therefore, the modified SEPIC input current ripple is 25%
lower than the current ripple of the boost converter using the
same inductance value, as presented in Section III.
The voltage waveform of the capacitors CS and CM are
Fig. 20. Power-factor variation as a function of the input voltage variation.
presented in Fig. 23 for an input voltage equal to Vi = 127 Vrm s ,
and in Fig. 24, for an input voltage equal to Vi = 220 Vrm s . The
experimental waveforms presented in Figs. 23 and 24 agree well
input voltage of the proposed converter and the classical boost with the theoretical waveforms presented in Figs. 11 and 12,
converter is shown in Fig. 19. considering as null the high-frequency capacitor voltage ripple.
The PF variation as a function of the input voltage of the The high-frequency voltage ripple presented in Fig. 23 is close
proposed converter and the classical boost converter is shown to 50 V.
in Fig. 20. A comparison of the switch voltage and current between the
The current waveform of the L1 input inductor and L2 in- proposed converter and the classical boost converter can be
ductor of the proposed converter operating with Vi = 127 Vrm s done with the waveforms presented in Figs. 25 and 26. Fig. 25
are presented in Fig. 21. The measured current ripple of the shows the switch voltage and current of the proposed converter
input current is equal to ∆iL 1 = 1.5 A. The current waveform operating with the nominal output power and an input voltage
of the input inductor of the classical boost converter operating equal to Vin = 127 Vrm s .

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318 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

Fig. 23. C S and C M capacitors voltage operating with V i = 127 Vrm s

Fig. 26. Switch current and voltage of the classical boost converter operating
(100 V/division and 5 ms/division).
with V i = 127 Vrm s (100 V/division, 5 A/division, and 5 ms/division).

Fig. 24. C S and C M capacitors voltage operating with V i = 220 Vrm s Fig. 27. Turn-on and turn-off switch commutations of the proposed con-
(100 V/division and 5 ms/division). verter operating with V i = 127 Vrm s (100 V/division, 5 A/division, and
2.5 µs/division).

The switch voltage is equal to the CM capacitor voltage and

the maximum value is equal to VSm ax = 320 V. The switch
peak current value is equal to IS = 10 A. The switch voltage
and current of the classical boost converter are shown in Fig. 26.
The switch voltage is equal to the output voltage and the
maximum value is equal to VSm ax = 420 V. The switch peak
current value is equal to IS = 9 A.
The commutation improvement obtained with the regenera-
tive snubber presented in Fig. 15 is shown in Fig. 27. Fig. 27
presents the turn-on and turn-off commutations of the power
switch. As can be seen in this figure, the turn-on and turn-off
commutations are soft switching and the commutation losses are
minimized. The maximum switch voltage is equal to the CM
capacitor voltage with the snubber presented in Fig. 15. The
proposed snubber is effective in all ranges of the input voltage
variation and in all ranges of the output power variation.
Fig. 28 presents the switch commutation operating with light
Fig. 25. Switch current and voltage of the proposed converter operating with load. As can be seen in this figure, the snubber circuit maintains
V i = 127 Vrm s (100 V/division, 5 A/division, and 5 ms/division). the reduction of the commutation losses.

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DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 319

Fig. 30. Efficiency curves of the proposed converter as a function of the output
power.

Fig. 28. Turn-on and turn-off switch commutations of the proposed con-
verter operating with V i = 127 Vrm s (100 V/division, 2.5 A/division, and
2.5 µs/division).

Fig. 31. Output voltage (V o ) and input inductor current (iL 1 ) of the proposed
converter operating with V i = 127 Vrm s and with the output power reduction
from 650 to 300 W (100 V/division, 2.5 A/division, and 50 ms/division).
Fig. 29. Efficiency curve of the proposed converter and the classical boost
converter with and without nondissipative snubber as a function of the input
voltage.

The efficiency curves of the proposed converter and the clas-

sical boost converter with hard switching and a nondissipative
snubber, operating with the nominal output power Po = 650 W,
are presented in Fig. 29. The highest efficiency is obtained with
the highest input voltage Vi = 240 Vrm s , and is equal to 97.4%
for the proposed converter and 95.5% for the classical boost
converter.
The efficiency of the classical boost converter with the nondis-
sipative snubber is equal to 97.2%. The lowest efficiency is ob-
tained with the lowest input voltage Vi = 85 Vrm s , and is equal
to 92.6% for the proposed converter and 89% for the boost
converter with the nondissipative snubber. Fig. 32. Output voltage (V o ) and input inductor current (iL b o o st ) of the
Therefore, the efficiency improvement with the proposed con- classical boost converter operating with V i = 127 Vrm s and with the out-
verter in relation, the classical boost converter in the worst op- put power reduction from 650 to 300 W (100 V/division, 2.5 A/division, and
50 ms/division).
eration condition is equal to 3.6%. The efficiency curves of the
proposed converter as a function of the output power and oper-
ating with the input voltage equal to 90, 127, 220, and 240 Vrm s proposed converter operating with an input voltage equal to
are presented in Fig. 30. Vi = 127 V. The output power is reduced from the nominal
The dynamic response of the high-PF rectifier implemented value Po = 650 W to Po = 300 W. The output voltage rises
with the modified SEPIC and the classical boost converters are from the nominal value Vo = 425 V to the maximum value
presented in Figs. 31 and 32, respectively. Fig. 31 presents the Vo = 475 V during the load transient. The transient duration is
output voltage (Vo ) and the input inductor current (iL 1 ) of the equal to 150 ms. Fig. 32 presents the output voltage (Vo ) and the

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320 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 2, FEBRUARY 2010

input inductor current (iLb o ost ) of the classical boost converter application,” IEEE Trans. Power Electron., vol. 13, no. 6, pp. 1079–1098,
operating with the same specifications of the proposed converter. Nov. 1998.
[10] J. Qian and F. C. Lee, “A high efficient single stage single switch high
The output power is reduced from the nominal value Po = power factor ac/dc converter with universal input,” IEEE Trans. Power
650 W to Po = 300 W, and the output voltage rises from the Electron., vol. 13, no. 4, pp. 699–705, Jul. 1998.
nominal value Vo = 425 V to the maximum value Vo = 465 V [11] L. Huber and M. M. Jovanovic, “Single stage single switch isolated power
supply technique with input current shaping and fast output voltage regu-
during the load transient. The transient duration is also 150 ms. lation for universal input voltage range applications,” in Proc. IEEE Appl.
Therefore, the overshoot of the output voltage presented by the Power Electron. Conf. Expo. (APEC), 1997, pp. 272–280.
proposed converter is equal to 11.76%, and the overshoot of the [12] C. Qiao and K. M. Smedley, “A topology survey of single-stage power
factor corrector with a boost type input current-shaper,” IEEE Trans.
classical boost converter is equal to 9.4% for the same controller Power Electron., vol. 16, no. 3, pp. 360–368, May 2001.
parameters. [13] M. H. L. Chow, Y. S. Lee, and C. K. Tse, “Single-stage single-switch
isolated PFC regulator with unity power factor, fast transient response,
and low-voltage stress,” IEEE Trans. Power Electron., vol. 15, no. 1,
V. CONCLUSION pp. 156–163, Jan. 2000.
[14] J. L. Lin, W. K. Yao, and S. P. Yang, “Analysis and design for a novel
A modified version of the SEPIC converter is proposed for the single-stage high power factor correction diagonal half-bridge forward
ac-dc converter,” IEEE Trans. Power Electron., vol. 53, no. 10, pp. 2274–
implementation of a high-PF rectifier suitable for universal line 2286, Oct. 2006.
application. Although the proposed structure presents a higher [15] Q. Zhao and F. C. Lee, “High-efficiency, high step-up DC–DC converters,”
circuit complexity than the classical boost converter, the advan- IEEE Trans. Power Electron., vol. 18, no. 1, pp. 65–73, Jan. 2003.
[16] R.-J. Wai and R.-Y. Duan, “High step-up converter with coupled-inductor,”
tages obtained are the higher static gain for the operation with IEEE Trans. Power Electron., vol. 20, no. 5, pp. 1025–1035, Sep. 2005.
the lower input voltage range, lower switch voltage operation, [17] R.-J. Wai and R.-Y. Duan, “High-efficiency power conversion for low
higher efficiency operation with the lowest input voltage, lower power fuel cell generation system,” IEEE Trans. Power Electron., vol. 20,
no. 4, pp. 847–856, Jul. 2005.
input current ripple, and easy integration with a regenerative [18] M. Prudente, L. L. Pfitscher, G. Emmendoerfer, E. F. R. Romaneli, and
snubber. Three snubber circuits are proposed in order to ob- R. Gules, “Voltage multiplier cells applied to non-isolated DC–DC con-
tain a reduction of the diode reverse recovery current problem, verters,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 871–887, Mar.
2008.
and also obtaining turn-on and turn-off soft switching for all [19] K. M. Smith, Jr. and K. M. Smedley, “Engineering design of lossless pas-
input voltage ranges and output power variation. The average sive soft switching methods for PWM converters—Part I: With minimum
current-mode control is used for the classical boost converter voltage stress circuit cells,” IEEE Trans. Power Electron., vol. 16, no. 3,
pp. 336–344, May 2001.
and also for the proposed converter, and the dynamic response [20] C. M. C. Duarte and I. Barbi, “A new ZVS-PWM active-clamping high
obtained with both converters is approximately the same. The power factor rectifier: Analysis, design and experimentation,” in Proc.
experimental results are obtained with the implementation of Appl. Power Electron. Conf. Expo. (APEC), Feb. 1998, vol. 1, pp. 230–
236.
a rectifier with an output power equal to Po = 650 W, using [21] H. M. Suryawanshi, M. R. Ramteke, K. L. Thakre, and V. B. Borghate,
the boost and the modified SEPIC converters, and the efficiency “Unity-power-factor operation of three-phase AC–DC soft switched con-
improvement with the proposed topology is equal to 3.6% for verter based on boost active clamp topology in modular approach,” IEEE
Trans. Power Electron., vol. 23, no. 1, pp. 229–236, Jan. 2008.
the worst operation condition.

REFERENCES
[1] Y. Jang and M. M. Jovanovic, “Interleaved boost converter with intrinsic
voltage-doubler characteristic for universal-line PFC front end,” IEEE
Trans. Power Electron., vol. 22, no. 4, pp. 1394–1401, Jul. 2007. Priscila Facco de Melo was born in Curitiba, Brazil,
[2] O. Garcı́a, J. A. Cobos, R. Prieto, P. Alou, and J. Uceda, “Single phase in 1984. She received the B.S. degree in electrical en-
power factor correction: A survey,” IEEE Trans. Power Electron., vol. 18, gineering from the Federal Technological University
no. 3, pp. 749–755, May 2003. of Paraná, Curitiba, in 2008, where she is currently
[3] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and working toward the M.S. degree.
D. P. Kothari, “A review of single-phase improved power quality AC– Her current research interests include power elec-
DC converters,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962–981, tronics, power quality, and digital control.
Oct. 2003.
[4] M. M. Jovanovic and Y. Jang, “State-of-the-art, single-phase, active power-
factor correction techniques for high-power applications—An overview,”
IEEE Trans. Ind. Electron., vol. 52, no. 3, pp. 701–708, Jun. 2005.
[5] J. Zhang, M. M. Jovanovic, and F. C. Lee, “Comparison between CCM
single-stage and two-stage boost PFC converters,” in Proc. Appl. Power
Electron. Conf. Expo. (APEC), Mar. 1999, vol. 1, pp. 335–341.
[6] J. Chen, D. Maksimovic, and R. W. Erickson, “Analysis and design of Roger Gules (M’09) was born in Bento Gonçalves,
a low-stress buck-boost converter in universal-input PFC applications,” Rio Grande do Sul, Brazil, in 1971. He received the
IEEE Trans. Power Electron., vol. 21, no. 2, pp. 320–329, Mar. 2006. B.S. degree from the Federal University of Santa
[7] C. Qiao and K. M. Smedley, “A universal input single-phase single-stage Maria, Rio Grande do Sul, and the M.S. and Ph.D. de-
power supply with power factor correction and automatic voltage clamp- grees from the Federal University of Santa Catarina,
ing,” in Proc. Power Electron. Spec. Conf. (PESC), Jun. 2001, pp. 907– Florianopolis, Brazil, in 1998 and 2001, respectively.
913. From 2001 to 2005, he was a Professor at the
[8] D. D. C. Lu, H. H. C. Iu, and V. Pjevalica, “A single-stage AC/DC converter Universidade do Vale do Rio dos Sinos, Rio Grande
with high power factor, regulated bus voltage, and output voltage,” IEEE do Sul. Since 2006, he has been a Professor at the
Trans. Power Electron., vol. 23, no. 1, pp. 218–228, Jan. 2008. Federal Technological University of Paraná, Curitiba,
[9] J. Qian, Q. Zhao, and F. C. Lee, “Single-stage single-switch power factor Brazil. His current research interests include power-
correction ac/dc converters with dc-bus voltage feedback for universal line switching converters and renewable energy applications.

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DE MELO et al.: MODIFIED SEPIC CONVERTER FOR HIGH-POWER-FACTOR RECTIFIER AND UNIVERSAL INPUT VOLTAGE APPLICATIONS 321

Eduardo Félix Ribeiro Romaneli received the B.S.
degree, and the Master’s and Doctorate degrees in
electrical engineering from the Federal University of
Santa Catarina, Florianopolis, Brazil, in 1993, 1998,
and 2001, respectively.
Since 2003, he has been a Full-Time Professor
at the Federal Technological University of Paraná,
Curitiba, Brazil. His research has spanned a several
disciplines, emphasizing power electronics. His cur-
rent research interests are focused but not restricted
to uninterruptible power system (UPS), power-factor
correction, and digital control.
Rafael Christiano Annunziato was born in Curitiba,
Brazil, in 1978. He is currently working toward the
degree in technology of automation at the Federal
Technology University of Paraná, Curitiba.
Since 1997, he has been with the National Health
Service (NHS) Sistemas Eletrônicos Ltda, Curitiba,
where he has been engaged in the development of
power electronics and microcontroller’s firmware for
uninterruptible power system (UPS). His current re-
search interests include power converters and digital
control applied to UPS and power-correction factor.

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