5/30/2018 Design Verification Quiz 4 Survey

Design Verification Quiz 4

Score: 66.7%
6/9 points

Page 1/1
5. Consider the module shown below.

module mux21 (input a, b, c, output m);

and #1 (p1, a, c);
not #1 (cbar, c);
and #1 (p2, b, c);
or #2 (m, p1, p2);
endmodule

Which of the following statements is true?

This is a behavioral description.

This is a gate-level description.

This is a data-flow model.

None of the above.

1/1 point

6. In the module mux21 described above, what is the delay of

the critical path?

5 units

4 units

3 units

None of the above

1/1 point

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5/30/2018 Design Verification Quiz 4 Survey

7. Which of the following tests will exercise the critical path?

a = 0; b = 1; c = 0; #1 a = 1;

a = 0; b = 1; c = 0; #1 b = 0;

a = 0; b = 1; c = 0; #1 c = 1;

None of the above.

0/1 point

8. In which of the following situations can we use formal

verification?

Check if the module will satisfy a particular property

when it is used.

Psuedorandom testbench creation.

To understand the coverage of the testbench.

None of the above.

1/1 point

9. Which of the following statements is true?

In the same module, we cannot mix structural, dataflow

and behavioral styles.

In the same file, we cannot mix structural, dataflow and

behavioral styles.

In the same project, we cannot mix structural, dataflow

and behavioral styles.

None of the above.

1/1 point

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5/30/2018 Design Verification Quiz 4 Survey

10. The "generate" statement is useful for

Synthesizing logic.

Describing iterative logic.

Generation of a gate-level netlist.

Generation of an automatic testbench.

1/1 point

11. Consider the n-bit adder module:

module ADDER (input A[1:n], B[1:n], carry_in, Sum[1:n],

carry_out);
It is instantiated as follows.

ADDER A_inst (x,y,cin,s,co);

Which of the following is the correct "assert" statements?

assert (x+y+cin == s)

assert (s > x+y+c_in)

assert (s+co*2**n == x+y+cin)

assert (s+co*2 == x+y+cin)

0/1 point

12. Comments are inserted in Verilog using

$display statements

Lines beginning with #

Lines beginning with %

None of the above

1/1 point

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5/30/2018 Design Verification Quiz 4 Survey

13. A company sells an IP for a combinational multiplier

which can multiply two 8-bit numbers. Their customers
make a request for a multiplier that can multiply an 8-bit
number with a 16-bit number. Which of the following
language features in Verilog helps in designing such a
module?

if-else

parameter

parameter and defparam

parameter, defparam and assert

0/1 point

Done

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