Soft Switching Three Level Inverter with Passive Snubber Circuit

(S3L Inverter)

Manfred W. Gekeler
HTWG KONSTANZ
HOCHSCHULE KONSTANZ TECHNIK, WIRTSCHAFT UND GESTALTUNG
UNIVERSITY OF APPLIED SCIENCES
Brauneggerstrasse 55
D – 78462 Konstanz; Constance, Germany
Tel.: +49 / (0) – 7531.206.220
Fax: +49 / (0) – 7531.206.87.220
E-Mail: gekeler@htwg-konstanz.de
URL: http://www.htwg-konstanz.de

Keywords
«Voltage Source Inverter (VCS)», «Soft Switching», «Multilevel Converters», «Switching Losses»,
«Efficiency»

Abstract
Presented here is a three level voltage source inverter for electric drives, uninterruptable power
supplies and for mains feeds. Unlike the usual hard switching topologies, it is implemented as
completely soft switching. A novel patented snubber circuit is added, which is structured very simply
and consists of only a few passive components. This snubber circuit works in principle without any
losses; all switching operations in the three level voltage source inverter are in principle free of
switching losses. For this reason, very high values of switching frequency up to about 40 kHz, and
very high efficiencies up to more than 98%, can be realized, even with utilization of economical
standard IGBT's. In particular with utilization of IGCT's, an effective di/dt limitation is to be
emphasized, which works without additional inductive voltage stressing of the IGCT's.

Introduction:
Voltage source inverters have been used for a long time, in particular for feeding speed-variable AC
drives, for uninterruptable power supplies and in photovoltaics as a mains feed-in inverter. Compared
to the frequently-used 2-level implementation, three level voltage source inverters indicate a series of
advantages. The output voltage indicates 3 levels. This can be used to advantage in different ways: In
case of similar pulse frequency (number of pulses of the output voltage per second), the ripple of the
load current is smaller than in case of the 2-level type, and the output-side smoothing inductor can be
significantly smaller. Alternatively, lower values can be selected for the pulse frequency.

State of the art

Usually three level voltage source inverters are operated with hard switching, thus they indicate
switching losses. This comes about because, during switching on and off operations on the power
semiconductor used (mainly IGBT's or IGCT's) simultaneous high values of the voltage and current
occur in principle. The product of both gives the switching losses which can assume extremely high
values [1]. This power-dissipation peak is present for a short time only; however, multiplied by the
frequency, thus the switching frequency of the power semiconductors, considerable switching losses
result averaged over time, which are undesirable and which limit the possible output power of the
inverter and reduce the efficiency.

These switching losses with the three level source voltage inverter are already reduced considerably
compared to two level types, as a result of the lower level of the voltage steps with switching of the
power semiconductors. However, they are significantly noticeable and decrease the efficiency, in
particular in case of higher values of the switching frequency.

In order to further reduce switching losses or to avoid them entirely, different technologies are known
under the general term "soft switching". Snubber circuits are suitable to avoid switching losses in the
transistors, but most of them produce losses in other components e.g. resistors [2]. For two level
voltage source inverters loss-free snubbers have been developped; e.g. [3]. For three level voltage
source inverters, however, different approaches are proposed in the literature which do not satisfy.
Thus e.g. the proposal [4] is very expensive and the number of power semiconductors is doubled. The
circuits according to [5] and [6] are not loss-free, and the approach according to [7] indicates inferior
efficiency and very limited possibilities of a pulse control process.

In case of inverters with Integrated Gate Commutated Thyristors (IGCT's), an effective di/dt limitation
is required during switching on [8]. This results in a series of disadvantageous features. This is dealt
with more exactly in a separate chapter.

The new approach

The objective of the "Soft Switching Three Level Inverter with Passive Snubber Circuit " presented
here consists in its indicating a very simple circuit which, compared to a hard switching three level
inverter, indicates only a small additional outlay of exclusively passive components, which in
principle avoids all switching losses and guarantees an effective di/dt limitation, as well as a du/dt
limitation.

Fig. 1 indicates the schematic circuit diagram of the "Soft Switching Three Level Inverter with Passive
Snubber Circuit" (abbreviated to S3L inverter). The starting point is the circuit of a three level inverter
with hard switching, consisting of the 4 IGBT's V1 to V4, and the 4 diodes D1 to D4. As is known, the
output terminal can be connected alternatively with the positive terminal, with the negative terminal or
with the central neutral tap of the input direct voltage Ud. A change between these 3 switching states
should be designated as commutation. With suitable e.g. sine-weighted pulse control processes, an
approximately sinusoidal load current with given frequency and amplitude can be achieved. This is not
dealt with in any further detail in the following.

Snubber Circuit

Dh1
C1 V1 D1

Ud /2 V2
Dh2 D2
L

Dh3 D3
V3

Load
Ud /2 C2 V4 D4
Dh4
u Load

Fig. 1: Schematic circuit diagram of the "Soft Switching Three Level Inverter" (S3L inverter)

Compared with the well known circuit of a "Neutral Point Clamped Three Level Inverter" (NPC
inverter) [9], this arrangement indicates the disadvantage that the IGBT's V1 and V4, as well as the
diodes D1 and D4, must be designed for the full input direct voltage; in case of the NPC inverters, all
power semiconductors must be capable of blocking only half the input direct voltage. The advantage
of the circuit represented, however, consists in the fact that whenever the output is switched to the
positive or the negative input direct voltage, thus V1, V4, D1 or D4 are conducting, only 1 power
semiconductor is flowed through by the load current, unlike the NPC inverter, where 2 power
semiconductors are always switched in series. In this way, the conduction losses are significantly less.

This three level inverter, consisting of the 4 IGBT's V1 to V4 and the 4 diodes D1 to D4, now has a
novel and patented [10] snubber circuit added to it, consisting of the inductor L, the two capacitors C1
and C2, as well as the 4 diodes Dh1 to Dh4. It participates in each of the designated commutation
processes. It can first be determined that there are a total of 6 possible commutation processes with
positive load current:

Table I: Possible commutations with positive load current

Commutation V1 → D3, V3 D3, V3 → V1 D3, V3 → D4 D4 → D3, V3 V1 → D4 D4 → V1
Admissible yes yes yes yes no no
Involved C2 C2 C1 C1 - -

In case of negative load current, there are correspondingly available a further 6 commutation
processes, however, which progress symmetrically.

As special cases, the commutation processes can be indicated with zero load current (or very low value
of the load current). For reasons of symmetry, it is enough to consider 3 of these:

Table II: Possible commutations with zero load current

Commutation V1 → D3, V3 D3, V3 → V1 V1 → D4
Admissible: yes yes no
Involved C2 C2 -

Operation mode
Each of these commutation processes progresses a little differently. For clarification, 2 commutation
processes should be considered more exactly as an example. It should be assumed that the load current
is approximately constant during the commutation process:

Commutation V1 → D3, V3
Before beginning the commutation process, V1 carries the positive load current I_Load. V3 is
switched on (however does not carry any current because of the diode D3), V2 and V4 are switched
off. The output terminal is connected with the positive terminal of the input direct voltage. The
capacitor C1 is discharged, the capacitor C2 is charged to –Ud. The current in the inductor L is zero
(Fig. 2a).

iV 1 = I Load (1)
uV 1 = 0 (2)
u C 2 = −U d (3)
iL = 0 (4)

The commutation process V1 → D3, V3 begins with the switching off of V1. Simultaneously V2 is
switched on. V3 remains switched on, V4 switched off. The commutation process now following
consists of 2 time intervals:

Time interval 1 ( t 0 ≤ t < t1 ): 2 Electric circuits are building: C2 with D2, V2, L, Ud/2 and Dh4 forms
a resonant circuit. Simultaneously, a current flows over C2, the load, the central tap of the input direct
voltage Ud, the lower half of Ud and the diode Dh4. Both electric circuits overlay (Fig 2b). What is
important in this case is that the current through V1 very rapidly decreases to zero, while the voltage at
V1 increases with only limited slope, so that the product of voltage and current, that is the power
dissipation, has only very small values. The switching-off procedure of V1 is thus without switching
losses.
iV 1 = 0 (5)
U U 1
uV 1 = d − d cos ω (t − t0 ) + L I Load sin ω (t − t0 ) with ω = (6)
2 2 C 2 LC 2
U U
uC 2 = − d − d cos ω (t − t 0 ) + L I Load sin ω (t − t 0 ) (7)
2 2 C2
Ud
2 sin ω (t − t ) − I
iL = − 0 Load cos ω (t − t 0 ) + I Load (8)
L
C2
Time interval 2 ( t1 ≤ t < t 2 ): Time interval 1 of the commutation process ends with the capacitor C2
being discharged and the diode D4 begins to conduct. Approximately synchronously, the current
through the inductor L comes to zero, D2 blocks, V3 and D3 begin to conduct (Fig. 2c). Since, during
this time interval 2, a constant voltage in the amount of Ud/2 is applied on the inductor L, its current
increases linearly with respect to time; vice versa the current through D4 decreases linearly with
respect to time.
Ud
iV 3 = 2 (t − t ) (9)
1
L
uV 3 = 0 (10)
uC 2 = 0 (11)
Ud
iL = 2 (t − t ) (12)
1
L

As soon as the current through D4 now comes to zero, and simultaneously the current through the
inductor L assumes the value of the load current, the commutation process is ended: D4 blocks, V3
and D3 conduct the load current (Fig 2d). C2 is discharged.

iV 3 = I Load (13)
uV 3 = 0 (14)
uC2 = 0 (15)
i L = I Load (16)

Fig. 3 indicates the time sequences of different voltages and currents under ideal conditions.

It is noted that all changes in current occur in V2, D2, V3 and D3 with limited slope di/dt only. The
switch-on procedure of V3 is thus also without switching losses, the power dissipation is at a low level
only. A significant feature is also that the current through D4 decreases only with limited di/dt; this
considerably reduces the reverse recovery charge and the losses resulting from this.

It is further pointed out that, with sufficiently large load current, V2 does not have to be switched on at
all. Then the described resonant circuit is dispensed with, the discharging of C2 is implemented
exclusively through the load current. However, since the period of this time-linear discharging
depends on the level of the load current, and can last very long particularly with low values of the load
current, which is mostly not desired, V2 is switched on. Then the discharge of C2 is additionally
implemented over the described resonant circuit, and the discharge time of C2 is limited to maximum
of half the period of the resonant circuit.
 V1 D1 V1 D1
0 0 0 0
u V1 u V1

Ud /2 V2 V2
D2 Ud /2 D2
I Load L ILoad
L

0 0 iL uL
Dh3 u C2 D3 Dh3 u C2 D3
V3 V3

Load Load
i C2
Ud /2 C2 C2
Dh4 Ud /2 Dh4
u Load u Load

a) b)

V1 D1 V1 D1
0 0 0 0
u V1 u V1

V2 V2
Ud /2 D2 Ud /2 D2
L I Load L I Load

0 iL 0 iL
uL uL
Dh3 u C2 D3 Dh3 u C2 D3
V3 V3

0 0 Load 0 0 Load
i C2 i C2
C2 C2
Ud /2 Dh4 Ud /2 Dh4

u Load u Load

c) d)

Fig. 2: Commutation V1 → D3, V3

It should be further pointed out that the capacitor C1, as well as the diodes Dh1 and Dh2, do not
participate in the commutation process considered.

black: uLoad; red: iL; blue; uC2 red: iV1; blue: uV1

Fig. 3: Commutation V1 → D3, V3; Ud/2 = 100; ILoad = 100

(simulation results; experimental results are shown in Fig. 5))
Commutation D3, V3 → V1
Before beginning the commutation process, V3 and D3 carry the positive load current I_Load. The
commutation D3, V3 → V1 begins with the switching on of V1. V2 will generally be still switched on
at this time and is switched off now. V3 remains switched on, V4 is switched off.

On the one hand, during this commutation the load current changes from V3, D3, to V1, on the other
hand, the capacitor C2 is charged again to Ud. It is noted that the current rise in V1 occurs with limited
di/dt only because of the inductor L, therefore without switching losses. The charging of C2 is
implemented over the resonant circuit, which forms from the upper half of the input direct voltage, as
well as V1, C2, Dh3 and L.

C2 is not charged completely to Ud because of the limited quality factor of the resonant circuit. This
can be dealt with in two ways: Either this is tolerated and the fact that the following commutation
V1→ D3, V3 progresses not completely without switching losses is taken into account. Or the losses
in the resonant circuit are compensated. This can be realized e.g. through allowing V2 to be switched
on for a short time while V1 is already conducting. This then results in an overlapping of the
conducting duration of both valves, through which an amount of energy is inserted in the snubber
circuit which compensates its losses.

For the time intervals outside of the commutation processes, the following schematic can be indicated
for the capacitor voltages and the control signals:

Table III: Control signals and capacitor voltages

ULoad Conducting: V1 V2 V3 4 UC1 UC2

(Switching State)
+ Ud/2 V1 or D1 on off on off 0 – Ud
V2 and D2
0 or off on on off 0 0
V3 and D3
– Ud/2 V4 or D4 off on off on Ud 0

Special features of the S3L inverter

Compared to the usual hard switching topologies, the S3L inverter indicates some special features
with regard to the control. The short pause necessary with hard switching topologies between the
switching-off and the switching-on of the corresponding valves (often designated as "dead time") can
be dispensed with in case of the S3L inverter. It is not only possible to select this dead time to zero; it
can even be appropriate to use a "negative dead time", that is an overlapping, in order to compensate
losses, in particular with very small values of the load current in the snubber circuit, and to ensure a
correct recharging of the snubber capacitor. What must be absolutely avoided is a commutation
directly from the high-side to the low-side valve, and vice versa. If such a commutation is required
(e.g. in case of dynamic processes with controlled electric drives), then this commutation must be
divided up into 2 sub-processes: First a commutation from the high-side to the medium-side valve, and
then from the medium-side to the low-side valve (and vice versa).

di/dt Limitation
In case of inverters with Integrated Gate Commutated Thyristors (IGCT's), an effective di/dt limitation
is required with switching on [9]. This is generally guaranteed by the series connection of an inductor.
In order to again reduce the current in this inductor (demagnetization), an inverse voltage is necessary
in principle. The blocking voltage of the IGCT must be the sum of the input direct voltage Ud and this
inverse voltage. The IGCT must therefore be considerably over-dimensioned concerning its blocking
voltage. In addition, the magnetic energy stored in the inductor is generally converted to heat in an
ohmic resistor, which reduces the efficiency.
Both are dispensed with in case of the S3L inverter. For all power semiconductors, a very effective
di/dt limitation is present. It should be emphasized that, with the high side and the low side IGCT, no
inductors are connected in series for that, and thus no inductive voltages occur while demagnetizing.
Thus the necessary blocking voltage of the IGCT remains limited to the level of the input direct
voltage Ud. The di/dt limition is guaranteed through the inductor L, which is located in the circuit path
to the central neutral tap of the input direct voltage. The voltage necessary for its demagnetization
therefore does not stress either the high side or the low side IGCT, however, the two medium IGCT's .
They must be designed for the complete input direct voltage.

Experimental setup and results of measurement

In a first step a half-bridge S3L inverter was developed and examined in detail, in order to generate a
three-phase S3L inverter in a second step, with the following data:

Half Bridge Three Phase

Rated Power 6,7 kVA 20 kVA
Rated Current 29 A_rms 29 A_rms
Frequency 50 Hz 0 … 100 Hz
DC Voltage 700 … 1000 V 700 … 1000 V
Pulse Frequency 25 kHz 25 kHz

Fig. 4 indicates the half-bridge. The 4-layer printed circuit board was structured with a large surface
and provided with pluggable power jumpers, so that different versions of the topology could be
plugged in and examined in a simple way. A disadvantage of this structure was the increased values of
the parasitic inductances and the ohmic resistances, caused both by the not insignificant lengths of the
printed circuit board tracks; in case of the jumpers, contact resistances were observed in addition. As
measurements showed, both effects negatively affected the losses and thus the efficiency. The three-
phase structure, which was not yet finished at the time of the existing paper, will avoid these effects to
a large extent.

Fig. 4: Prototype of S3L inverter (half bridge)

With this half-bridge, all commutation processes were examined and the special features of the control
process considered (see above). Fig. 5 indicates the commutation processes already considered in the
chapter "Operating mode". It can be identified that the time sequences of the currents and voltages
behave as expected, however, a oscillation with a frequency of approx. 1 MHz occurs at the end of
commutation V1 → D3, V3. This oscillation can be attributed to parasitic inductances and
capacitances, which result for the most part from the large-area structure of the printed circuit board,
and should be reduced with the new three-phase version.
Fig. 5: Commutation V3, D3 → V1 (switching on of V1; left)
Commutation V1 → V3, D3 (switching off of V1; right)
blue: iV1 (10 A/div); red: uV1 (200 V/div); time: 4 us/div

Fig. 6: Commutation V1 → D3, V3

red: uV1 (100 V/div); blue: iV1 (10 A/div); time: 400 ns/div

Fig 7 indicates the measured efficiency with different values of the load current and, with that, the
output power with an operation corresponding to mains feed into the 3x 400 V, 50 Hz three-phase
mains. It is expected that the values with the 3-phase structure, which was not yet finished at the time
of the existing paper, will be higher, since the designated weak points of the 1-phase structure are
avoided in this case.

Efficiency
1
0,99
Efficiency

0,98

0,97
0,96
0,95
0,2 0,4 0,6 0,8 1
Relative Load Current

Fig. 7: Efficiency versus relative load current; pulse frequency 25 kHz

Conclusion
A known three level voltage source inverter was equipped with a very simple snubber circuit, which
consists of only a few passive components and has the effects of switching the inverter complete
softly, avoiding switching losses and increasing efficiency. Compared to hard switching three level
inverters, the novel and patented soft switching three level inverter with passive snubber circuit (S3L
inverter) indicates the following advantages:

• All commutation processes run without switching losses, i.e. there exists either a du/dt limitation
or a di/dt limitation or both.
• The snubber circuit works in principle without any losses.
• Therefore very high efficiency up to more than 98 % can be achieved.
• Because of the di/dt limiation, the voltages spikes induced as a result of parasitic inductances are
very small; the voltage-related over-dimensioning of the power semiconductors, which is often
necessary with hard switching topologies, can be kept very much smaller.
• In particular in case of IGCT inverters, the di/dt limitation of the S3L inverter is positively
noticeable. This is implemented without any theoretical inductive overvoltage on the high side
and low side valves. The voltage-related over-dimensioning of these valves, which is frequently
necessary because of such inductive voltage peaks, can be reduced significantly.
• Since the du/dt and the di/dt values are capable of being kept very low, a significant reduction of
the necessary EMC filtering measures is expected. However, to date this has not yet been
examined in any great detail.

Some disadvantages should not to be concealed:

• All power semiconductors must be designed for the full input direct voltage Ud.
• The snubber circuit is also active in case of small values of the load current, and contributes to the
total losses with its losses. The efficiency with low load currents is thus lower than with a hard
switching topology. However, there are approaches of a control-technical and circuit-technical
nature to deactivate the snubber circuit completely or in part with small load currents, and thus to
reduce its losses. To date, this has also not yet been examined in more detail.

References
[1] Application Handbook IGBT and MOSFET Power Modules, Chapter 1.2.3 “Hard Switching Behavior of
MOSFETs and IGBTs”, Semikron International 1998, ISBN 3-932633-24-5
[2] Application Handbook IGBT and MOSFET Power Modules, Chapter 3.8 “Soft Switching”, Semikron
International 1998, ISBN 3-932633-24-5
[3] Würslin, Rainer: Pulsumrichtergespeister Asynchronmaschinenantrieb mit hoher Taktfrequenz und sehr
großem Feldschwächbereich; Dissertation Universität Stuttgart, Germany, 1984
[4] Soft Switching Three Level Inverter; United States Patent 5,684,688; Nov. 4., 1997
[5] Voltage Clamp Snubbers for Three Level Inverter; United States Patent 5,982,646; Nov. 9., 1999
[6] ARCP Dreipunkt- oder Mehrpunktstromrichter; Offenlegungsschrift DE 199 45 864 A1; Anmeldetag
23.09.1999; Anmelder: ABB Patent GmbH; Erfinder: Ralph Teichmann
[7] Stig Munk-Nielsen et.al.: Comparison of soft and hard-switching efficiency in a three-level single phase 60
kW dc-ac converter; Aalborg University Denmark;
http://www.nsn.aau.dk/GetAsset.action?contentId=2375551&assetId=3519794, Internet 20.10.2009
[8] Data Sheet: Asymmetric Integrated Gate-Commutated Thyristor 5SHY 35L4510, ABB,
http://www05.abb.com/global/scot/scot256.nsf/veritydisplay/faee9d678a30fb23c125744b00287a56/$file/
5sy%2035l4510_5sya1232-03may%2008.pdf; Internet 11.03.2011
[9] Nabae, H. Akagi and I. Takahashi, “A New Neutral-Point-Clamped PWM Inverter”, IEEE Transactions on
Industry Applications, Vol. IA-17, NO. 5, September/October 1981, pp. 518-523
[10] 3-Stufen-Pulswechselrichter mit Entlastungsnetzwerk; Deutsche Patentanmeldung 18.02.2010;
Erteilungsbeschluss 21.02.2011; Anmelder HTWG Konstanz; Erfinder Manfred Gekeler; Aktenzeichen
10 2010 008 426.3