Signed Multiplication

Normal Multiplication
Simplifying Multiplication

 The processor can keep a running product rather than

summing at the end.

 For each ‘1’ in the multiplier we can apply an add and a shift.

 For each ‘0’ only a shift is needed.

Hardware Implementation for Signed-
Magnitude Multiplication
Description
Q multiplier
B multiplicand
A 0
 SC number of bits in multiplier
E overflow bit for A
 Do SC times
 If low-order bit of Q is 1
 A ←A + B
 Shift right EAQ
 Product is in AQ
Flow chart for Multiplication (Signed Magnitude Representation)
Multiply Operation
23 × 19 = 437
Q = 19 (10011), B = 23 (10111)
Multiplicand in B
Multiplier in Q
E A Q SC

AS ← QS + BS 0 00000 10011 101

QS ← QS + BS Add 10111
A ← 0, E ← 0
SC ← n – 1 10111
Shift 0 01011 11001 100
Add 10111
=0 =1
Qn 1 00010
Shift 0 10001 01100 011
EA ← A + B
Shift 0 01000 10110 010
Shr EAQ
SC ← SC – 1 Shift 0 00100 01011 001
Add 10111
≠0 =0 11011
SC
Shift 0 01101 10101 000
END
(Product is in AQ)
 Example: 11 × 13

Group Exercise:
Group 1: 3 X 7, Group 2: -3 X 7, Group 3: 3 X -7, Group 4: -3 X -7
Reference

 Morris Mano, “Computer System Architecture”, Pearson

Education, 3rd edition (Chapter 10)
Signed Multiplication
Normal Multiplication
Simplifying Multiplication

 The processor can keep a running product rather than

summing at the end.

 For each ‘1’ in the multiplier we can apply an add and a shift.

 For each ‘0’ only a shift is needed.

3
Hardware Implementation for Signed-
Magnitude Multiplication

4
Description
Q multiplier
B multiplicand
A 0
 SC number of bits in multiplier
E overflow bit for A
 Do SC times
 If low-order bit of Q is 1
 A ←A + B
 Shift right EAQ
 Product is in AQ

5
Flow chart for Multiplication (Signed Magnitude Representation)
Multiply Operation
23 × 19 = 437
Q = 19 (10011), B = 23 (10111)
Multiplicand in B
Multiplier in Q
E A Q SC

AS ← QS + BS 0 00000 10011 101

QS ← QS + BS Add 10111
A ← 0, E ← 0
SC ← n – 1 10111
Shift 0 01011 11001 100
Add 10111
=0 Qn =1
1 00010
Shift 0 10001 01100 011
EA ← A + B
Shift 0 01000 10110 010
Shr EAQ
SC ← SC – 1 Shift 0 00100 01011 001
Add 10111
≠0 =0 11011
SC
Shift 0 01101 10101 000
END
(Product is in AQ)

6
 Example: 11 × 13

Group Exercise:
Group 1: 3 X 7, Group 2: -3 X 7, Group 3: 3 X -7, Group 4: -3 X -7

7
Reference

 Morris Mano, “Computer System Architecture”, Pearson

Education, 3rd edition (Chapter 10)