Machine Basics /

Simple Machine Intro

CS270 Unit 2
Max Luttrell, Fall 2016
 interpreting data
• what's this?

• 0001001010011111

• could be anything!

• 16 bit unsigned int

• 16 bit signed int

• float

• an instruction for a computer to execute

 where is data stored?
memory type
slower,
cheaper, backup
(e.g. cloud, tape backup)
larger
external storage
(e.g. hard drive, flash drive)

random access memory

(RAM)
faster, more
expensive, registers
smaller
typically, data must be in a register to run an instruction on it
 running a program
• a program's instructions are typically stored
consecutively in RAM

• typical machine uses two special registers to

execute them

Instruction Register
holds current instruction
(IR)

Program Counter holds address of next

(PC) instruction to execute
 fetch / decode / execute
cycle
• Prior to running program, load PC
with address of its first instruction.
IR PC
Then repeatedly:
• Fetch
• load IR with next instruction
• increment PC
• Decode
• determine what instruction
does and where operands are
• Execute
• perform the instruction
 types of instructions -
arithmetic
• arithmetic instruction includes:

• opcode operation to perform, e.g. add,

multiply

• operands - what data to perform operation on

• where to place the result

 types of instructions -
branch
• branch instruction includes:

• under what conditions to branch

• address of next instruction to execute if we

are to branch
 types of instructions -
halt
• halt: stop the machine

• halt instruction: normal termination

• or, error condition encountered

 Instruction Set Architecture
(ISA)
• ISA: set of instructions and machine capabilities

• interface between hardware and lowest-level software

type description example
postfix calculator,
stack-based uses stack for data e.g. 3 4 + to
calculate 3+4
implicitly uses one
accumulator-
accumulator (or a select Simple Machine
based
few) for data
many general purpose
general- registers; info about all MIPS, ARM, Intel
register operands contained in x86
each instruction
 general-register
architecture types
• CISC vs. RISC

• Reduced Instruction Set Computer -

instructions are simple. Most modern
architectures are RISC

• Complex Instruction Set Computer - more

complex instructions available. Intel x86 is
CISC but with some RISC added
 addressing modes
• where are the operands?
mode description example

instruction requires both add two registers,

register source operands and store result in
destination in registers another register

one operand is in a add a register to a

mixed / register, the other operand constant, store
constant is a constant contained in result in register
instruction
MIPS mult
instruction places
one or more operands is
implicit results of multiply
implicit in the instruction
in lo and hi
registers
 memory interface
• we need to be able to read from
memory and write to memory
MBR MAR
• memory interface: array of bytes
with two special registers
• Memory Address Register
(MAR) - address of next
memory reference
• Memory Buffer Register
RAM
(MBR) - storage location for
data being read from or
written to memory
 memory cycle
• how to write to memory:
MBR MAR • access the MAR
• place contents of MBR at
memory[MAR]

• how to read from memory:

RAM • access the MAR
• retrieve contents of
memory[MAR] and put in
MBR
 register transfer language/
notation (RTL/RTN)
• all internal operations in a CPU can be described as
sequence of operations on, and transfers between registers,
and memory cycles.

• the RTL (or RTN) contains:

• operations

• operands

• ability to specify specific bits in registers

• programming constructs for CPU's logic capabilities

 Simple Machine
• Simple Machine - our first machine

• not a real machine

• use it to learn concepts

• simple accumulator-based architecture

• von Neumann architecture

 Simple Machine
memory and ISA
• Von Neumann architecture architecture: instructions for program
and data are both stored in 16-bit RAM

• 15 instructions supported

• all data is short int

• conceptually we can think of simple machine's memory as an array

of 16-bit ints

• first are the instructions, then comes the data.

• first instruction always at address 0x0

• instructions: interpreted as unsigned

• data: interpreted as signed

 instruction format

• bits 15-12: opcode; can handle 24 (16) opcodes. 0x0

thru 0xe are defined, 0xf is not

• bits 11, 10: reserved; not used

• bits 9-0: address field (if used). can be either:

• 10-bit address

• 10-bit integer
 registers
type register name description
accum accumulator
user- areg address register
accessible
ctr counter

mar memory address register

memory-
interface
mbr memory buffer register

pc program counter
instruction-
cycle
ir instruction register
 data paths

• data can flow between registers connected by arrows

• ADDR is the decoded address part of IR, i.e. IR(9:0)

simple machine programs
• always starts with PC = 0

• thus, we put our instructions in memory starting at

position 0, and then put any data after them

• simulator

• to simulate running a Simple Machine program, we

use the simulator sim (on hills)

• no assembler!

• must encode instructions in hex!

 program format
• a program file lists what should be stored in
memory, first line goes to memory address 0,
next line to memory address 1, etc.

• each line can contain one instruction or piece of

data (all instructions must come before data)

• use # for comments (can comment whole line)

• hex numbers start with 0x

 program example
• simplest program on simple machine:

0x0 # this is the HALT instruction

 program example 2
• I find this instruction at memory location 0x3:

0x900a
• opcode 9 does a subtract, specifically:

• accum = memory[address] - accum

simple machine instructions
#define HALT 0 /* halt the machine */
#define LOAD 1 /* load accumulator from memory */
#define STORE 2 /* store accumulator to memory */
#define ADDC 3 /* add counter to accumulator */
#define MVAC 4 /* move accumulator to counter */
#define JEQ 5 /* jump to address if counter equals 0 */
#define JLT 6 /* jump to address if counter is less than 0 */
#define JMP 7 /* jump to address */
#define ADD 8 /* accumulator = memory + accumulator */
#define SUB 9 /* accumulator = memory - accumulator */
#define DEC 10 /* decrement counter */
/* LA takes the memory address from the instruction and loads it
into the accumulator (load address) */
#define LA 11
/* LIA uses the memory address in the areg to load memory into the
accumulator (load indirect address) */
#define LIA 12
/* SIA stores the value in the accumulator in the memory address
found in the areg (store indirect address) */
#define SIA 13
/* MVAA moves the value in the accumulator to the areg */
#define MVAA 14
 RTL
• we can use a simple register transfer language
(RTL) to indicate movement of data between
registers, memory, and doing other CPU instructions

• generally, we have a destination register, a source

register, and a potential operation. a couple
examples:

• reg <- 0 // clear reg, e.g. accum <- 0

• reg <- reg // transfer contents from source to

destination register, e.g. accum <- mbr
 RTL

note: reg can be a register, e.g. accum,

or it can be a range of bits in register, e.g. ir(9:0)
RTL examples
 fetch cycle in RTL
• set next memory load address to address in the PC
MAR <- PC

• increment the PC
PC <- PC+1

• perform memory read

get()

• transfer instruction to IR
IR <- MBR
 example execute cycle in RTL
for SUB (opcode 9)
• transfer address in SUB instruction to MAR
MAR <- IR(9:0)

• perform memory read()

get()

• do the subtraction
ACCUM <- MBR - ACCUM

SUB: accum = memory[address] - accum

 fetch execute cycle
recap

//Fetch cycle
MAR <- PC // set the next memory address to that in the PC
PC <- PC+1 // increment the PC
get() // perform the memory cycle, placing mem[MAR] into MBR
IR <- MBR // transfer the instruction to the IR
//Execute cycle // do the instruction, in this case opcode 0x9, which is SUB
MAR <- IR(9:0) // transfer the address in the SUB instruction to the MAR
get()
ACCUM <- MBR - ACCUM // subtract the accumulator from the memory value
 fetch example
memory
addr. value
0x0 0xb030
0x1 0x200a
0x2 0xb026
0x3 0x900a
0x4 0x2009
0x5 0x0
0x6 0x0
0x7 0x0
0x8 0x0
0x9 0x0
example: PC=0x3, ACCUM=0x26 0xa 0x30
0xb 0x40
//Fetch cycle
MAR <- PC // set the next memory address to that in the PC
PC <- PC+1 // increment the PC
get() // perform the memory cycle, placing mem[MAR] into MBR
IR <- MBR // transfer the instruction to the IR
 execute example (SUB)
memory
addr. value
0x0 0xb030
0x1 0x200a
0x2 0xb026
0x3 0x900a
0x4 0x2009
0x5 0x0
0x6 0x0
0x7 0x0
0x8 0x0
0x9 0x0
now PC=0x4, ACCUM=0x26, IR = 0x900a 0xa 0x30
0xb 0x40
//Execute cycle // do the instruction, in this case opcode 0x9, which is SUB
MAR <- IR(9:0) // transfer the address in the SUB instruction to the MAR
get()
ACCUM <- MBR - ACCUM // subtract the accumulator from the memory value
 Exercise 2A

• Linux basics and simple machine intro

http://fog.ccsf.edu/~mluttrel/cs270/exercises/ex2a.html
 Exercise 2B
• In today's class, we looked at the the RTL for
opcode 0x9, which is SUB.

• Write RTL for the following instructions:

• 0x5 JEQ // jump to address if counter
equals 0

• 0x1 LOAD // load accumulator from memory

• note: you will need to use the memory

interface (MAR and MBR, and get()) for this