ASYNCHRONOUS DEC TESTBENCH

module test;
reg rst,clk,en;
wire [3:0] q;
asyndecade counter1(rst , clk , en,q);
initial
begin
clk= 1'b0;
forever #100 clk = ~ clk;
end
initial
begin
rst = 1'b1;#200;
rst = 1'b0;
en=1'b1;
#3300;
end
initial #3300 $finish;
endmodule