Verilog Design of Full Adder Based on Reversible
Gates*
Varun Pratap Singh
Department of Electronics & Communication Engineering
PremPrakash Gupta Institute of Engineering
Bareilly, India
varun1select@hotmail.com
Abstract— In modern nanotechnology and quantum
computation, reversible logic plays a pivotal role as it has
minimal impact on physical entropy. Reversible logic gates have
same number of input and output hence power loss due to bit
erase operation can be avoided. There are many reversible logic
structures which can perform different Arithmetic and logic
operations as traditional or classical logic structures can do. In
this paper, two reversible logic structures are proposed which
can perform operation of addition. These logic structures namely
proposed design I and Proposed design II, generate carry output
signal and carry propagate signal on the basis of two reversible
logic gates known as Fredkin gate and Feynman gate.
Performance of proposed designs is evaluated in terms of
quantum cost, constant input, garbage output and delay. It is
found that proposed design II is a better choice over proposed
design I and some other existing Designs.
Keywords—Fredkin Gate; Feynman Gate; Quantum Cost;
Reversible Adder;
I. INTRODUCTION
In logic circuit information is represented either by logic
level 0 or by logic level 1. These logic levels are known as bit.
Overwrite and erase operations of these bits lead towards the
consumption of energy as these bits are represented by voltage
levels. According to the Landauer [1] if energy consumption
in bit erase is considered, an n input and single output gate
provides a loss of (n-1) information bit while going through
the classical logic gate. One bit of information has energy of
KT ln2 where k is the Boltzmann constant and T is the
absolute temperature thus any (n×1) classical logic gate losses
this much energy for every bit of information loss. C.H.
Bennett [2, 3] showed that dissipated energy is directly
correlated with number of lost bits as well as computer can be
made logically reversible with the virtue of maintaining its
simplicity and provide accurate calculation at practical speed.
AND gate can be considered as an example of energy loss in
irreversible logic circuit. It follows ordinary logic and can be
said traditional or classical logic gate. Output of any AND
gate comes to be logic 0 for three combinations of input bits. It
appears logic 1 for only one combination of inputs. Thus it
erases and overwrites 0 for three different combinations which
is nothing but loss of energy. To resolve this problem,
reversible logic gates can be used. It provides same number of
input and output with unique input output combinations.
978-1-5090-3480-2/16/$31.00 ©2016 IEEE
Manish Rai
Department of Electronics & Communication Engineering
MJP Rohilkhand University
Bareilly, India
manishrai1968@gmail.com
The key point of reversible computing is that the electric
charge at output of any device should remain available for
further calculations. It means transistor should not follow the
process of flow of charge when the transistor is switched
between on/off positions [4]. In this way output can be reused
through reversible computation. When there is no information
bit loss while approaching towards output from input or vice
versa, system is reversible. To perform this type of
computation, it is necessary to have some n × n logic devices
which can substitute traditional or classical n × 1 logic
devices.
II. BASIC DEFINITIONS ABOUT REVERSIBLE LOGIC GATE
If matter of performance is discussed, reversible logic
gates have some parameters namely quantum cost, constant
input and garbage output. Also, delay in circuit and number of
transistors used are important factors to consider while
designing any reversible logic structure.
A. Garbage outputs
In order to ensure reversibility, number of outputs and
inputs should be equal. Sometimes all the outputs of reversible
gates are not used in next stage. Some of them exist to
maintain equality between number of inputs and outputs.
These outputs are known as garbage. Relation between the
number of garbage outputs and constant inputs can be given
below in (1).
Input + constant input = output + garbage (1)
B. Quantum cost
There are two primitive reversible logic gates with input-
output relation as 1×1 or 2×2. These reversible primitive gates
are NOT gate and Controlled NOT gate. Every reversible logic
gate and hence every reversible logic circuit can be realized in
terms of these primitive gates. Number of primitive logic gates
(either 1×1 or 2×2) used in realization of any reversible logic
circuit is called quantum cost of that circuit. In other words,
quantum cost of a reversible circuit is the minimum number of
2×2 unitary gates to represent the circuit in such a manner that,
output must not be changed. Quantum cost of a 2×2 gate is 1.
C. Delay
Delay means the travel time of input to reach an output
through shortest path of a logic circuit. It can also be given as
maximum number of gates in a path from any input line to any
output line. These definitions are based on two assumptions.
First assumption is that each gate takes one unit time to
calculate any output from given input, this unit time can be
Fig. 3. Fan-Out signal
given as 1Δ. Second assumption says that the process of
computations is considered to be started when all inputs to that
circuit are available. If total number of reversible gates in any B. Fredkin Gate (FG)
shortest path from input to output is called logical depth. This Fredkin gate as shown in Fig. 4 is a reversible 3×3 gate as
logical depth can be considered as measure of the delay as proposed in [8]. Relation between inputs (X3, X2, X1) and
proposed by Mohammadi and Eshghi [5]. Each 1×1 gate and outputs (Y3, Y2, Y1) of Fredkin gate is given by (4), (5) and
2×2 reversible gate is taken as unit delay 1. Other reversible (6).
gates can be derived from these primitive gates and hence
their delay can also be calculated. Y3 = X3 (4)
III. SOME REVERSIBLE LOGIC GATES
A reversible logic gate should follow property of bijection Y2 = ⎯X3· X2 +X3·X1 (5)
between input and output. It means number of inputs and
number of outputs is equal and output can be uniquely Y1 = X3 ·X2 +⎯X3 ·X1 (6)
generated for given input combinations. Similar to classical
logic gate, reversible logic gate can be designed by using pass Fredkin gate has the property to swap the inputs according to
transistor as given in [6] or CMOS logic as given in [7]. the value of control signal as given in (7) and (8). X3 is control
Reversible logic gates used in proposed designs are Feynman signal in this case.
[4] gate and Fredkin gate [8].
A. Feynman (F) / CNOT Gate Y2 = X2 & Y1 = X1 when X3 = 0 (7)
The Feynman gate as shown in Fig. 1 is also called CNOT
gate, is the fundamental reversible logic gate as describe in [4] Y2 = X1 & Y1 = X2 when X3 = 1 (8)
has mapping of input (X1, X0) to output (Y1, Y0) as shown in
(2) and (3).

Y1 = X1 (2)

Y0 =X0 ⊕ X1 (3)

According to quantum representation shown in Fig. 2, Fig. 4. Fredkin Gate

Quantum cost of Feynman gate is one and delay according to
[5, 9] is 1ǻ. It can also be used to generate fan out signals by
keeping one input at ground according to Fig. 3.

Fig. 1. Feynman Gate Fig. 5. Quantum representation of Fredkin Gate

Quantum representation of FG is shown in Fig. 5. Since there

are 2 CNOT gate, 1 V gate and 2 other 2×2 gates each with
quantum cost 1. In this way, the quantum cost of FG is 5 and
delay according to [5, 9] is 5ǻ. If one input of this gate is kept
at logic 1 and another at logic 0 as shown in Fig. 6, it can also
be used to create inverse and fan out function simultaneously.
Fig. 2. Quantum Representation of Feynman Gate
Two input AND gate can be generated by grounding one
terminal as shown in Fig. 7. Two input OR gate can be
generated by tying one terminal of FG to supply voltage as
represented in Fig. 8. Higher order AND and OR logic can be
realized by using FG arranged in binary tree. Realization of B
bit AND gate requires B-1 FGs arranged in binary tree
manner. In this type of structure input passes a maximum of
log2N FGs [10].

Fig. 6. Fan-out signal

Fig.9. Proposed Adder design I

The adder shown in Fig. 9 has quantum cost of 10, 2 constant

inputs and 2 garbage outputs. Delay in sum signal generation is
3F and delay in carry output signal generation is 1FG+2F.
Carry propagate signal is generated after the delay of 3F. In
design I Cout signal and Sum signal are generated
simultaneously.
Fig. 7. Logical 'AND ' operation
B. Proposed Design II
The proposed adder design II, consist of 1 Fredkin gate and 3
Feynman gates. One out of three Feynman gates are used to
generate fanout signal remaining two Feynman gates are used
to generate carry propogate signal. Fredkin gate is used to
select either Xi or Cin as carry out signal on the basis of
Xi⊕Yi signal.
Fig. 8. Logical 'OR' operation

IV. ADDER BASED ON REVERSIBLE LOGIC

Similar to classical logic, arithmetic operations can be
performed in reversible logic. Various reversible logic
structures are suggested by [10, 11, 12, 13, 14] which can
perform addition with carry. Most of these are carry skip
adder with different quantum cost, garbage output and
constant input. For example, reversible adder described in
[14] is based on single reversible gate namely TSG with
quantum cost of 13, constant input 1, garbage output equal to
2 and delay of 13 ǻ. Reversible adder given in [13] includes 3
reversible gates namely NG, Feynman gate and Toffoli gate.
Delay in sum signal and carry signal generation is
consecutively 14ǻ and 13ǻ. Reversible adder based on
Fredkin gate is given in [10]. There are two proposed designs
of reversible carry skip Adder in this work which can be
compared with all these existing designs.
Fig.10. Proposed Adder design II
A. Proposed Design I
The adder Design as shown in Fig. 9, consist of 1 Fredkin This Adder shown in Fig.10 has quantum cost of 8, one
gate and 5 Feynman gates. Two out of five Feynman gates are constant input and one garbage output. Delay in sum signal
used to generate fan-out signal remaining three Feynman gates generation is 3F and delay in carry output signal generation is
are used to generate carry propagate signal .Fredkin gate is 1FG+2F. Carry propagate signal is generated after the delay of
used for making either Xi or Yi as carry out signal on the basis 2F. In design II Cout signal is generated after Sum signal.
of signal Xi ْCin.
 V. RESULTS
Both of these designs are prepared in Verilog and simulated on
Modelsim (By Mentor Graphics). Simulation waveform is
shown for each signal of proposed designs.
A. Output Waveform of Design I
Output wave form corresponding to design I, is given in
the Fig.11. There are three inputs namely A, B, C_IN and
three outputs namely SUM, C_OUT and carry propagate
signal P. In design I, carry signal and Sum signals are obtained
simultaneously. Only Pr (XiْCin) signal is shown to use in
any enhanced design in future.
VI. CONCLUSION
Finally, there are two proposed designs of reversible full adder
in this text. According to Table I, proposed design II is better
choice over proposed design I in terms of quantum cost,
constant input and garbage output. As far as delay is
concerned, both proposed designs are almost equal as shown
in Table II. Here delay is given in terms of FG and F, which is
5ǻ and 1ǻ, corresponding to Fredkin and Feynman gate.
Generation of carry skip signal is an important feature of both
the proposed designs. Due to this feature higher order bits can
be added faster than any other design.
If other existing designs are considered, reversible adder
given in [14] is better in terms of number of gates used in
design but proposed design II is better in terms of quantum
cost, garbage output and constant input. For these terms,
proposed designs II is also better than the designs described in
[10, 11 and 13]. In terms of delay in various signal
generation, proposed design II is better than those described in
[10, 11, 13, 14]. As well as proposed design I provides a
garbage output Xi ْ Cin which can be used to extend the
circuit to obtain arithmetic and logic operations in future.

TABLE I : PARAMETER COMPARISON

Parameters
Parameter
Comparison Garbage Constant
Quantum Cost
output Input
Proposed
Design I
10 2 2
Proposed
Design II
8 1 1
Fig.11. Waveform I

TABLE II: DELAY COMPARISON

B. Output Waveform of Design II Delay
Delay
Output wave form corresponding to design II, is given in the Comparison Sum Carry Out Propagate
Fig. 12 There are three inputs namely A, B, C_IN and three Proposed
3F 1FG+2F 3F
outputs namely SUM, C_OUT and carry propagate signal Pr Design I
Proposed
(AْB). 3F 1FG+2F 2F
Design II

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