Professional Documents
Culture Documents
A Course Material
on
Embedded Systems
By
V.Suresh
Assistant Professor
Electrical and Electronics Engineering Department
Quality Certificate
Year/Sem:III/VI
Name: V.Suresh
This is to certify that the course material being prepared by Mr.V.Suresh is of the
adequate quality. He has referred more than five books and one among them is from
abroad author.
Seal: Seal:
OBJECTIVES:
To introduce the Building Blocks of Embedded System
To Educate in Various Embedded Development Strategies
To Introduce Bus Communication in processors, Input/output interfacing.
To impart knowledge in Various processor scheduling algorithms.
To introduce Basics of Real time operating system and example tutorials to discuss on one
realtimeoperating system tool
TOTAL: 45 PERIODS
OUTCOMES:
Ability to understand and analyse, linear and digital electronic circuits.
TEXT BOOKS:
1. Rajkamal, ‘Embedded System-Architecture, Programming, Design’, Mc Graw Hill, 2013.
2. Peckol, “Embedded system Design”, John Wiley & Sons,2010
3. Lyla B Das,” Embedded Systems-An Integrated Approach”, Pearson, 2013
REFERENCES:
1. Shibu. K.V, “Introduction to Embedded Systems”, Tata Mcgraw Hill,2009.
2. Elicia White,” Making Embedded Systems”, O’ Reilly Series,SPD,2011.
3. Tammy Noergaard, “Embedded Systems Architecture”, Elsevier, 2006.
4. Han-Way Huang, ”Embedded system Design Using C8051”, Cengage Learning,2009.
5. Rajib Mall “Real-Time systems Theory and Practice” Pearson Education, 2007.
CONTENTS
1 Unit – I 6
2 Unit – II 36
3 Unit – III 63
4 Unit – IV 76
5 Unit – V 105
Unit – I
2. What are the different types of memory used in embedded system design?
(CO1-L1)
Volatile Memory Module – RAM
Non- Volatile Memory-ROM Memory
3. What are the steps involved in the build process? (CO1-L1- April/may 2016)
5. Decide how suitable memory will be selected for the design of the embedded
system? (CO1-H2)
Selection of suitable memory is very much essential step in high performance
applications, because the challenges and limitations of the system performance are
often decided upon the type of memory architecture. Systems memory requirement
depend primarily on the nature of the application that is planned to run on the system.
Memory performance and capacity requirement for low cost systems are small, whereas
memory throughput can be the most critical requirement in a complex, high
performance system. Following are the factors that are to be considered while selecting
the memory devices,
Speed
Data storage size and capacity
Bus width
Latency
Power consumption
Cost
7. What are the different modes of DMA transfer? Which one is suitable for
embedded system? (CO1-L1)
Single transfer at a time and then release of the hold on the system bus.
Burst transfer at a time and then release of the hold on the system bus. A burst
may be of a few kB.
Bulk transfer and then release of the hold on the system bus after the transfer is
completed. Most suitable
Power, cost and reliability are often important attributes that influence
design;
Application specific processor design can be a significant component of
some
embedded systems.
Other characteristics:
• Application specific
• Digital signal processing in ECS
• Reactive
• Real-time
• Distributed
23. What are the two essential units of a processor on an embedded system?
(CO1-L1)
1. Program flow control unit (CU)
2. Execution unit (EU)
24. What does the execution unit of a processor in an embedded system do?
(CO1-L1)
The execution unit implements data transfer and data conversion. It includes
ALU and circuits that execute instruction for jump, interrupt, etc.,
28. Give some examples for small scale embedded systems. (CO1-L1)
68HC05, PIC 16F8x, 8051, etc.,
29. Give some examples for medium scale embedded systems. (CO1-L1)
8051, 80251, 80x86, 80196,68HC11xx
Part – B
Data memory can be used to store primarily two kind of information. One
is relating to the intermediate data being processed- for e.g. a variable storing a
value during course of execution of an algorithm or a Process Control Block in
an OS etc. The other is the Stack which is used by the processor to store its
return functions and local variables. In either case the memory type is volatile.
Following are the factors that are to be considered while selecting the memory
devices,
Speed
Data storage size and capacity
Bus width
Latency
Power consumption
Cost
SRAM’s have lower data storage and capacity hence they are suitable for lower
end systems where as SDRAM for higher end systems with complex
requirements.
Among the high speed types of SDRAM, DDR2 memory modules can have
memory capacities from 256MB to 4GB capacities. Most of the DDR2 memory
chips come in FBGA (Fine Ball Grid Array) package. The package allows higher
memory densities in smaller space with better electrical properties. DDR2
memory uses 1.8V for power, resulting in lower power and cooler operation,
whereas the DDR uses 2.5V.
Further there are variations of DDR available that are fine tuned for particular
applications. For example, the Graphic DDR (GDDR) memory is designed for
higher performance than the standard DDR memory. To achieve this, they
operate at additional voltage of 2.0V. But the capacity of GDDR memory devices
in comparison to DDR tends to be reduced typically from 256Mb to 512Mb. This
enables them to be used in resource intensive video cards. On the other end of
the spectrum, Mobile DDR (MDDR) memory devices are optimized for low
power applications such as battery operated and handheld devices. In deep
power down (DPD) mode of operation, their current can go as low as 10uA.
The data rates are defined by the RAM manufacturer and are based on various
factors such as CAS latency, RAS-CAS delay etc. Even a increase of 0.5 cycle,
can impact a change of up to 10% of speed.
Again, these high speed varieties of SDRAM needs careful PCB layout with
signal integrity considerations including presence of suitable terminations.
Obviously a 32-bit width memory can fetch more data in a same cycle as a 16
bit memory. Thus more the data width, better the transfer rate, provided the data
line support is available.
that allows programming the flash but needs the application to be stopped at
that time. Or it could be IAP (In-Application Programming) that will allow re-
programming of the memory even when the application firmware is running. This
is determined by the memory architecture. Nowadays many microcontrollers
support both the options and ISP is used for manufacturing and IAP is
appropriate for field updates.
Though nowadays the memory controllers available in the SoC primarily dictate
the selection of the memory devices, we believe this blog provides a good
insight about various memory technologies, their application and selection. In
the next blog, we will analyze about the power supply design in an embedded
system.
2. Quote in brief about the various steps involved in the Embedded System build
process. (CO1-L2- APRIL/MAY 2016)
When build tools run on the same system as the program they produce,
they can make a lot of assumptions about the system. This is typically not the
case in embedded software development, where the build tools run on a host
computer that differs from the target hardware platform. There are a lot of things
that software development tools can do automatically when the target platform is
well defined. [1] This automation is possible because the tools can exploit
features of the hardware and operating system on which your program will
execute. For example, if all of your programs will be executed on IBM-
compatible PCs running Windows, your compiler can automate—and, therefore,
hide from your view—certain aspects of the software build process. Embedded
software development tools, on the other hand, can rarely make assumptions
about the target platform. Instead, the user must provide some of her own
knowledge of the system to the tools by giving them more explicit instructions.
1. Each of the source files must be compiled or assembled into an object file.
2. All of the object files that result from the first step must be linked together
to produce a single object file, called the relocatable program.
3. Physical memory addresses must be assigned to the relative offsets within
the relocatable program in a process called relocation.
The result of the final step is a file containing an executable binary image that is
ready to run on the embedded system.The embedded software development
process just described is illustrated in Figure In this figure, the three steps are
shown from top to bottom, with the tools that perform the steps shown in boxes
that have rounded corners. Each of these development tools takes one or more
files as input and produces a single output file. More specific information about
these tools and the files they produce is provided in the sections that follow.
3. List and explain the various hardware units that must be present in the
embedded systems. (CO1-L1)
(ALU), and for instructions for aprogram control task, say, datatransfer
instructions, halt, interrupt,or jump to another set of instructionsor call
to another routine or sleep orreset
Rather than simply stating the clock frequency of the processor which has
limited significance to its processing power, it makes more sense to describe the
capability in a standard notation. MIPS (Million Instructions Per Second) or
MIPS/MHz was an earlier notation followed by Dhrystones and latest EEMBC’s
Processor architectures with support for extra instruction can help improving
performance for specific applications. For example, SIMD (Single
Instruction/Multiple Data) set and Jazelle – Java acceleration can help in
improving multimedia and JVM execution speeds.
Power Considerations
Increasing the logic density and clock speed has adverse impact on power
requirement of the processor. A higher clock implies faster charge and
discharge cycles leading to more power consumption. More logic leads to higher
power density there by making the heat dissipation difficult. Further with more
emphasis on greener technologies and many systems becoming battery
operated, it is important the design is for optimal power usage.
Peripheral Set
Every system design needs, apart from the processor, many other peripherals
for input and output operations. Since in an embedded system, almost all the
processors used are SoCs, it is better if the necessary peripherals are available
in the chip itself. This offers various benefits compared to peripherals in external
IC’s such as optimal power architecture, effective data communication using
DMA, lower BoM etc. So it is important to have peripheral set in consideration
when selecting the processor.
Operating Voltages
Each and every processor will have its own operating voltage condition. The
operating voltage maximum and minimum ratings will be provided in the
respective data sheet or user manual.
While higher end processors typically operate with 2 to 5 voltages including 1.8V
for Cores/Analogue domains, 3.3V for IO lines, needs specialized PMIC
devices, it is a deciding factor in low end micro-controllers based on the input
voltage. For example it is cheaper to work with a 5V micro-controller when the
input supply is 5V and a 3.3 micro-controllers when operated with Li-on
batteries.
Specialized Processing
RISC cores supports primarily integer only instruction set. Hence presence of a
FP co-processor can be very helpful in application involving complex
mathematical operations including multimedia, imaging, codecs, signal
processing etc.
Various GPU’s like ARM’s MALI, PowerVX, OpenGL etc are increasing
available in higher end processors. Choosing the right co-processor can enable
smooth design of the embedded application.
Price
Volatile memory
Volatile memories can hold their contents only when power is continuously
applied to the memory devices. As soon as the power is removed, the contents
in the memories are lost. The primary usage is to store the data/stack as well as
storing the program instructions.
Examples of volatile memories include static RAM, dynamic RAM and static
dynamic RAM.
Generally the volatile memories used are of type Random Access Memory
(RAM) i.e. data at any address in the memory can be accessed by giving the
address in the address bus of the memory. Primarily the volatile memory is
divided in to two types:
The static RAM is a type of memory that uses bi-stable latching circuitry to store
each bit. Due to the design, the memories need not be refreshed. Thus the data
stored will be static till the duration of power being applied to the RAM.
The primary advantage of SRAM is its speed. Fast SRAMs can operate on par
with the processor speed enabling access times equal to a clock cycle used by
the microprocessor. Synchronous SRAMs are the preferred way of
implementing Instruction and Data caches in a processor system. Further since
there is no need for specialized controllers to refresh the RAM, they are easier
to use with low end microcontrollers.
The down side is that the density of the SRAMs is comparatively lower than the
DRAMs. Also the cost is comparatively higher.
DRAM stores each bit in a storage cell consisting of capacitor and transistors.
Since capacitors lose their charges quickly they need to be recharged. So by
design, each bit in the DRAM must be refreshed periodically to maintain its
contents and hence the name “Dynamic”. Due to the structural simplicity (only
one transistor and a capacitor per bit), DRAM can be packed much denser than
SRAM.
Even though they need specialized controller to take care of refreshing, their
higher density provides a higher cost to memory ratio compared to SRAM’s.
SDRAM is a type of DRAM that ‘Synchronous’ with the system bus. The
device needs a SDRAM controller typically a part of the SoC for it to function
properly. The data is organized as row and column and an internal state
machine that takes care of fetch and refresh logic.
High speed varieties of SDRAM include DDR, DDR2, and DDR3. DDR – Double
Data Rate RAMs can transfer data on both edges of the clock and hence the
name. DDR2/DDR3 has higher data width and different power requirements
even though internally they operate at the same rates as DDR.
Non-volatile memory
Non-volatile memories will retain their contents even when the power to the
memory device is removed. This makes them better choice for storing the data
that are to be retrieved after the system is restarted. The configurations settings
are typically stored in the non-volatile memory. They are typically slower than
volatile memory and require complex procedures for reading and writing.
Though there are many other kinds of technologies such as Disk-On-Chip, SSD,
MMC Cards etc, are available, the most common non-volatile memories found in
embedded systems are as follows
Flash memory
EEPROM
SD cards
Flash memory
Flash memory is a most commonly used type of non volatile memory in the
embedded system for their durability and larger number of erase cycles.
Microcontroller unit mostly contains flash memory on which the programs are
written for execution. Since flash memory is integrated on-chip with the
microcontroller, its usage become easier. Flash memory is generally
sector/block erasable, which means one sector/block of the memory can be
erased at a time in which each bit erased is moved to a state ‘1’. When it is
written, the state is changed from ‘1’ to ‘0’.
Apart from the on-chip flash memories, there are two types of flash memories
available for external storage. They are NAND and NOR flash memories
NAND flash
NAND flash memories are the most commonly used types of flash memory.
NAND type of flash memory can be written and read in blocks. They are
generally smaller and are primarily used in USB flash drives and SSD’s. They
have core cells connected in series either as 8 or 16 cells.
NOR flash
NOR flash contains core cells connected in parallel (common ground). Since
random access is supported, they are used for storing Execute in Place code.
SD cards are the type of non volatile memory commonly used in portable
devices. The SD card itself has a processor inside to take care of the complex
interface requirements as well as performing internal operations like error
correction, wear levelling etc. SD cards are also used as a boot device is most
of the high performance embedded system. Common SD card interface modes
available are SD and SPI.
Direct Memory Access (DMA) allows devices to transfer data without subjecting
the processor a heavy overhead. Otherwise, the processor would have to copy
each piece of data from the source to the destination. This is typically slower
than copying normal blocks of memory since access to I/O devices over a
peripheral bus is generally slower than normal system RAM. During this time the
processor would be unavailable for any other tasks involving processor bus
access. But it can continue to work on any work which does not require bus
access. DMA transfers are essential for high performance embedded systems
where large chunks of data need to be transferred from the input /output devices
to or from the primary memory.
DMA controller
A DMA controller is a device, usually peripheral to a CPU that is
programmed to perform a sequence of data transfers on behalf of the CPU. A
DMA controller can directly access memory and is used to transfer data from
one memory location to another, or from an I/O device to memory and vice
versa. A DMA controller manages several DMA channels, each of which can be
programmed to perform a sequence of these DMA transfers. Devices, usually
I/O peripherals, that acquire data that must be read (or devices that must output
data and be written to) signal the DMA controller to perform a DMA transfer by
asserting a hardware DMA request (DRQ) signal. A DMA request signal for
each channel is routed to the DMA controller. This signal is monitored and
responded to in much the same way that a processor handles interrupts. When
the DMA controller sees a DMA request, it responds by performing one or many
data transfers from that I/O device into system memory or vice versa. Channels
must be enabled by the processor for the DMA controller to respond to DMA
requests. The number of transfers performed, transfer modes used, and
memory locations accessed depends on how the DMA channel is programmed.
A DMA controller typically shares the system memory and I/O bus with the CPU
and has both bus master and slave capability. Fig.16.1 shows the DMA
controller architecture and how the DMA controller interacts with the CPU. In
bus master mode, the DMA controller acquires the system bus (address, data,
and control lines) from the CPU to perform the DMA transfers. Because the
CPU releases the system bus for the duration of the transfer, the process is
sometimes referred to as cycle stealing.
In bus slave mode, the DMA controller is accessed by the CPU, which
programs the DMA controller's internal registers to set up DMA transfers. The
internal registers consist of source and destination address registers and
transfer count registers for each DMA channel, as well as control and status
registers for initiating, monitoring, and sustaining the operation of the DMA
controller.
DMA controllers vary as to the type of DMA transfers and the number of DMA
channels they support. The two types of DMA transfers are flyby DMA transfers
and fetch-and-deposit DMA transfers. The three common transfer modes are
single, block, and demand transfer modes. These DMA transfer types and
modes are described in the following paragraphs. The fastest DMA transfer
type is referred to as a single-cycle, single-address, or flyby transfer. In a flyby
DMA transfer, a single bus operation is used to accomplish the transfer, with
data read from the source and written to the destination simultaneously. In flyby
operation, the device requesting service asserts a DMA request on the
appropriate channel request line of the DMA controller. The DMA controller
responds by gaining control of the system bus from the CPU and then issuing
the pre-programmed memory address. Simultaneously, the DMA controller
sends a DMA acknowledge signal to the requesting device. This signal alerts
the requesting device to drive the data onto the system data bus or to latch the
data from the system bus, depending on the direction of the transfer. In other
words, a flyby DMA transfer looks like a memory read or write cycle with the
DMA controller supplying the address and the I/O device reading or writing the
data. Because flyby DMA transfers involve a single memory cycle per data
transfer, these transfers are very efficient. Fig.16.2 shows the flyby DMA
transfer signal protocol.
Unlike the flyby operation, this type of DMA transfer is suitable for both
memory-to-memory and I/O transfers.
Single, block, and demand are the most common transfer modes. Single
transfer mode transfers one data value for each DMA request assertion. This
mode is the slowest method of transfer because it requires the DMA controller
to arbitrate for the system bus with each transfer. This arbitration is not a major
problem on a lightly loaded bus, but it can lead to latency problems when
multiple devices are using the bus. Block and demand transfer modes increase
system throughput by allowing the DMA controller to perform multiple DMA
transfers when the DMA controller has gained the bus. For block mode
transfers, the DMA controller performs the entire DMA sequence as specified
by the transfer count register at the fastest possible rate in response to a single
DMA request from the I/O device. For demand mode transfers, the DMA
controller performs DMA transfers at the fastest possible rate as long as the I/O
device asserts its DMA request. When the I/O device unasserts this DMA
request, transfers are held off.
DMA Controller Operation
For each channel, the DMA controller saves the programmed address and
count in the base registers and maintains copies of the information in the
current address and current count registers, as shown in Fig.16.1. Each DMA
channel is enabled and disabled via a DMA mask register. When DMA is
started by writing to the base registers and enabling the DMA channel, the
current registers are loaded from the base registers. With each DMA transfer,
the value in the current address register is driven onto the address bus, and the
current address register is automatically incremented or decremented. The
current count register determines the number of transfers remaining and is
automatically decremented after each transfer. When the value in the current
count register goes from 0 to -1, a terminal count (TC) signal is generated,
which signifies the completion of the DMA transfer sequence. This termination
event is referred to as reaching terminal count. DMA controllers often generate
a hardware TC pulse during the last cycle of a DMA transfer sequence. This
signal can be monitored by the I/O devices participating in the DMA transfers.
DMA controllers require reprogramming when a DMA channel reaches TC.
Thus, DMA controllers require some CPU time, but far less than is required for
the CPU to service device I/O interrupts. When a DMA channel reaches TC,
the processor may need to reprogram the controller for additional DMA
transfers. Some DMA controllers interrupt the
processor whenever a channel terminates. DMA controllers also have
mechanisms for automatically reprogramming a DMA channel when the DMA
transfer sequence completes. These mechanisms include auto initialization and
buffer chaining. The auto initialization feature repeats the DMA transfer
sequence by reloading the DMA channel's current registers from the base
registers at the end of a DMA sequence and re-enabling the channel. Buffer
chaining is useful for transferring blocks of data into noncontiguous buffer
areas or for handling double- buffered data acquisition. With buffer chaining, a
channel interrupts the CPU and is programmed with the next address and
count parameters while DMA transfers are being performed on the current
buffer. Some DMA controllers minimize CPU intervention further by having a
chain address register that points to a chain control table in memory. The DMA
controller then loads its own channel parameters from memory. Generally, the
more sophisticated the DMA controller, the less servicing the CPU has to
perform.
A DMA controller has one or more status registers that are read by the CPU to
determine the state of each DMA channel. The status register typically
indicates whether a DMA request is asserted on a channel and whether a
channel has reached TC. Reading the status register often clears the terminal
count information in the register, which leads to problems when multiple
programs are trying to use different DMA channels.
A counter is a device that stores (and sometimes displays) the number of times
a particular event or process occurred, with respect to a clock signal. It is used
to count the events happening outside the microcontroller. In electronics,
Timer Counter
A timing device such that it is set for a preset time interval and an event must
occur during that interval else the device will generate the timeout signal on
failure to get that event in the watched time interval.On that event, the
watchdog timer is disabled to disable generation of timeout or
reset Timeout may result in processor start a service routine or start from
beginning.It resets the system after a defined time.
Baud or Bit Rate Control for serialcommunication on a line or
network.Timer timeout interrupts define thetime of each baud
Input pulse counting when using atimer, which is ticked by giving
Example
•Assume that we anticipate that a set of tasks must finish in 100 ms interval.
•The watchdog timer is disabled and stopped by the program instruction in
case the tasks finish
within 100 ms interval.
•In case task does not finish (not disabled by the program instruction),
watchdog timer generates
interrupts after 100 ms and executes a routine, which is programmed to run
because there is
failure of finishing the task in anticipated interval.
The main program typically has a loop that it constantly goes through
performing various functions. The watchdog timer is loaded with an initial value
greater than the worst case time delay through the main program loop. Each
time it goes through the main loop the code resets the watchdog timer
(sometimes called “kicking” or “feeding” the dog). If a fault occurs and the main
program does not get back to reset the timer before it counts down, an
interrupt is generated to reset the processor. Used in this way, the watchdog
timer can detect a fault on an unattended embedded device and attempt
corrective action with a reset. Typically after reset, a register can also be read
to determine if the watchdog timer generated the reset or if it was a normal
reset. On the mbed this register is called the Reset Source Identification
Register (RSID)
There are different types and sizes of in-circuit emulators are available
according to the need of engineers and it depends on their project
requirements. The best in-circuit emulator can emulate a large number of
processor family simply by changing the pod and reconfiguration of emulator.
Microcontrollers or Microprocessors family are included such as Intel, Motorola,
PIC, Samsung, NXP, ARM and many more
Benefits- In-circuit emulator offers additional benefits when integrated with
compilers. When in-circuit emulators are integrated with compilers, the
build/make process is streamline so when bugs are found the code can be
quickly changed in-circuit emulator environment and retested. You can get in-
circuit emulators that can support multiple microprocessors built by different
manufacturers.
Hardware Elements in the Embedded Systems
Features- One of the greatest feature of in-circuit emulator is the ability to set
trace condition. Complex trace condition and filters allow developers to trap bug
and then look back the events that led up to the error. The trace offers the
engineers a view of what he would normally not be able to see. The trace
happens in real time which help of events that may need to happen without
delays of stopping or even slowing down the microprocessors.
So, you can choose a good in-circuit emulator that comes in your budget and
according to the compatibility of your computer or laptop as some configuration
has to be checked before buying and using emulators.
HARDWARE DEBUGGING
Embedded systems are designed to accomplish a very specific task or group of
tasks. Although no single set of constraints will factor in all embedded systems,
it is likely that the designer must balance constraints such as robustness, small
size and weight, real-time requirements, long life cycle, low price, and low (or
no) tolerance for malfunctions. According to Robert Cravotta, Technical Editor –
EDN, in his article “Shedding light on embedded debugging”, 9/4/2008 “For
each year of Embedded Systems Design’s annual market survey of embedded-
system developers, the single most requested area of improvement for
design activities is debugging tools. The percentage of respondents making this
request has remained steady at around 32% throughout the three years of the
survey.” There are many reasons why debugging is seen as the most
problematic and costly issue of the development cycle including increasing
complexity, the balance of often conflicting constraints, “increased
inaccessibility to silicon, lack of bug reproducibility and more pressure to meet
shorter
development schedule cycles.”
The trends in the industry that these reasons will continue to intensify and so
new approaches to debugging are required. In this paper we put forward some
suggestions that have been found to assist. The underlying principle is simple -
use all available tools, low level and high level, to isolate and identify the core
issue. Our suggestions are:
1. Use both high and low level debugging tools
2. Have built-in unit testing in your code
3. Make sure that your code can also run on a desktop
4. Have integrated debugging architecture in your code
5. Use memory management tools
6. Use profilers and code coverage tools
7. Use and re-use proven and well-tested software components
Unit-II
Embedded Networking
Part-A
5. Give the steps for accomplishing input output data transfer. (CO2-L3)
Accomplishing input/output data transfer There are three main methods used to
perform/control input/output data transfers. They are,
• Software programming (scanning or polling)
• interrupt controlled
• Direct memory access (DMA)
11. What are the three ways of communication for a device? (CO2-L1)
i. Separate clock pulse along with data bits
ii. Data bits modulated with clock information
iii. Embedded clock information with data bits before transmitting
22. What are the four types of data transfer used in USB? (CO2-L1)
• Controlled transfer
• Bulk transfer
• Interrupt driven data transfer
• Iso-synchronous transfer
servers to access remote storage devices without taking a large performance hit, as
would occur if these devices were simply living on the local network. Two common
solutions to this problem are double-ended SCSI and fibre-channel.
Part-B
1. Describe the functions of a typical parallel I/O interface with a neat diagram.
(CO2-L1)
card).
Master output slave input (MOSI) and Master input slave output (MISO)
MOSI when the SCLK is sent from the sender to the receiver
and slave is forced to synchronize sent inputs from the master as per
the inputs from master clock.
MISO when the SCLK is sent to the sender (slave)from the receiver
(master) and slave is forced to synchronize for sending the inputs to
master as per the master clock outputs.
Synchronous serial input is used for interprocessor transfers, audio
inputs and streaming data inputs.
Example Synchronous Serial Output
a shift register at the port to where the microprocessor writes the byte.
Synchronous serial output is used for inter processor transfers, audio outputs
and streaming data outputs. Synchronous Serial Input/output
Does not receive the clock pulses or clock information along with the
bits.
Each bit is received in each byte at fixed intervals but each
received byte is not in synchronization.
Asynchronous serial input is used for keypad inputs and modem inputs
in computers
Keypad controller serial data-in, mice, keyboard controller, modem
input, character send inputs on serial line [also called UART (universal
receiver and transmitter) input when according to UART mode]
roothub.
A hub is one that connects to othernodes or hubs.
A tree- like topology
USB Device features
Can be hot plugged (attached), configuredand used, reset,
reconfigured and used
Bandwidth sharing with other devices: Hostschedules the sharing of
bandwidth amongthe attached devices at an instance.
Can be detached (while others are inoperation) and reattached.
Attaching and detaching USB device orhost without rebooting
USB device descriptor
Has data structure hierarchy asfollows:
It has device descriptor at the root,which has number of configuration
descriptors, which has number ofinterface descriptor and which
hasnumber of end point descriptor.
Powering USB device
A device can be either bus-powered orself- powered.
In addition, there is a powermanagement by software at the host
forUSB ports
USB protocol
o USB bus cable has four wires, one for+5V, two for twisted pairs and
one forground.
host at thenode. It gives the input and gets outputbetween the physical and
data link layers atthe host node.
_ The CAN controller has a BIU (businterface unit consisting of buffer
anddriver), protocol controller, status-cumcontrolregisters, receiver-buffer
andmessage objects. These units connect thehost node through the host
interface circuit
Three standards:
1. 33 kbps CAN,
2. 110 kbps Fault Tolerant CAN,
3. 1 Mbps High Speed CAN
CAN protocol
There is a CAN controller between the CANline and the host node.
_ CAN controller ─BIU (Bus Interface Unit)consisting of a buffer and driver
_ Method for arbitration─ CSMA/AMP(Carrier Sense Multiple Access
withArbitration on Message Priority basis)
4.Explain the serial bus communication protocol using I2C. (CO2-L2- APRIL/MAY
2016)
Interconnecting number of device circuits, Assume flash memory,
touch screen,ICs for measuring temperatures andICs for measuring
pressures at a number of processes in a plant.ICs mutually network
through acommon synchronous serial bus I2C An 'Inter Integrated Circuit'
(I2C) bus,a popular bus for these circuits.Synchronous Serial Bus
Communication for networking. Each specific I/O synchronous serial
devicemay be connected to other using specificinterfaces, for example,
with I/O deviceusing I2C controller
I2C Bus communication− use of onlysimplifies the number of connections
andprovides a common way (protocol) of connecting different or same type
of I/Odevices using synchronous serialcommunication
IO I2C Bus
Any device that is compatible with a I2Cbus can be added to the
system(assuming an appropriate device driverprogram is available), and a
I2C devicecan be integrated into any system thatuses that I2C bus.
I2C Bus
The Bus has two lines that carry its signals— one line is for the clock
andone is
for bi- directional data.There is a standard protocol for the I2Cbus.
Device Addresses and Master in the I2C bus
Each device has a 7-bit address using which the data transfers take
place.
Master can address 127 other slaves at an instance.
Master has at a processing elementfunctioning as bus controller or
amicrocontroller with I2C (InterIntegrated Circuit) bus interfacecircuit.
ACTIVE STATE: An active state corresponds to the binary value 1. An active signal
state can also be indicated as logic “1”, “on”, “true”, or a “mark”.
INACTIVE STATE: An inactive signal state is stated as logic “0”, “off”, “false”, or a
“space”.
• For data signals, the “true” state occurs when the received signal voltage is more
negative than -3 volts, while the "false" state occurs for voltages more positive
than 3 volts.
• For control signals, the "true" state occurs when the received signal voltage is
more positive than 3 volts, while the "false" state occurs for voltages more
negative than -3 volts.
Disadvantage
Communication Technique
• The flair of this standard lies in its capability in tolerating the ground voltage
differences between sender and receiver. Ground voltage differences can occur
in electrically noisy environments where heavy electrical machinery is
operating.
• The criterion here is the differential-data communication technique, also
referred to as balanced-differential signaling. In this, the driver uses two wires
over which the signal is transmitted. However, each wire is driven and floating
separate from ground, meaning, neither is grounded and in this respect this
system is different to the single-ended systems. Correspondingly, the receiver
has two inputs, each floating above ground and electrically balanced with the
other when no data is being transmitted. Data on the line causes a desired
• It may be mentioned here to avoid any ambiguity in understanding the RS-422 and
the RS-423 standards, that, the standard RS-423 is an advanced counterpart of
RS-422 which has been designed to tolerate the ground voltage differences
between the sender and the receiver for the more advanced version of RS-232,
that is, the RS-232C.
• Unlike RS-232, an RS-422 driver can service up to 10 receivers on the same line
(bus). This is often referred to as a half-duplex single-source multi-drop
network, (not to be confused with multi-point networks associated with RS-
485), this will be explained further in conjugation with RS-485.
• Only one device may drive data onto the bus at a time. The standard does not
specify the rules for deciding who transmits and when on such a network. That
solely depends upon the system designer to define.
• Variable data rates are available for this standards but the standard max. data rate
is 10 Mbps, however ,some manufacturers do offer up to double the standard
range i.e. around 20 Mbps,but of course, it is at the expense of cable width. It
can connect upto 32 drivers and receivers in fully differential mode similar to the
RS – 422.
COMMUNICATION TECHNIQUE
EIA Recommended Standard 485 is designed to provide bi-directional half-duplex
multi-point data communications over a single two-wire bus.
• Like RS-232 and RS-422, full-duplex operation is possible using a four-wire, two-
bus network but the RS-485 transceiver ICs must have separate transmit and
receive pins to accomplish this.
• RS-485 has the same distance and data rate specifications as RS-422 and
uses differential signaling but, unlike RS-422, allows multiple drivers on the
same bus. As depicted in the Figure below, each node on the bus can include
both a driver and receiver forming a multi-point star network. Each driver at each
node remains in a disabled high-impedance state until called upon to transmit.
This is different than drivers made for RS-422 where there is only one driver and
it is always enabled and cannot be disabled.
• With automatic repeaters and tri-state drivers the 32-node limit can be greatly
exceeded. In fact, the ANSI-based SCSI-2 and SCSI-3 bus specifications use
RS-485 for the physical (hardware) layer.
Advantages
• Among all of the asynchronous standards mentioned above this standard offers the
maximum data rate.
• Apart from that special hardware for avoiding bus contention and ,
• A higher receiver input impedance with lower Driver load impedances are its other
assets.
All together the important electrical and mechanical characteristics for application
purposes may be classified and summarized according to the table below
. RS-232 RS-422/423 RS-485
Signaling Single-Ended Differential Differential
Technique (Unbalanced) (Balanced) (Balanced)
Unit-III
Part-A
6.Design the classic embedded product development life cycle model. (CO3-H3)
HW-SW partitioning:
Allocating elements in the refined model to either (1) HW units, or (2) SW
running on custom Hardware or a general microprocessor.
Scheduling
The times at which the functions are executed. This is important when
several modules in the Partition shares a single hardware unit.
Mapping (Implementing)
A functional description into (1) software that runs on a processor or (2) a
collection of custom, semi-custom, or commodity HW.
10.What are the different approaches used for designing embedded system.
(CO3-L1)
1. Linear/Waterfall Model
2. Iterative/Incremental/fountain model
3. Prototyping/evolutionary model
4. Spiral model
Part-B
Scheduling
The times at which the functions are executed. This is important when
several modules in the Partition shares a single hardware unit.
Mapping (Implementing)
A functional description into (1) software that runs on a processor or (2) a
collection of custom, semi-custom, or commodity HW.
Requirement analysis
Design
Development and test
Deployment and maintenance
The no of phases involved in EDLC model depends on the complexity
of the product
Classic Embedded product development life cycle model
NEED:
Any embedded product may evolves as an output of a need.
Need may come from an individual/from public/from company(generally
speaking from an end user/client)
New/custom product development
Product re-engineering
Product maintenance
ANALYSIS:
DESIGN: Deals with the entire design of the product taking the
requirements into consideration and focuses on how the functionalities can be
delivered.
• Only i/p & o/p are defined here
• Product will look like a black box
• Sent for approval from client
• Generates detailed architecture
• Detailed architecture also needs approval
DEVELOPMENT AND TESTING:
Development phase transforms the design into realizable product
Design is transformed into hardware and firmware
Look and feel of the device is very important
Prototyping/evolutionary model:
Similar to iterative model, product is developed in multiple cycles
The only difference is the model produces more refined prototype of the product at
each cycle instead of just adding the functionality at each cycle like in iterative model.
Spiral model:
Spiral model is best suited for the development of complex embedded products
and situations where the requirements are changing from customer side.
Risk evaluation in each stage helps in reducing risk
Unit-IV
RTOS Based Embedded System Design
Part-A
1. Define process.(CO4-L1)
A process is a program that performs a specific function.
15. When the error will occur when we use the semaphore? (CO4-L2)
i. When the process interchanges the order in which the wait and signal
operations on the semaphore mutex.
ii. When a process replaces a signal (mutex) with wait (mutex).
iii. When a process omits the wait (mutex), or the signal (mutex), or both.
PART-B
Process ID,
process priority,
parent process (if any),
child process (if any), and
address to the next process PCB which will run,
allocated program memory address blocks in physical memory and in
secondary (virtual) memory for the process-codes,
allocated process-specific data address blocks
allocated process-heap (data generated during the program run)
addresses,
allocated process-stack addresses for the functions called
during running of the process,
allocated addresses of CPU register-save area as a process
context represents by CPU registers, which include the program
counter and stack pointer
allocated addresses of CPU register-save area as a process
context [Register-contents (define process context) include the
program counter and stack pointer contents]
process-state signal mask [when mask is set to 0 (active) the
process is inhibited from running and when reset to 1, the process
is allowed to run],
Signals (messages) dispatch table [process IPC functions],
OS allocated resources‘ descriptors (for example, file descriptors
for open files, device descriptors for open (accessible) devices,
device-buffer addresses and status, socket- descriptor for open
socket), and
Security restrictions and permissions.
Context
Context loads into the CPU registers from memory when process
starts running, and the registers save at the addresses of register-
save area on the context switch to another process
The present CPU registers, which include program counter and
stack pointer are called context
When context saves on the PCB pointed process-stack and
register-save area addresses, then the running process
Process… heavyweight
• Process considered as a heavyweight process and a kernel-level
controlled entity.
• Process thus can have codes in secondary memory from
which the pages can be swapped into the physical primary
memory during running of the process. [Heavy weight means
its running may depend on system resources]
• May have process structure with the virtual memory
map, file descriptors, user–ID, etc.
• Can have multiple threads, which share the process structure
thread
• A process or sub-process within a process that has its own
program counter, its own stack pointer and stack, its own
priority parameter for its scheduling by a thread scheduler
• Its variables that load into the processor registers on context
switching.
• Has own signal mask at the kernel. Thread‘s signal mask
• When unmasked lets the thread activate and run.
• When masked, the thread is put into a queue of pending threads.
• A thread stack is at a memory address block allocated by the
OS.
Multiprocessing OS
Thread parameters
Thread’s stack
•
When a function in a thread in OS is called, the calling function
state is placed on the stack top.
• When there is return the calling function takes the state
information from the stack top
• A data structure having the information using which the OS
controls the thread state.
• Stores in protected memory area of the kernel.
• Consists of the information about the thread state
Thread and Task
•
Thread is a concept used in Java or Unix.
•
A thread can either be a sub-process within a process or
a process within an application program.
• To schedule the multiple processes, there is the concept of
forming thread groups and thread libraries.
• A task is a process and the OS does the multitasking.
• Task is a kernel-controlled entity while thread is a process-
controlled entity.
• A thread does not call another thread to run. A task also
does not directly call another task to run.
• Multithreading needs a thread-scheduler. Multitasking also
needs a task-scheduler.
• There may or may not be task groups and task libraries in a
given OS
Task and Task States Task Concepts
• An application program can also be said to be a program
consisting of the tasks and task behaviors in various states that
are controlled by OS.
• A task is like a process or thread in an OS.
• Task─ term used for the process in the RTOSes for the
embedded systems. For example, VxWorks and μCOS-
II are the RTOSes, which use the term task.
• A task consists of executable program (codes), state of which
is controlled by OS, the state during running of a task
represented by information of process status (running,
blocked, or finished),process-structure—its data, objects and
3. Explain the basic concepts of RTOS. What are the different types of RTOS?
Explain the features of Micro OS-II. (CO4-L2- APRIL/MAY 2016)
Kernel of an RTOS
• Used for real-time programming features to meet hard and soft real time
constraints,
• Provides for preemption points at kernel, user controlled dynamic priority
changes, fixed memory blocks, asynchronous IOs, user processes in kernel
space and other functions for a system.
Development Approaches
Types of RTOSes
4. Write the fifteen point strategy for synchronization between the ISRs, OS
functions and tasks for resource management.
ISR
• ISR is a function called on an interrupt from an interrupting source.
• Further unlike a function, the ISR can have hardware and
software assigned priorities.
• Further unlike a function, the ISR can have mask, which inhibits
execution on the event, when mask is set and enables execution
when mask reset.
TASK
Task defined as an executing computational unit that processes on a
CPU and state of which is under the control of kernel of an operating
system.
Distinction Between Function, ISR and Task Uses
• Function─ for running specific set of codes for performing a
specific set of actions as per the arguments passed to it
• ISR─ for running on an event specific set of codes for
performing a specific set of actions for servicing the interrupt
call.
Task ─ for running codes on context switching to it by OS and
•
the codes can be in endless loop for the event (s)
Calling Source
•
OS Functions provide for the use of a semaphore for
signalling or notifying of certain action or notifying the
acceptance of the notice or signal.
• Let a binary Boolean variable, s, represents the semaphore.
The taken and post operations on s─ (i)signals or notifies
operations for communicating the occurrence of an event and
(ii) for communicating taking note of the event.
• Notifying variable s is like a token ─ (i) acceptance of the
token is taking note of that event (ii) Release of a token is the
occurrence of an event
Binary Semaphore
• Let the token (flag for event occurrence) s initial value = 0
• Assume that the s increments from 0 to 1 for signalling or
notifying occurrence of an event from a section of codes in a
task or thread.
• When the event is taken note by section in another task waiting
for that event, the s
decrements from 1 to 0 and the waiting task codes start another
action.
• When s = 1─ assumed that it has been released (or sent or
posted) and no task code section has taken it yet.
• When s = 0 ─ assumed that it has been taken (or accepted) and
other task code
• section has not taken it yet
5. Explain RTOS system level functions with an example MUCOS has system
level functions. These are for RTOS initiation and start, RTC ticks initiation and
the ISR enter and exit functions. (CO4-L2- APRIL/MAY 2016).
Functions in this table pass no arguments and return type is void.
There is a global variable,OslntNesting.which increments on entering ISR.Global
variable OSlntNesting decrements on'exit"from an ISR. Initiating the operating $)stem
before
starting the use of the RTOS functions
Function void OSInit (void) operating system.
Its use is compulsory before functions.
It returns no parameter.
Starting use of RTOS multitasking functions and returning the tasks
Function void OSStart(void) is used to start the initiated operating system and
create tasks.
Its use is compulsory for the multitasking OS kernel operations.
It returns no parameter.
Starting the RTOS System clock
Function void OsTicklnit(void) is used to initiate the system clock ticks and
interrupts at regular intervals as per OS_TICKS_PER_SEC predefined during
configuring the
MUCOS.
Its use is compulsory for the multitasking OS kernel operations when the timer
functions ane to be used.
It returns no parameter.
Sending message to RTOS taking control al the start of an ISR
Function void OSlntEnter(void) is used at the start of an ISR.
It is for sending a message to RTOS kernel for taking control. Its use is
compulsory to let the multitasking OS kernel, control the nesting of the ISRs in case of
occurrences of multiple interrupts of varying priorities.
It returns no parameter.
Ready
Running
Waiting
ISR
Source files
There are two types of source files.
Master header files includes the #include preprocessor commands for all the files of
both types. It is referred to as include.h file Preprocessor dependent
8. Explain the use of Semaphores for a Task or for the Critical Sections of a Task.
Use of a Single Semaphore. (CO4-L2).
Semaphore provides a mechanism to let a task wait till another finishes. It is a way of
synchronizing concurrent process operations. When a semaphore is 'taken' by a task,
then that task has to access to the necessary resources; when given, the resources
unlock. Semaphore can be used as an event flag or as a resource key. Resource key is
one that permits use of resources like CPU, memory or other functions or critical section
codes Semaphore, which is a binary Boolean variable (or it is a signaling variable or
notifying variable.)Used as event flag. Semaphore is called binary semaphore when its
value is 0 and it is assumed that it has Boolean taken. When its value is l, it is assumed
that no task has taken it and that it has been released.
Unit-V
Embedded System Application Development
Part-A
1. Define smart card?(CO5-L1)
Smart card is one of the most used embedded systems today. It is used for
credit, debit bank card, e-wallet card, identification card, medical card (for history
and diagnosis details) and card for a number of new innovative applications
2. What are the hardware units needed to design smart card. (CO5-L1)
Microcontroller or ASIP
RAM for temporary variables and Stack
OTP ROM for application codes and RTOS codes for scheduling the tasks
Flash for storing user data, user address, user identification codes, card number
and expiry date
Timer and interrupt controller
A carrier frequency generating circuit and ASK modulator
Interfacing circuit for the IOs.
Charge pumps for delivering power to the antenna for transmission and for the
system circuits.
3. What are the Software units needed to design smart card. (CO5-L1)
6. What are the hardware units needed to design Washing machine. (CO5-L1)
Buttons, Display & buzzer, electronic circuitry.
7. What are the software units needed to design Washing machine. (CO5-L1)
It has a chip on the circuit that holds the software which drives controls &
monitors the various operations possible.
PART-B
Sequence of washing the clothes with this can be explained in few steps as follows:
2) Put the detergent Soap (of your choice like Surf n Excel etc.)
3) Put ON the tap, water rushes inside the tub. Embedded Systems
4) If its electronic control , then by the press of the keys ,you could program , if its
mechanical it shall something like an mechanical switches wherein you are allowed to
operate for setting the wash time.
5) Now the wash motor rotates and washes the clothes and gives you a beep sound
6) Now your clothes are washed …remove it from the wash tub and put it on the spin
tub and program it accordingly…after spinning clothes are dried and you
are allowed to hang it for proper drying in sunlight.
The fully automatic also comes in two category front loading as well as top loading.
i) Front loading is the one wherein you are given an opening to put clothes in on the
front side.
ii) Top loading is on the top.
iv) System Controller: Such Component is used to control the motor speed. Motor
can move in forward direction as well as reverse direction.
System Controller reads the speed of motor and controls the speed of motor in
different phases such as in Washing, Cleaning Drying etc. All kinds of Sensors
such as Door Sensor, Pressure Sensor and Keypad, Speed sensor are also
maintained by this.
b. They are built around low cost microprocessors and microcontrollers and digital
signal processors.
c. Audio controller, passenger and driver door locks, door glass control etc.
Automotive Communication Buses
Embedded system used inside an automobile communicate with each other using serial
buses. This reduces the wiring required. Following are the different types of serial
Interfaces used in automotive embedded applications:
a. Controller Area Network (CAN):-
CAN bus was originally proposed by Robert Bosch.
It supports medium speed and high speed data transfer
CAN is an event driven protocol interface with support
for error handling in data transmission.
b. Local Interconnect Network (LIN):-
LIN bus is single master multiple slave communication interface with support for data
rates up to 20 Kbps and is used for sensor/actuatorinterfacing
LIN bus follows the master communication triggering to eliminate the bus arbitration
problem
LIN bus applications are mirror controls , fan controls seat positioning controls
c. Media-Oriented System Transport(MOST):-
MOST is targeted for automotive audio/video equipment interfacing
A MOST bus is a multimedia fiber optics point–topoint network implemented in a star
ring or daisy chained topology over optical fiber cables.
MOST bus specifications define the physical as well as application layer , network
layer and media access control.
3. Design architectural hardware and software units needed in smart card.( CO5-
H3- APRIL/MAY 2016)
Smart card is one of the most used embedded systems today. It is used for
credit, debit bank card, e-wallet card, identification card, medical card (for history
and diagnosis details) and card for a number of new innovative applications.
Microcontroller or ASIP
RAM for temporary variables and Stack
OTP ROM for application codes and RTOS codes for scheduling the tasks
Flash for storing user data, user address, user identification codes, card number
and expiry date
Timer and interrupt controller
A carrier frequency generating circuit and ASK modulator
Interfacing circuit for the IOs.
Charge pumps for delivering power to the antenna for transmission and for the
system circuits.
EMBEDDED SOFTWARE COMPONENTS
Class diagram
on
SOFTWARE ARCHITECTURE
Needs cryptographic software, needs special features in its operating system
over and above the MS DOS or UNIX system features. Protected environment -OS
stored in the protected part of ROM.
• A restricted run-time environment.
• OS, every method, class and run time library should be scalable,
Optimum Code-size
• Limited use of data types; multidimensional arrays, long 64-bitinteger and floating
points and very limited use of the error handlers, exceptions, signals, serialization,
debugging and profiling. Three-layered file system for the data
• Master file to store all file headers (file status, access conditions and the file lock) A
header means file status, access conditions and the file lock.
• Dedicated file─ second file to hold a file grouping and headers of the immediate
successor• Elementary file ─ third file to hold the file header and its file data. Either a
fixed length file management or a variable file length management with each file with a
predefined offset.