Energy Ramp-Up Test Method for SOA Definition of Smart Power Switches
with Application Relevant Stress Pulses
Alfred Waukmann1,2, Michael Glavanovics1
1
KAI GmbH (Kompetenzzentrum für Automobil- und Industrieelektronik) Villach, Austria
2
FH Kärnten Villach, Carinthia University of Applied Sciences, Austria
alfred.waukmann@k-ai.at
Abstract
An empirical method for determining the Safe
Operating Area (SOA) of smart power devices with
integrated Zener clamping is described in this work. The
SOA is determined utilizing the Energy Ramp-Up (ERU)
method without reference to transient junction
temperature, which cannot be directly measured. The
presented ERU hardware has the potential to apply high
power, arbitrarily shaped, application relevant stress
pulses to the Device Under Test (DUT).
1 Introduction
Microelectronic devices such as integrated smart power
products are not replaceable in our technology-oriented
society nowadays. They are required for numerous
applications in the fields of automotive, industry,
telecommunications, and electronic data processing [1].
The term “smart power” refers to a device that contains
built-in protection functions like short circuit protection
or peak-voltage clamping for switching off inductive
loads, in addition to the power switch [2].
Automotive smart power devices are often connected to
inductive loads like injection coils. When these
inductances are switched off, the stored inductive energy
has to be dissipated. The inductance reacts to the current
decrease by raising its terminal voltage. If the DUT is
unprotected, voltage and energy are limited by the
avalanche capability of the device. To prevent the device
from entering the avalanche mode, a Zener clamping
structure is typically implemented as a protection
function (see Figure 1). The clamping voltage (Vclamp) is
higher than the operating voltage (VDD) but lower than
the breakdown voltage of the device. [3,4]
Figure 1. Switching of inductive loads with smart
power devices
The energy dissipated in the power switch during an
ideal inductive turn-off (i.e. neglecting series resistance)
is described in Eq. (1).
L I max 2  Vclamp 

E (1)
2  Vclamp  VDD 
 
In this ideal case, the current Imax trough the DUT
decreases linearly during tclamp. The corresponding
clamping time is calculated in Eq. (2) [4].
L I max
t clamp  (2)
Vclamp  VDD
2 Testing the Clamping Capability
Destructive single pulse stress tests on integrated power
switches have to be performed to define the SOA. There
are multiple methods for acquiring information about the
maximum energy capability of DUTs. A generalized
analytical approach valid for arbitrary pulse shapes and
based on technological properties of the semiconductor
would require knowledge of the transient device
temperature during the power pulse, as destruction of the
power DMOS is related to its peak junction temperature.
However this is not directly measurable and thus needs
to be computed from a thermal model, usually by FEM
(finite element method) simulation [5]. – Two empirical
techniques to determine the SOA for application relevant
pulse shapes, relying solely on electrical measurements,
will be described in this work in paragraph 2.3 and 2.4.
The test assembly can either be built up with real coils
as described in paragraph 2.1 or can employ an
electronic load. In any case, the test circuit must be able
to provide high power and high energy during the
clamping operation. A current source unit, which meets
these demands, is presented in paragraph 2.2.
2.1 Clamping Test Configuration for applying
Application Relevant Stress Pulses
A method for testing the clamping behavior and
evaluating the SOA with application relevant high power
stress pulses is illustrated in Figure 2. [6]
The load current amplitude is defined by the on-time of
the DUT. When the device is switched off, the inductive
load raises the drain voltage up to the Zener breakdown
level Vclamp. The switch S is toggled from position 1 to
position 2 simultaneously to disconnect the power
supply, in order to provide a well-defined initial
clamping condition (VDD = 0 V).
Figure 2. Basic circuit for testing the clamping
behavior and evaluating the SOA of a power
transistor during inductive switching
Testing different stress conditions requires extra
hardware effort, as several different inductances have to
be provided.
2.2 Energy Ramp-Up Test Bench for Advanced
Stress Pulses Definition
The ERU test bench in Figure 3 consists of
a) a PC with a built-in FPGA card for controlling
the test system
b) an four channel oscilloscope
c) a controlled current source unit for applying
stress pulses to a DUT
d) a climate chamber for setting the ambient
temperature between -70 °C and +125 °C.
Figure 3. ERU test bench for single clamping
The current source unit is capable of applying an
arbitrarily shaped current pulse to the DUT. The unit can
provide up to 60 A for single pulses, the maximum
clamping voltage is 100 V. [7]
Figure 4. Block diagram of ERU test circuit
The pulse width of the injected pulse can be adjusted
between 50 µs and 100 ms at an update rate of 200 kS/s
for the reference value. The failure event detection is
implemented in the hardware of the current source unit.
Furthermore, as the source is fully floating, high side and
low side power switches can be stressed by simple
reconfiguration of the wiring. [8,9]
2.3 Pulse Width SOA Test Method
A rectangular current pulse with a fixed amplitude and
a pulse width well below the destruction limit is applied
to the DUT. After the device sustains the pulse energy,
the pulse width and therefore the pulse energy is increa-
sed and the DUT is stressed again. To obtain an accurate
value for the energy at which a DUT is destroyed, the
pulse width of the pulse is increased in minor steps.
Time between the stress pulses is chosen long enough
for the DUT to return to ambient temperature.
Figure 5. Rectangular current stress pulses
Figure 5 represents four sample stress pulses – 500 µs,
600 µs, 700 µs, and 775 µs. The DUT is destroyed after
778.5 µs or when the energy reaches 85.4 mJ. This test
was performed at an ambient temperature of +40 °C.
When testing a single device, this test method is
meaningful and sufficient. Comparing different device
groups or different design steps directly during device
development is difficult, as destruction time may vary.
2.4 Energy Ramp-Up Test
In contrast to the pulse width SOA test method, the
current pulse in the ERU test method has constant pulse
width while the current amplitude is increased.
Consequently, the energy of the pulse is ramped up.
Figure 6. Rectangular stress pulses (ERU method)
 The current amplitude is increased in 10 mA steps. In
Figure 6 only four sample stress pulses are visualized.
The destruction pulse has an energy of 236.5 mJ (test
performed at -45 °C).
As described in paragraph 2.2, the load is a controlled
current source unit and the stress pulse can take on
arbitrary shapes. For an application relevant load
condition, a triangular ramp current pulse may be
chosen.
Figure 7. Triangular ramp current pulses
The current amplitude is increased again in minor
steps. For better visualization, only four sample current
pulses are presented in Figure 7. The destruction of the
DUT is reached at 223.1 mJ or after 560 µs at an
ambient temperature of -45 °C.
A direct comparison of different device groups is
achievable with this method by applying stress pulses
with the same pulse width and at the same ambient
temperature. Furthermore, support during device
development is simplified by a standardized method.
Different design steps can easily be compared and
quantitative support can be provided, e.g. to find the
necessary minimum DMOS area required for dissipating
a given inductive energy.
3 Test Results
For the ERU tests in the course of this work,
automotive lateral n-channel DMOS transistors with a
breakdown voltage of 60 V and a chip area of 1 mm²
were used. Rectangular and triangular ramp shaped
current pulses with four different pulse widths (160 µs,
340 µs, 610 µs, and 1240 µs) were applied to the DUTs
at ambient temperatures of -45 °C, +40 °C, and +125 °C.
Figure 8. Comparison of triangular ramp and
rectangular shaped pulses
During the destructive tests the clamping voltage and
the current is measured and analyzed. The pulse power
and energy is calculated for each pulse. For short pulses,
the maximum energy capability is nearly independent of
pulse shape – a comparison for 610 µs rectangular and
triangular shaped pulses is shown in Figure 8. The
following analyses are therefore limited to a set of
rectangular stress pulses.
3.1 Pulse Energy over Pulse Width
Since the current is ramped up in minor steps, the
energy level of the last non-destructive pulse can be used
in order to obtain the SOA limit. Measured energy
values are displayed in Figure 9 for the given set of pulse
widths and temperatures. As the diagram employs a
double logarithmic scale, the trend lines appear linear,
indicating a power law relationship [10]. Energy
capability increases with pulse width, but decreases with
ambient temperature, as expected.
Figure 9. Maximum energy capability of DUTs from
the same type at three different case temperatures
The sample stress data is even sufficient to determine a
quantitative relationship for the maximum pulse energy
for pulse widths between 160 µs and 1240 µs. The
energy limit can be interpolated from the graph in
Figure 9, if the desired DUT is operated within the tested
temperature range.
3.2 Pulse Power over Case Temperature
Figure 10. Power derating curve and estimated
destruction temperature.
 Based on the assumption that the destruction
temperature is a property of the device technology and
thus independent of the applied pulse shape and width of
the destructive power pulse, a simple linearized model
based on the thermal impedance Zth may be applied
Eq. (3) [10].
T
Zth (t pulse )  (3)
Pmax
where
T  Tdestr  Tcase (P max) (4)
Tcase (Pmax) is the initial case temperature of the DUT,
before the destructive power pulse is applied. Tdestr is the
junction temperature, at which the DUT is destroyed. It
can be estimated from the common intersection point of
the power versus temperature lines in Figure 10, where
the device would hypothetically be destroyed by
applying 0 W of electrical power. Thermal impedance
for the tested pulse widths may then be calculated from
the slope of temperature versus power according to
Eq. (3). Results based on a least squares fit are shown in
Figure 11.
Figure 11. Power switch transient thermal impedance
as extracted from SOA test data
With this approach, the destruction temperature at the
common intersection for the described pulse set was
found to be about 420 °C. Based on the knowledge of the
destruction temperature and thermal impedances, the
SOA for the tested device type may be predicted for
arbitrary operating points around the measured range of
test pulses and ambient temperatures between -45 °C and
+125 °C.
4 Conclusion
A high power and high energy test circuit for testing the
clamping capability of smart power devices was
introduced. Based on the destruction data for a set of test
pulses applied to DUTs under a well defined
environment, the thermal impedance model was used to
estimate the destruction temperature. A method for
defining the SOA over a wide temperature range for
devices of the same type was proposed.
Acknowledgements
The Federal Ministry of Economics and Labor of the
Republic of Austria and the Carinthia Economic Fund
(KWF) jointly funded this work.
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